1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 ARM_MAP_TSP_SEC_MEM, 83 #if TRUSTED_BOARD_BOOT 84 /* To access the Root of Trust Public Key registers. */ 85 MAP_DEVICE2, 86 #endif 87 #if ARM_BL31_IN_DRAM 88 ARM_MAP_BL31_SEC_DRAM, 89 #endif 90 {0} 91 }; 92 #endif 93 #ifdef IMAGE_BL2U 94 const mmap_region_t plat_arm_mmap[] = { 95 MAP_DEVICE0, 96 V2M_MAP_IOFPGA, 97 {0} 98 }; 99 #endif 100 #ifdef IMAGE_BL31 101 const mmap_region_t plat_arm_mmap[] = { 102 ARM_MAP_SHARED_RAM, 103 V2M_MAP_IOFPGA, 104 MAP_DEVICE0, 105 MAP_DEVICE1, 106 {0} 107 }; 108 #endif 109 #ifdef IMAGE_BL32 110 const mmap_region_t plat_arm_mmap[] = { 111 #ifdef AARCH32 112 ARM_MAP_SHARED_RAM, 113 #endif 114 V2M_MAP_IOFPGA, 115 MAP_DEVICE0, 116 MAP_DEVICE1, 117 {0} 118 }; 119 #endif 120 121 ARM_CASSERT_MMAP 122 123 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 124 static const int fvp_cci400_map[] = { 125 PLAT_FVP_CCI400_CLUS0_SL_PORT, 126 PLAT_FVP_CCI400_CLUS1_SL_PORT, 127 }; 128 129 static const int fvp_cci5xx_map[] = { 130 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 131 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 132 }; 133 134 static unsigned int get_interconnect_master(void) 135 { 136 unsigned int master; 137 u_register_t mpidr; 138 139 mpidr = read_mpidr_el1(); 140 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 141 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 142 143 assert(master < FVP_CLUSTER_COUNT); 144 return master; 145 } 146 #endif 147 148 /******************************************************************************* 149 * A single boot loader stack is expected to work on both the Foundation FVP 150 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 151 * SYS_ID register provides a mechanism for detecting the differences between 152 * these platforms. This information is stored in a per-BL array to allow the 153 * code to take the correct path.Per BL platform configuration. 154 ******************************************************************************/ 155 void fvp_config_setup(void) 156 { 157 unsigned int rev, hbi, bld, arch, sys_id; 158 159 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 160 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 161 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 162 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 163 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 164 165 if (arch != ARCH_MODEL) { 166 ERROR("This firmware is for FVP models\n"); 167 panic(); 168 } 169 170 /* 171 * The build field in the SYS_ID tells which variant of the GIC 172 * memory is implemented by the model. 173 */ 174 switch (bld) { 175 case BLD_GIC_VE_MMAP: 176 ERROR("Legacy Versatile Express memory map for GIC peripheral" 177 " is not supported\n"); 178 panic(); 179 break; 180 case BLD_GIC_A53A57_MMAP: 181 break; 182 default: 183 ERROR("Unsupported board build %x\n", bld); 184 panic(); 185 } 186 187 /* 188 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 189 * for the Foundation FVP. 190 */ 191 switch (hbi) { 192 case HBI_FOUNDATION_FVP: 193 arm_config.flags = 0; 194 195 /* 196 * Check for supported revisions of Foundation FVP 197 * Allow future revisions to run but emit warning diagnostic 198 */ 199 switch (rev) { 200 case REV_FOUNDATION_FVP_V2_0: 201 case REV_FOUNDATION_FVP_V2_1: 202 case REV_FOUNDATION_FVP_v9_1: 203 case REV_FOUNDATION_FVP_v9_6: 204 break; 205 default: 206 WARN("Unrecognized Foundation FVP revision %x\n", rev); 207 break; 208 } 209 break; 210 case HBI_BASE_FVP: 211 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 212 213 /* 214 * Check for supported revisions 215 * Allow future revisions to run but emit warning diagnostic 216 */ 217 switch (rev) { 218 case REV_BASE_FVP_V0: 219 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 220 break; 221 case REV_BASE_FVP_REVC: 222 arm_config.flags |= (ARM_CONFIG_FVP_SHIFTED_AFF | 223 ARM_CONFIG_FVP_HAS_SMMUV3 | 224 ARM_CONFIG_FVP_HAS_CCI5XX); 225 break; 226 default: 227 WARN("Unrecognized Base FVP revision %x\n", rev); 228 break; 229 } 230 break; 231 default: 232 ERROR("Unsupported board HBI number 0x%x\n", hbi); 233 panic(); 234 } 235 } 236 237 238 void fvp_interconnect_init(void) 239 { 240 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 241 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 242 ERROR("Unrecognized CCN variant detected. Only CCN-502" 243 " is supported"); 244 panic(); 245 } 246 247 plat_arm_interconnect_init(); 248 #else 249 uintptr_t cci_base = 0; 250 const int *cci_map = 0; 251 unsigned int map_size = 0; 252 253 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 254 ARM_CONFIG_FVP_HAS_CCI5XX))) { 255 return; 256 } 257 258 /* Initialize the right interconnect */ 259 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 260 cci_base = PLAT_FVP_CCI5XX_BASE; 261 cci_map = fvp_cci5xx_map; 262 map_size = ARRAY_SIZE(fvp_cci5xx_map); 263 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 264 cci_base = PLAT_FVP_CCI400_BASE; 265 cci_map = fvp_cci400_map; 266 map_size = ARRAY_SIZE(fvp_cci400_map); 267 } 268 269 assert(cci_base); 270 assert(cci_map); 271 cci_init(cci_base, cci_map, map_size); 272 #endif 273 } 274 275 void fvp_interconnect_enable(void) 276 { 277 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 278 plat_arm_interconnect_enter_coherency(); 279 #else 280 unsigned int master; 281 282 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 283 ARM_CONFIG_FVP_HAS_CCI5XX)) { 284 master = get_interconnect_master(); 285 cci_enable_snoop_dvm_reqs(master); 286 } 287 #endif 288 } 289 290 void fvp_interconnect_disable(void) 291 { 292 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 293 plat_arm_interconnect_exit_coherency(); 294 #else 295 unsigned int master; 296 297 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 298 ARM_CONFIG_FVP_HAS_CCI5XX)) { 299 master = get_interconnect_master(); 300 cci_disable_snoop_dvm_reqs(master); 301 } 302 #endif 303 } 304