1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <sys/types.h> 14 #include <utils.h> 15 #include <utils_def.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 #if defined(IMAGE_BL1) || defined(IMAGE_BL31) 20 # define IMAGE_EL 3 21 #else 22 # define IMAGE_EL 1 23 #endif 24 25 static unsigned long long calc_physical_addr_size_bits( 26 unsigned long long max_addr) 27 { 28 /* Physical address can't exceed 48 bits */ 29 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 30 31 /* 48 bits address */ 32 if (max_addr & ADDR_MASK_44_TO_47) 33 return TCR_PS_BITS_256TB; 34 35 /* 44 bits address */ 36 if (max_addr & ADDR_MASK_42_TO_43) 37 return TCR_PS_BITS_16TB; 38 39 /* 42 bits address */ 40 if (max_addr & ADDR_MASK_40_TO_41) 41 return TCR_PS_BITS_4TB; 42 43 /* 40 bits address */ 44 if (max_addr & ADDR_MASK_36_TO_39) 45 return TCR_PS_BITS_1TB; 46 47 /* 36 bits address */ 48 if (max_addr & ADDR_MASK_32_TO_35) 49 return TCR_PS_BITS_64GB; 50 51 return TCR_PS_BITS_4GB; 52 } 53 54 #if ENABLE_ASSERTIONS 55 /* Physical Address ranges supported in the AArch64 Memory Model */ 56 static const unsigned int pa_range_bits_arr[] = { 57 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 58 PARANGE_0101 59 }; 60 61 unsigned long long xlat_arch_get_max_supported_pa(void) 62 { 63 u_register_t pa_range = read_id_aa64mmfr0_el1() & 64 ID_AA64MMFR0_EL1_PARANGE_MASK; 65 66 /* All other values are reserved */ 67 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 68 69 return (1ull << pa_range_bits_arr[pa_range]) - 1ull; 70 } 71 #endif /* ENABLE_ASSERTIONS*/ 72 73 int is_mmu_enabled(void) 74 { 75 #if IMAGE_EL == 1 76 assert(IS_IN_EL(1)); 77 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 78 #elif IMAGE_EL == 3 79 assert(IS_IN_EL(3)); 80 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 81 #endif 82 } 83 84 void xlat_arch_tlbi_va(uintptr_t va) 85 { 86 /* 87 * Ensure the translation table write has drained into memory before 88 * invalidating the TLB entry. 89 */ 90 dsbishst(); 91 92 #if IMAGE_EL == 1 93 assert(IS_IN_EL(1)); 94 tlbivaae1is(TLBI_ADDR(va)); 95 #elif IMAGE_EL == 3 96 assert(IS_IN_EL(3)); 97 tlbivae3is(TLBI_ADDR(va)); 98 #endif 99 } 100 101 void xlat_arch_tlbi_va_sync(void) 102 { 103 /* 104 * A TLB maintenance instruction can complete at any time after 105 * it is issued, but is only guaranteed to be complete after the 106 * execution of DSB by the PE that executed the TLB maintenance 107 * instruction. After the TLB invalidate instruction is 108 * complete, no new memory accesses using the invalidated TLB 109 * entries will be observed by any observer of the system 110 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 111 * "Ordering and completion of TLB maintenance instructions". 112 */ 113 dsbish(); 114 115 /* 116 * The effects of a completed TLB maintenance instruction are 117 * only guaranteed to be visible on the PE that executed the 118 * instruction after the execution of an ISB instruction by the 119 * PE that executed the TLB maintenance instruction. 120 */ 121 isb(); 122 } 123 124 int xlat_arch_current_el(void) 125 { 126 int el = GET_EL(read_CurrentEl()); 127 128 assert(el > 0); 129 130 return el; 131 } 132 133 uint64_t xlat_arch_get_xn_desc(int el) 134 { 135 if (el == 3) { 136 return UPPER_ATTRS(XN); 137 } else { 138 assert(el == 1); 139 return UPPER_ATTRS(PXN); 140 } 141 } 142 143 /******************************************************************************* 144 * Macro generating the code for the function enabling the MMU in the given 145 * exception level, assuming that the pagetables have already been created. 146 * 147 * _el: Exception level at which the function will run 148 * _tlbi_fct: Function to invalidate the TLBs at the current 149 * exception level 150 ******************************************************************************/ 151 #define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ 152 static void enable_mmu_internal_el##_el(int flags, \ 153 uint64_t mair, \ 154 uint64_t tcr, \ 155 uint64_t ttbr) \ 156 { \ 157 uint32_t sctlr = read_sctlr_el##_el(); \ 158 assert((sctlr & SCTLR_M_BIT) == 0); \ 159 \ 160 /* Invalidate TLBs at the current exception level */ \ 161 _tlbi_fct(); \ 162 \ 163 write_mair_el##_el(mair); \ 164 write_tcr_el##_el(tcr); \ 165 \ 166 /* Set TTBR bits as well */ \ 167 if (ARM_ARCH_AT_LEAST(8, 2)) { \ 168 /* Enable CnP bit so as to share page tables */ \ 169 /* with all PEs. This is mandatory for */ \ 170 /* ARMv8.2 implementations. */ \ 171 ttbr |= TTBR_CNP_BIT; \ 172 } \ 173 write_ttbr0_el##_el(ttbr); \ 174 \ 175 /* Ensure all translation table writes have drained */ \ 176 /* into memory, the TLB invalidation is complete, */ \ 177 /* and translation register writes are committed */ \ 178 /* before enabling the MMU */ \ 179 dsbish(); \ 180 isb(); \ 181 \ 182 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 183 if (flags & DISABLE_DCACHE) \ 184 sctlr &= ~SCTLR_C_BIT; \ 185 else \ 186 sctlr |= SCTLR_C_BIT; \ 187 \ 188 write_sctlr_el##_el(sctlr); \ 189 \ 190 /* Ensure the MMU enable takes effect immediately */ \ 191 isb(); \ 192 } 193 194 /* Define EL1 and EL3 variants of the function enabling the MMU */ 195 #if IMAGE_EL == 1 196 DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) 197 #elif IMAGE_EL == 3 198 DEFINE_ENABLE_MMU_EL(3, tlbialle3) 199 #endif 200 201 void enable_mmu_arch(unsigned int flags, 202 uint64_t *base_table, 203 unsigned long long max_pa, 204 uintptr_t max_va) 205 { 206 uint64_t mair, ttbr, tcr; 207 208 /* Set attributes in the right indices of the MAIR. */ 209 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 210 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 211 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 212 213 ttbr = (uint64_t) base_table; 214 215 /* 216 * Set TCR bits as well. 217 */ 218 219 /* 220 * Limit the input address ranges and memory region sizes translated 221 * using TTBR0 to the given virtual address space size. 222 */ 223 assert(max_va < UINTPTR_MAX); 224 uintptr_t virtual_addr_space_size = max_va + 1; 225 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 226 /* 227 * __builtin_ctzll(0) is undefined but here we are guaranteed that 228 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 229 */ 230 tcr = 64 - __builtin_ctzll(virtual_addr_space_size); 231 232 /* 233 * Set the cacheability and shareability attributes for memory 234 * associated with translation table walks. 235 */ 236 if (flags & XLAT_TABLE_NC) { 237 /* Inner & outer non-cacheable non-shareable. */ 238 tcr |= TCR_SH_NON_SHAREABLE | 239 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 240 } else { 241 /* Inner & outer WBWA & shareable. */ 242 tcr |= TCR_SH_INNER_SHAREABLE | 243 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 244 } 245 246 /* 247 * It is safer to restrict the max physical address accessible by the 248 * hardware as much as possible. 249 */ 250 unsigned long long tcr_ps_bits = calc_physical_addr_size_bits(max_pa); 251 252 #if IMAGE_EL == 1 253 assert(IS_IN_EL(1)); 254 /* 255 * TCR_EL1.EPD1: Disable translation table walk for addresses that are 256 * translated using TTBR1_EL1. 257 */ 258 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 259 enable_mmu_internal_el1(flags, mair, tcr, ttbr); 260 #elif IMAGE_EL == 3 261 assert(IS_IN_EL(3)); 262 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 263 enable_mmu_internal_el3(flags, mair, tcr, ttbr); 264 #endif 265 } 266