1ARM Trusted Firmware Porting Guide 2================================== 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting the ARM Trusted Firmware to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard ARM platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39ARM standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the ARM Trusted Firmware 47`User Guide`_. 48 49Common modifications 50-------------------- 51 52This section covers the modifications that should be made by the platform for 53each BL stage to correctly port the firmware stack. They are categorized as 54either mandatory or optional. 55 56Common mandatory modifications 57------------------------------ 58 59A platform port must enable the Memory Management Unit (MMU) as well as the 60instruction and data caches for each BL stage. Setting up the translation 61tables is the responsibility of the platform port because memory maps differ 62across platforms. A memory translation library (see ``lib/xlat_tables/``) is 63provided to help in this setup. 64 65Note that although this library supports non-identity mappings, this is intended 66only for re-mapping peripheral physical addresses and allows platforms with high 67I/O addresses to reduce their virtual address space. All other addresses 68corresponding to code and data must currently use an identity mapping. 69 70Also, the only translation granule size supported in Trusted Firmware is 4KB, as 71various parts of the code assume that is the case. It is not possible to switch 72to 16 KB or 64 KB granule sizes at the moment. 73 74In ARM standard platforms, each BL stage configures the MMU in the 75platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 76an identity mapping for all addresses. 77 78If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 79block of identity mapped secure memory with Device-nGnRE attributes aligned to 80page boundary (4K) for each BL stage. All sections which allocate coherent 81memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 82section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 83possible for the firmware to place variables in it using the following C code 84directive: 85 86:: 87 88 __section("bakery_lock") 89 90Or alternatively the following assembler code directive: 91 92:: 93 94 .section bakery_lock 95 96The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 97used to allocate any data structures that are accessed both when a CPU is 98executing with its MMU and caches enabled, and when it's running with its MMU 99and caches disabled. Examples are given below. 100 101The following variables, functions and constants must be defined by the platform 102for the firmware to work correctly. 103 104File : platform\_def.h [mandatory] 105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 106 107Each platform must ensure that a header file of this name is in the system 108include path with the following constants defined. This may require updating the 109list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the ARM development 110platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 111 112Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 113which provides typical values for some of the constants below. These values are 114likely to be suitable for all platform ports. 115 116Platform ports that want to be aligned with standard ARM platforms (for example 117FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 118standard values for some of the constants below. However, this requires the 119platform port to define additional platform porting constants in 120``platform_def.h``. These additional constants are not documented here. 121 122- **#define : PLATFORM\_LINKER\_FORMAT** 123 124 Defines the linker format used by the platform, for example 125 ``elf64-littleaarch64``. 126 127- **#define : PLATFORM\_LINKER\_ARCH** 128 129 Defines the processor architecture for the linker by the platform, for 130 example ``aarch64``. 131 132- **#define : PLATFORM\_STACK\_SIZE** 133 134 Defines the normal stack memory available to each CPU. This constant is used 135 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 136 `plat/common/aarch64/platform\_up\_stack.S`_. 137 138- **define : CACHE\_WRITEBACK\_GRANULE** 139 140 Defines the size in bits of the largest cache line across all the cache 141 levels in the platform. 142 143- **#define : FIRMWARE\_WELCOME\_STR** 144 145 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 146 function. 147 148- **#define : PLATFORM\_CORE\_COUNT** 149 150 Defines the total number of CPUs implemented by the platform across all 151 clusters in the system. 152 153- **#define : PLAT\_NUM\_PWR\_DOMAINS** 154 155 Defines the total number of nodes in the power domain topology 156 tree at all the power domain levels used by the platform. 157 This macro is used by the PSCI implementation to allocate 158 data structures to represent power domain topology. 159 160- **#define : PLAT\_MAX\_PWR\_LVL** 161 162 Defines the maximum power domain level that the power management operations 163 should apply to. More often, but not always, the power domain level 164 corresponds to affinity level. This macro allows the PSCI implementation 165 to know the highest power domain level that it should consider for power 166 management operations in the system that the platform implements. For 167 example, the Base AEM FVP implements two clusters with a configurable 168 number of CPUs and it reports the maximum power domain level as 1. 169 170- **#define : PLAT\_MAX\_OFF\_STATE** 171 172 Defines the local power state corresponding to the deepest power down 173 possible at every power domain level in the platform. The local power 174 states for each level may be sparsely allocated between 0 and this value 175 with 0 being reserved for the RUN state. The PSCI implementation uses this 176 value to initialize the local power states of the power domain nodes and 177 to specify the requested power state for a PSCI\_CPU\_OFF call. 178 179- **#define : PLAT\_MAX\_RET\_STATE** 180 181 Defines the local power state corresponding to the deepest retention state 182 possible at every power domain level in the platform. This macro should be 183 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 184 PSCI implementation to distinguish between retention and power down local 185 power states within PSCI\_CPU\_SUSPEND call. 186 187- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 188 189 Defines the maximum number of local power states per power domain level 190 that the platform supports. The default value of this macro is 2 since 191 most platforms just support a maximum of two local power states at each 192 power domain level (power-down and retention). If the platform needs to 193 account for more local power states, then it must redefine this macro. 194 195 Currently, this macro is used by the Generic PSCI implementation to size 196 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 197 198- **#define : BL1\_RO\_BASE** 199 200 Defines the base address in secure ROM where BL1 originally lives. Must be 201 aligned on a page-size boundary. 202 203- **#define : BL1\_RO\_LIMIT** 204 205 Defines the maximum address in secure ROM that BL1's actual content (i.e. 206 excluding any data section allocated at runtime) can occupy. 207 208- **#define : BL1\_RW\_BASE** 209 210 Defines the base address in secure RAM where BL1's read-write data will live 211 at runtime. Must be aligned on a page-size boundary. 212 213- **#define : BL1\_RW\_LIMIT** 214 215 Defines the maximum address in secure RAM that BL1's read-write data can 216 occupy at runtime. 217 218- **#define : BL2\_BASE** 219 220 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 221 Must be aligned on a page-size boundary. 222 223- **#define : BL2\_LIMIT** 224 225 Defines the maximum address in secure RAM that the BL2 image can occupy. 226 227- **#define : BL31\_BASE** 228 229 Defines the base address in secure RAM where BL2 loads the BL31 binary 230 image. Must be aligned on a page-size boundary. 231 232- **#define : BL31\_LIMIT** 233 234 Defines the maximum address in secure RAM that the BL31 image can occupy. 235 236For every image, the platform must define individual identifiers that will be 237used by BL1 or BL2 to load the corresponding image into memory from non-volatile 238storage. For the sake of performance, integer numbers will be used as 239identifiers. The platform will use those identifiers to return the relevant 240information about the image to be loaded (file handler, load address, 241authentication information, etc.). The following image identifiers are 242mandatory: 243 244- **#define : BL2\_IMAGE\_ID** 245 246 BL2 image identifier, used by BL1 to load BL2. 247 248- **#define : BL31\_IMAGE\_ID** 249 250 BL31 image identifier, used by BL2 to load BL31. 251 252- **#define : BL33\_IMAGE\_ID** 253 254 BL33 image identifier, used by BL2 to load BL33. 255 256If Trusted Board Boot is enabled, the following certificate identifiers must 257also be defined: 258 259- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 260 261 BL2 content certificate identifier, used by BL1 to load the BL2 content 262 certificate. 263 264- **#define : TRUSTED\_KEY\_CERT\_ID** 265 266 Trusted key certificate identifier, used by BL2 to load the trusted key 267 certificate. 268 269- **#define : SOC\_FW\_KEY\_CERT\_ID** 270 271 BL31 key certificate identifier, used by BL2 to load the BL31 key 272 certificate. 273 274- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 275 276 BL31 content certificate identifier, used by BL2 to load the BL31 content 277 certificate. 278 279- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 280 281 BL33 key certificate identifier, used by BL2 to load the BL33 key 282 certificate. 283 284- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 285 286 BL33 content certificate identifier, used by BL2 to load the BL33 content 287 certificate. 288 289- **#define : FWU\_CERT\_ID** 290 291 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 292 FWU content certificate. 293 294- **#define : PLAT\_CRYPTOCELL\_BASE** 295 296 This defines the base address of ARM® TrustZone® CryptoCell and must be 297 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 298 capable ARM platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 299 set. 300 301If the AP Firmware Updater Configuration image, BL2U is used, the following 302must also be defined: 303 304- **#define : BL2U\_BASE** 305 306 Defines the base address in secure memory where BL1 copies the BL2U binary 307 image. Must be aligned on a page-size boundary. 308 309- **#define : BL2U\_LIMIT** 310 311 Defines the maximum address in secure memory that the BL2U image can occupy. 312 313- **#define : BL2U\_IMAGE\_ID** 314 315 BL2U image identifier, used by BL1 to fetch an image descriptor 316 corresponding to BL2U. 317 318If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 319must also be defined: 320 321- **#define : SCP\_BL2U\_IMAGE\_ID** 322 323 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 324 corresponding to SCP\_BL2U. 325 NOTE: TF does not provide source code for this image. 326 327If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 328also be defined: 329 330- **#define : NS\_BL1U\_BASE** 331 332 Defines the base address in non-secure ROM where NS\_BL1U executes. 333 Must be aligned on a page-size boundary. 334 NOTE: TF does not provide source code for this image. 335 336- **#define : NS\_BL1U\_IMAGE\_ID** 337 338 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 339 corresponding to NS\_BL1U. 340 341If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 342be defined: 343 344- **#define : NS\_BL2U\_BASE** 345 346 Defines the base address in non-secure memory where NS\_BL2U executes. 347 Must be aligned on a page-size boundary. 348 NOTE: TF does not provide source code for this image. 349 350- **#define : NS\_BL2U\_IMAGE\_ID** 351 352 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 353 corresponding to NS\_BL2U. 354 355For the the Firmware update capability of TRUSTED BOARD BOOT, the following 356macros may also be defined: 357 358- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 359 360 Total number of images that can be loaded simultaneously. If the platform 361 doesn't specify any value, it defaults to 10. 362 363If a SCP\_BL2 image is supported by the platform, the following constants must 364also be defined: 365 366- **#define : SCP\_BL2\_IMAGE\_ID** 367 368 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 369 from platform storage before being transfered to the SCP. 370 371- **#define : SCP\_FW\_KEY\_CERT\_ID** 372 373 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 374 certificate (mandatory when Trusted Board Boot is enabled). 375 376- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 377 378 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 379 content certificate (mandatory when Trusted Board Boot is enabled). 380 381If a BL32 image is supported by the platform, the following constants must 382also be defined: 383 384- **#define : BL32\_IMAGE\_ID** 385 386 BL32 image identifier, used by BL2 to load BL32. 387 388- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 389 390 BL32 key certificate identifier, used by BL2 to load the BL32 key 391 certificate (mandatory when Trusted Board Boot is enabled). 392 393- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 394 395 BL32 content certificate identifier, used by BL2 to load the BL32 content 396 certificate (mandatory when Trusted Board Boot is enabled). 397 398- **#define : BL32\_BASE** 399 400 Defines the base address in secure memory where BL2 loads the BL32 binary 401 image. Must be aligned on a page-size boundary. 402 403- **#define : BL32\_LIMIT** 404 405 Defines the maximum address that the BL32 image can occupy. 406 407If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 408platform, the following constants must also be defined: 409 410- **#define : TSP\_SEC\_MEM\_BASE** 411 412 Defines the base address of the secure memory used by the TSP image on the 413 platform. This must be at the same address or below ``BL32_BASE``. 414 415- **#define : TSP\_SEC\_MEM\_SIZE** 416 417 Defines the size of the secure memory used by the BL32 image on the 418 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 419 the memory required by the BL32 image, defined by ``BL32_BASE`` and 420 ``BL32_LIMIT``. 421 422- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 423 424 Defines the ID of the secure physical generic timer interrupt used by the 425 TSP's interrupt handling code. 426 427If the platform port uses the translation table library code, the following 428constants must also be defined: 429 430- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 431 432 Optional flag that can be set per-image to enable the dynamic allocation of 433 regions even when the MMU is enabled. If not defined, only static 434 functionality will be available, if defined and set to 1 it will also 435 include the dynamic functionality. 436 437- **#define : MAX\_XLAT\_TABLES** 438 439 Defines the maximum number of translation tables that are allocated by the 440 translation table library code. To minimize the amount of runtime memory 441 used, choose the smallest value needed to map the required virtual addresses 442 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 443 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 444 as well. 445 446- **#define : MAX\_MMAP\_REGIONS** 447 448 Defines the maximum number of regions that are allocated by the translation 449 table library code. A region consists of physical base address, virtual base 450 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 451 defined in the ``mmap_region_t`` structure. The platform defines the regions 452 that should be mapped. Then, the translation table library will create the 453 corresponding tables and descriptors at runtime. To minimize the amount of 454 runtime memory used, choose the smallest value needed to register the 455 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 456 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 457 the dynamic regions as well. 458 459- **#define : ADDR\_SPACE\_SIZE** 460 461 Defines the total size of the address space in bytes. For example, for a 32 462 bit address space, this value should be ``(1ull << 32)``. This definition is 463 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 464 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 465 466- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 467 468 Defines the total size of the virtual address space in bytes. For example, 469 for a 32 bit virtual address space, this value should be ``(1ull << 32)``. 470 471- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 472 473 Defines the total size of the physical address space in bytes. For example, 474 for a 32 bit physical address space, this value should be ``(1ull << 32)``. 475 476If the platform port uses the IO storage framework, the following constants 477must also be defined: 478 479- **#define : MAX\_IO\_DEVICES** 480 481 Defines the maximum number of registered IO devices. Attempting to register 482 more devices than this value using ``io_register_device()`` will fail with 483 -ENOMEM. 484 485- **#define : MAX\_IO\_HANDLES** 486 487 Defines the maximum number of open IO handles. Attempting to open more IO 488 entities than this value using ``io_open()`` will fail with -ENOMEM. 489 490- **#define : MAX\_IO\_BLOCK\_DEVICES** 491 492 Defines the maximum number of registered IO block devices. Attempting to 493 register more devices this value using ``io_dev_open()`` will fail 494 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 495 With this macro, multiple block devices could be supported at the same 496 time. 497 498If the platform needs to allocate data within the per-cpu data framework in 499BL31, it should define the following macro. Currently this is only required if 500the platform decides not to use the coherent memory section by undefining the 501``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 502required memory within the the per-cpu data to minimize wastage. 503 504- **#define : PLAT\_PCPU\_DATA\_SIZE** 505 506 Defines the memory (in bytes) to be reserved within the per-cpu data 507 structure for use by the platform layer. 508 509The following constants are optional. They should be defined when the platform 510memory layout implies some image overlaying like in ARM standard platforms. 511 512- **#define : BL31\_PROGBITS\_LIMIT** 513 514 Defines the maximum address in secure RAM that the BL31's progbits sections 515 can occupy. 516 517- **#define : TSP\_PROGBITS\_LIMIT** 518 519 Defines the maximum address that the TSP's progbits sections can occupy. 520 521If the platform port uses the PL061 GPIO driver, the following constant may 522optionally be defined: 523 524- **PLAT\_PL061\_MAX\_GPIOS** 525 Maximum number of GPIOs required by the platform. This allows control how 526 much memory is allocated for PL061 GPIO controllers. The default value is 527 528 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 529 530If the platform port uses the partition driver, the following constant may 531optionally be defined: 532 533- **PLAT\_PARTITION\_MAX\_ENTRIES** 534 Maximum number of partition entries required by the platform. This allows 535 control how much memory is allocated for partition entries. The default 536 value is 128. 537 `For example, define the build flag in platform.mk`_: 538 PLAT\_PARTITION\_MAX\_ENTRIES := 12 539 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 540 541The following constant is optional. It should be defined to override the default 542behaviour of the ``assert()`` function (for example, to save memory). 543 544- **PLAT\_LOG\_LEVEL\_ASSERT** 545 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 546 ``assert()`` prints the name of the file, the line number and the asserted 547 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 548 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 549 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 550 defined, it defaults to ``LOG_LEVEL``. 551 552File : plat\_macros.S [mandatory] 553~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 554 555Each platform must ensure a file of this name is in the system include path with 556the following macro defined. In the ARM development platforms, this file is 557found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 558 559- **Macro : plat\_crash\_print\_regs** 560 561 This macro allows the crash reporting routine to print relevant platform 562 registers in case of an unhandled exception in BL31. This aids in debugging 563 and this macro can be defined to be empty in case register reporting is not 564 desired. 565 566 For instance, GIC or interconnect registers may be helpful for 567 troubleshooting. 568 569Handling Reset 570-------------- 571 572BL1 by default implements the reset vector where execution starts from a cold 573or warm boot. BL31 can be optionally set as a reset vector using the 574``RESET_TO_BL31`` make variable. 575 576For each CPU, the reset vector code is responsible for the following tasks: 577 578#. Distinguishing between a cold boot and a warm boot. 579 580#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 581 the CPU is placed in a platform-specific state until the primary CPU 582 performs the necessary steps to remove it from this state. 583 584#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 585 specific address in the BL31 image in the same processor mode as it was 586 when released from reset. 587 588The following functions need to be implemented by the platform port to enable 589reset vector code to perform the above tasks. 590 591Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 592~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 593 594:: 595 596 Argument : void 597 Return : uintptr_t 598 599This function is called with the MMU and caches disabled 600(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 601distinguishing between a warm and cold reset for the current CPU using 602platform-specific means. If it's a warm reset, then it returns the warm 603reset entrypoint point provided to ``plat_setup_psci_ops()`` during 604BL31 initialization. If it's a cold reset then this function must return zero. 605 606This function does not follow the Procedure Call Standard used by the 607Application Binary Interface for the ARM 64-bit architecture. The caller should 608not assume that callee saved registers are preserved across a call to this 609function. 610 611This function fulfills requirement 1 and 3 listed above. 612 613Note that for platforms that support programming the reset address, it is 614expected that a CPU will start executing code directly at the right address, 615both on a cold and warm reset. In this case, there is no need to identify the 616type of reset nor to query the warm reset entrypoint. Therefore, implementing 617this function is not required on such platforms. 618 619Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 620~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 621 622:: 623 624 Argument : void 625 626This function is called with the MMU and data caches disabled. It is responsible 627for placing the executing secondary CPU in a platform-specific state until the 628primary CPU performs the necessary actions to bring it out of that state and 629allow entry into the OS. This function must not return. 630 631In the ARM FVP port, when using the normal boot flow, each secondary CPU powers 632itself off. The primary CPU is responsible for powering up the secondary CPUs 633when normal world software requires them. When booting an EL3 payload instead, 634they stay powered on and are put in a holding pen until their mailbox gets 635populated. 636 637This function fulfills requirement 2 above. 638 639Note that for platforms that can't release secondary CPUs out of reset, only the 640primary CPU will execute the cold boot code. Therefore, implementing this 641function is not required on such platforms. 642 643Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 645 646:: 647 648 Argument : void 649 Return : unsigned int 650 651This function identifies whether the current CPU is the primary CPU or a 652secondary CPU. A return value of zero indicates that the CPU is not the 653primary CPU, while a non-zero return value indicates that the CPU is the 654primary CPU. 655 656Note that for platforms that can't release secondary CPUs out of reset, only the 657primary CPU will execute the cold boot code. Therefore, there is no need to 658distinguish between primary and secondary CPUs and implementing this function is 659not required. 660 661Function : platform\_mem\_init() [mandatory] 662~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 663 664:: 665 666 Argument : void 667 Return : void 668 669This function is called before any access to data is made by the firmware, in 670order to carry out any essential memory initialization. 671 672Function: plat\_get\_rotpk\_info() 673~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 674 675:: 676 677 Argument : void *, void **, unsigned int *, unsigned int * 678 Return : int 679 680This function is mandatory when Trusted Board Boot is enabled. It returns a 681pointer to the ROTPK stored in the platform (or a hash of it) and its length. 682The ROTPK must be encoded in DER format according to the following ASN.1 683structure: 684 685:: 686 687 AlgorithmIdentifier ::= SEQUENCE { 688 algorithm OBJECT IDENTIFIER, 689 parameters ANY DEFINED BY algorithm OPTIONAL 690 } 691 692 SubjectPublicKeyInfo ::= SEQUENCE { 693 algorithm AlgorithmIdentifier, 694 subjectPublicKey BIT STRING 695 } 696 697In case the function returns a hash of the key: 698 699:: 700 701 DigestInfo ::= SEQUENCE { 702 digestAlgorithm AlgorithmIdentifier, 703 digest OCTET STRING 704 } 705 706The function returns 0 on success. Any other value is treated as error by the 707Trusted Board Boot. The function also reports extra information related 708to the ROTPK in the flags parameter: 709 710:: 711 712 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 713 hash. 714 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 715 verification while the platform ROTPK is not deployed. 716 When this flag is set, the function does not need to 717 return a platform ROTPK, and the authentication 718 framework uses the ROTPK in the certificate without 719 verifying it against the platform value. This flag 720 must not be used in a deployed production environment. 721 722Function: plat\_get\_nv\_ctr() 723~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 724 725:: 726 727 Argument : void *, unsigned int * 728 Return : int 729 730This function is mandatory when Trusted Board Boot is enabled. It returns the 731non-volatile counter value stored in the platform in the second argument. The 732cookie in the first argument may be used to select the counter in case the 733platform provides more than one (for example, on platforms that use the default 734TBBR CoT, the cookie will correspond to the OID values defined in 735TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 736 737The function returns 0 on success. Any other value means the counter value could 738not be retrieved from the platform. 739 740Function: plat\_set\_nv\_ctr() 741~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 742 743:: 744 745 Argument : void *, unsigned int 746 Return : int 747 748This function is mandatory when Trusted Board Boot is enabled. It sets a new 749counter value in the platform. The cookie in the first argument may be used to 750select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 751the updated counter value to be written to the NV counter. 752 753The function returns 0 on success. Any other value means the counter value could 754not be updated. 755 756Function: plat\_set\_nv\_ctr2() 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void *, const auth_img_desc_t *, unsigned int 762 Return : int 763 764This function is optional when Trusted Board Boot is enabled. If this 765interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 766first argument passed is a cookie and is typically used to 767differentiate between a Non Trusted NV Counter and a Trusted NV 768Counter. The second argument is a pointer to an authentication image 769descriptor and may be used to decide if the counter is allowed to be 770updated or not. The third argument is the updated counter value to 771be written to the NV counter. 772 773The function returns 0 on success. Any other value means the counter value 774either could not be updated or the authentication image descriptor indicates 775that it is not allowed to be updated. 776 777Common mandatory function modifications 778--------------------------------------- 779 780The following functions are mandatory functions which need to be implemented 781by the platform port. 782 783Function : plat\_my\_core\_pos() 784~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 785 786:: 787 788 Argument : void 789 Return : unsigned int 790 791This funtion returns the index of the calling CPU which is used as a 792CPU-specific linear index into blocks of memory (for example while allocating 793per-CPU stacks). This function will be invoked very early in the 794initialization sequence which mandates that this function should be 795implemented in assembly and should not rely on the avalability of a C 796runtime environment. This function can clobber x0 - x8 and must preserve 797x9 - x29. 798 799This function plays a crucial role in the power domain topology framework in 800PSCI and details of this can be found in `Power Domain Topology Design`_. 801 802Function : plat\_core\_pos\_by\_mpidr() 803~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 804 805:: 806 807 Argument : u_register_t 808 Return : int 809 810This function validates the ``MPIDR`` of a CPU and converts it to an index, 811which can be used as a CPU-specific linear index into blocks of memory. In 812case the ``MPIDR`` is invalid, this function returns -1. This function will only 813be invoked by BL31 after the power domain topology is initialized and can 814utilize the C runtime environment. For further details about how ARM Trusted 815Firmware represents the power domain topology and how this relates to the 816linear CPU index, please refer `Power Domain Topology Design`_. 817 818Common optional modifications 819----------------------------- 820 821The following are helper functions implemented by the firmware that perform 822common platform-specific tasks. A platform may choose to override these 823definitions. 824 825Function : plat\_set\_my\_stack() 826~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 827 828:: 829 830 Argument : void 831 Return : void 832 833This function sets the current stack pointer to the normal memory stack that 834has been allocated for the current CPU. For BL images that only require a 835stack for the primary CPU, the UP version of the function is used. The size 836of the stack allocated to each CPU is specified by the platform defined 837constant ``PLATFORM_STACK_SIZE``. 838 839Common implementations of this function for the UP and MP BL images are 840provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 841`plat/common/aarch64/platform\_mp\_stack.S`_ 842 843Function : plat\_get\_my\_stack() 844~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 845 846:: 847 848 Argument : void 849 Return : uintptr_t 850 851This function returns the base address of the normal memory stack that 852has been allocated for the current CPU. For BL images that only require a 853stack for the primary CPU, the UP version of the function is used. The size 854of the stack allocated to each CPU is specified by the platform defined 855constant ``PLATFORM_STACK_SIZE``. 856 857Common implementations of this function for the UP and MP BL images are 858provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 859`plat/common/aarch64/platform\_mp\_stack.S`_ 860 861Function : plat\_report\_exception() 862~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 863 864:: 865 866 Argument : unsigned int 867 Return : void 868 869A platform may need to report various information about its status when an 870exception is taken, for example the current exception level, the CPU security 871state (secure/non-secure), the exception type, and so on. This function is 872called in the following circumstances: 873 874- In BL1, whenever an exception is taken. 875- In BL2, whenever an exception is taken. 876 877The default implementation doesn't do anything, to avoid making assumptions 878about the way the platform displays its status information. 879 880For AArch64, this function receives the exception type as its argument. 881Possible values for exceptions types are listed in the 882`include/common/bl\_common.h`_ header file. Note that these constants are not 883related to any architectural exception code; they are just an ARM Trusted 884Firmware convention. 885 886For AArch32, this function receives the exception mode as its argument. 887Possible values for exception modes are listed in the 888`include/lib/aarch32/arch.h`_ header file. 889 890Function : plat\_reset\_handler() 891~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 892 893:: 894 895 Argument : void 896 Return : void 897 898A platform may need to do additional initialization after reset. This function 899allows the platform to do the platform specific intializations. Platform 900specific errata workarounds could also be implemented here. The api should 901preserve the values of callee saved registers x19 to x29. 902 903The default implementation doesn't do anything. If a platform needs to override 904the default implementation, refer to the `Firmware Design`_ for general 905guidelines. 906 907Function : plat\_disable\_acp() 908~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 909 910:: 911 912 Argument : void 913 Return : void 914 915This api allows a platform to disable the Accelerator Coherency Port (if 916present) during a cluster power down sequence. The default weak implementation 917doesn't do anything. Since this api is called during the power down sequence, 918it has restrictions for stack usage and it can use the registers x0 - x17 as 919scratch registers. It should preserve the value in x18 register as it is used 920by the caller to store the return address. 921 922Function : plat\_error\_handler() 923~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 924 925:: 926 927 Argument : int 928 Return : void 929 930This API is called when the generic code encounters an error situation from 931which it cannot continue. It allows the platform to perform error reporting or 932recovery actions (for example, reset the system). This function must not return. 933 934The parameter indicates the type of error using standard codes from ``errno.h``. 935Possible errors reported by the generic code are: 936 937- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 938 Board Boot is enabled) 939- ``-ENOENT``: the requested image or certificate could not be found or an IO 940 error was detected 941- ``-ENOMEM``: resources exhausted. Trusted Firmware does not use dynamic 942 memory, so this error is usually an indication of an incorrect array size 943 944The default implementation simply spins. 945 946Function : plat\_panic\_handler() 947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 948 949:: 950 951 Argument : void 952 Return : void 953 954This API is called when the generic code encounters an unexpected error 955situation from which it cannot recover. This function must not return, 956and must be implemented in assembly because it may be called before the C 957environment is initialized. 958 959Note: The address from where it was called is stored in x30 (Link Register). 960The default implementation simply spins. 961 962Function : plat\_get\_bl\_image\_load\_info() 963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965:: 966 967 Argument : void 968 Return : bl_load_info_t * 969 970This function returns pointer to the list of images that the platform has 971populated to load. This function is currently invoked in BL2 to load the 972BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 973 974Function : plat\_get\_next\_bl\_params() 975~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 976 977:: 978 979 Argument : void 980 Return : bl_params_t * 981 982This function returns a pointer to the shared memory that the platform has 983kept aside to pass trusted firmware related information that next BL image 984needs. This function is currently invoked in BL2 to pass this information to 985the next BL image, when LOAD\_IMAGE\_V2 is enabled. 986 987Function : plat\_get\_stack\_protector\_canary() 988~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 989 990:: 991 992 Argument : void 993 Return : u_register_t 994 995This function returns a random value that is used to initialize the canary used 996when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 997value will weaken the protection as the attacker could easily write the right 998value as part of the attack most of the time. Therefore, it should return a 999true random number. 1000 1001Note: For the protection to be effective, the global data need to be placed at 1002a lower address than the stack bases. Failure to do so would allow an attacker 1003to overwrite the canary as part of the stack buffer overflow attack. 1004 1005Function : plat\_flush\_next\_bl\_params() 1006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1007 1008:: 1009 1010 Argument : void 1011 Return : void 1012 1013This function flushes to main memory all the image params that are passed to 1014next image. This function is currently invoked in BL2 to flush this information 1015to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1016 1017Modifications specific to a Boot Loader stage 1018--------------------------------------------- 1019 1020Boot Loader Stage 1 (BL1) 1021------------------------- 1022 1023BL1 implements the reset vector where execution starts from after a cold or 1024warm boot. For each CPU, BL1 is responsible for the following tasks: 1025 1026#. Handling the reset as described in section 2.2 1027 1028#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1029 only this CPU executes the remaining BL1 code, including loading and passing 1030 control to the BL2 stage. 1031 1032#. Identifying and starting the Firmware Update process (if required). 1033 1034#. Loading the BL2 image from non-volatile storage into secure memory at the 1035 address specified by the platform defined constant ``BL2_BASE``. 1036 1037#. Populating a ``meminfo`` structure with the following information in memory, 1038 accessible by BL2 immediately upon entry. 1039 1040 :: 1041 1042 meminfo.total_base = Base address of secure RAM visible to BL2 1043 meminfo.total_size = Size of secure RAM visible to BL2 1044 meminfo.free_base = Base address of secure RAM available for 1045 allocation to BL2 1046 meminfo.free_size = Size of secure RAM available for allocation to BL2 1047 1048 BL1 places this ``meminfo`` structure at the beginning of the free memory 1049 available for its use. Since BL1 cannot allocate memory dynamically at the 1050 moment, its free memory will be available for BL2's use as-is. However, this 1051 means that BL2 must read the ``meminfo`` structure before it starts using its 1052 free memory (this is discussed in Section 3.2). 1053 1054 In future releases of the ARM Trusted Firmware it will be possible for 1055 the platform to decide where it wants to place the ``meminfo`` structure for 1056 BL2. 1057 1058 BL1 implements the ``bl1_init_bl2_mem_layout()`` function to populate the 1059 BL2 ``meminfo`` structure. The platform may override this implementation, for 1060 example if the platform wants to restrict the amount of memory visible to 1061 BL2. Details of how to do this are given below. 1062 1063The following functions need to be implemented by the platform port to enable 1064BL1 to perform the above tasks. 1065 1066Function : bl1\_early\_platform\_setup() [mandatory] 1067~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1068 1069:: 1070 1071 Argument : void 1072 Return : void 1073 1074This function executes with the MMU and data caches disabled. It is only called 1075by the primary CPU. 1076 1077On ARM standard platforms, this function: 1078 1079- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1080 1081- Initializes a UART (PL011 console), which enables access to the ``printf`` 1082 family of functions in BL1. 1083 1084- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1085 the CCI slave interface corresponding to the cluster that includes the 1086 primary CPU. 1087 1088Function : bl1\_plat\_arch\_setup() [mandatory] 1089~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1090 1091:: 1092 1093 Argument : void 1094 Return : void 1095 1096This function performs any platform-specific and architectural setup that the 1097platform requires. Platform-specific setup might include configuration of 1098memory controllers and the interconnect. 1099 1100In ARM standard platforms, this function enables the MMU. 1101 1102This function helps fulfill requirement 2 above. 1103 1104Function : bl1\_platform\_setup() [mandatory] 1105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1106 1107:: 1108 1109 Argument : void 1110 Return : void 1111 1112This function executes with the MMU and data caches enabled. It is responsible 1113for performing any remaining platform-specific setup that can occur after the 1114MMU and data cache have been enabled. 1115 1116In ARM standard platforms, this function initializes the storage abstraction 1117layer used to load the next bootloader image. 1118 1119This function helps fulfill requirement 4 above. 1120 1121Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1122~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1123 1124:: 1125 1126 Argument : void 1127 Return : meminfo * 1128 1129This function should only be called on the cold boot path. It executes with the 1130MMU and data caches enabled. The pointer returned by this function must point to 1131a ``meminfo`` structure containing the extents and availability of secure RAM for 1132the BL1 stage. 1133 1134:: 1135 1136 meminfo.total_base = Base address of secure RAM visible to BL1 1137 meminfo.total_size = Size of secure RAM visible to BL1 1138 meminfo.free_base = Base address of secure RAM available for allocation 1139 to BL1 1140 meminfo.free_size = Size of secure RAM available for allocation to BL1 1141 1142This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1143populates a similar structure to tell BL2 the extents of memory available for 1144its own use. 1145 1146This function helps fulfill requirements 4 and 5 above. 1147 1148Function : bl1\_init\_bl2\_mem\_layout() [optional] 1149~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1150 1151:: 1152 1153 Argument : meminfo *, meminfo * 1154 Return : void 1155 1156BL1 needs to tell the next stage the amount of secure RAM available 1157for it to use. This information is populated in a ``meminfo`` 1158structure. 1159 1160Depending upon where BL2 has been loaded in secure RAM (determined by 1161``BL2_BASE``), BL1 calculates the amount of free memory available for BL2 to use. 1162BL1 also ensures that its data sections resident in secure RAM are not visible 1163to BL2. An illustration of how this is done in ARM standard platforms is given 1164in the **Memory layout on ARM development platforms** section in the 1165`Firmware Design`_. 1166 1167Function : bl1\_plat\_prepare\_exit() [optional] 1168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1169 1170:: 1171 1172 Argument : entry_point_info_t * 1173 Return : void 1174 1175This function is called prior to exiting BL1 in response to the 1176``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1177platform specific clean up or bookkeeping operations before transferring 1178control to the next image. It receives the address of the ``entry_point_info_t`` 1179structure passed from BL2. This function runs with MMU disabled. 1180 1181Function : bl1\_plat\_set\_ep\_info() [optional] 1182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1183 1184:: 1185 1186 Argument : unsigned int image_id, entry_point_info_t *ep_info 1187 Return : void 1188 1189This function allows platforms to override ``ep_info`` for the given ``image_id``. 1190 1191The default implementation just returns. 1192 1193Function : bl1\_plat\_get\_next\_image\_id() [optional] 1194~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1195 1196:: 1197 1198 Argument : void 1199 Return : unsigned int 1200 1201This and the following function must be overridden to enable the FWU feature. 1202 1203BL1 calls this function after platform setup to identify the next image to be 1204loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1205with the normal boot sequence, which loads and executes BL2. If the platform 1206returns a different image id, BL1 assumes that Firmware Update is required. 1207 1208The default implementation always returns ``BL2_IMAGE_ID``. The ARM development 1209platforms override this function to detect if firmware update is required, and 1210if so, return the first image in the firmware update process. 1211 1212Function : bl1\_plat\_get\_image\_desc() [optional] 1213~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1214 1215:: 1216 1217 Argument : unsigned int image_id 1218 Return : image_desc_t * 1219 1220BL1 calls this function to get the image descriptor information ``image_desc_t`` 1221for the provided ``image_id`` from the platform. 1222 1223The default implementation always returns a common BL2 image descriptor. ARM 1224standard platforms return an image descriptor corresponding to BL2 or one of 1225the firmware update images defined in the Trusted Board Boot Requirements 1226specification. 1227 1228Function : bl1\_plat\_fwu\_done() [optional] 1229~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1230 1231:: 1232 1233 Argument : unsigned int image_id, uintptr_t image_src, 1234 unsigned int image_size 1235 Return : void 1236 1237BL1 calls this function when the FWU process is complete. It must not return. 1238The platform may override this function to take platform specific action, for 1239example to initiate the normal boot flow. 1240 1241The default implementation spins forever. 1242 1243Function : bl1\_plat\_mem\_check() [mandatory] 1244~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1245 1246:: 1247 1248 Argument : uintptr_t mem_base, unsigned int mem_size, 1249 unsigned int flags 1250 Return : int 1251 1252BL1 calls this function while handling FWU related SMCs, more specifically when 1253copying or authenticating an image. Its responsibility is to ensure that the 1254region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1255that this memory corresponds to either a secure or non-secure memory region as 1256indicated by the security state of the ``flags`` argument. 1257 1258This function can safely assume that the value resulting from the addition of 1259``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1260overflow. 1261 1262This function must return 0 on success, a non-null error code otherwise. 1263 1264The default implementation of this function asserts therefore platforms must 1265override it when using the FWU feature. 1266 1267Boot Loader Stage 2 (BL2) 1268------------------------- 1269 1270The BL2 stage is executed only by the primary CPU, which is determined in BL1 1271using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1272``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1273 1274#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1275 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1276 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1277 The platform also defines the address in memory where SCP\_BL2 is loaded 1278 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1279 to determine if there is enough memory to load the SCP\_BL2 image. 1280 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1281 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1282 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1283 1284#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1285 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1286 by BL1. This structure allows BL2 to calculate how much secure RAM is 1287 available for its use. The platform also defines the address in secure RAM 1288 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1289 information to determine if there is enough memory to load the BL31 image. 1290 1291#. (Optional) Loading the BL32 binary image (if present) from platform 1292 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1293 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1294 The platform also defines the address in memory where BL32 is loaded 1295 through the optional constant ``BL32_BASE``. BL2 uses this information 1296 to determine if there is enough memory to load the BL32 image. 1297 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1298 1299#. (Optional) Arranging to pass control to the BL32 image (if present) that 1300 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1301 structure in memory provided by the platform with information about how 1302 BL31 should pass control to the BL32 image. 1303 1304#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1305 other means) into non-secure DRAM from platform storage and arranging for 1306 BL31 to pass control to this image. This address is determined using the 1307 ``plat_get_ns_image_entrypoint()`` function described below. 1308 1309#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1310 platform with information about how BL31 should pass control to the 1311 other BL images. 1312 1313The following functions must be implemented by the platform port to enable BL2 1314to perform the above tasks. 1315 1316Function : bl2\_early\_platform\_setup() [mandatory] 1317~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1318 1319:: 1320 1321 Argument : meminfo * 1322 Return : void 1323 1324This function executes with the MMU and data caches disabled. It is only called 1325by the primary CPU. The arguments to this function is the address of the 1326``meminfo`` structure populated by BL1. 1327 1328The platform may copy the contents of the ``meminfo`` structure into a private 1329variable as the original memory may be subsequently overwritten by BL2. The 1330copied structure is made available to all BL2 code through the 1331``bl2_plat_sec_mem_layout()`` function. 1332 1333On ARM standard platforms, this function also: 1334 1335- Initializes a UART (PL011 console), which enables access to the ``printf`` 1336 family of functions in BL2. 1337 1338- Initializes the storage abstraction layer used to load further bootloader 1339 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1340 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1341 1342Function : bl2\_plat\_arch\_setup() [mandatory] 1343~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1344 1345:: 1346 1347 Argument : void 1348 Return : void 1349 1350This function executes with the MMU and data caches disabled. It is only called 1351by the primary CPU. 1352 1353The purpose of this function is to perform any architectural initialization 1354that varies across platforms. 1355 1356On ARM standard platforms, this function enables the MMU. 1357 1358Function : bl2\_platform\_setup() [mandatory] 1359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1360 1361:: 1362 1363 Argument : void 1364 Return : void 1365 1366This function may execute with the MMU and data caches enabled if the platform 1367port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1368called by the primary CPU. 1369 1370The purpose of this function is to perform any platform initialization 1371specific to BL2. 1372 1373In ARM standard platforms, this function performs security setup, including 1374configuration of the TrustZone controller to allow non-secure masters access 1375to most of DRAM. Part of DRAM is reserved for secure world use. 1376 1377Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1378~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1379 1380:: 1381 1382 Argument : void 1383 Return : meminfo * 1384 1385This function should only be called on the cold boot path. It may execute with 1386the MMU and data caches enabled if the platform port does the necessary 1387initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1388 1389The purpose of this function is to return a pointer to a ``meminfo`` structure 1390populated with the extents of secure RAM available for BL2 to use. See 1391``bl2_early_platform_setup()`` above. 1392 1393Following function is required only when LOAD\_IMAGE\_V2 is enabled. 1394 1395Function : bl2\_plat\_handle\_post\_image\_load() [mandatory] 1396~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1397 1398:: 1399 1400 Argument : unsigned int 1401 Return : int 1402 1403This function can be used by the platforms to update/use image information 1404for given ``image_id``. This function is currently invoked in BL2 to handle 1405BL image specific information based on the ``image_id`` passed, when 1406LOAD\_IMAGE\_V2 is enabled. 1407 1408Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1409 1410Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1411~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1412 1413:: 1414 1415 Argument : meminfo * 1416 Return : void 1417 1418This function is used to get the memory limits where BL2 can load the 1419SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1420validate whether the SCP\_BL2 image can be loaded within the given 1421memory from the given base. 1422 1423Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1424~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1425 1426:: 1427 1428 Argument : image_info * 1429 Return : int 1430 1431This function is called after loading SCP\_BL2 image and it is used to perform 1432any platform-specific actions required to handle the SCP firmware. Typically it 1433transfers the image into SCP memory using a platform-specific protocol and waits 1434until SCP executes it and signals to the Application Processor (AP) for BL2 1435execution to continue. 1436 1437This function returns 0 on success, a negative error code otherwise. 1438 1439Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1440~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1441 1442:: 1443 1444 Argument : void 1445 Return : bl31_params * 1446 1447BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1448will use for passing information to BL31. The ``bl31_params`` structure carries 1449the following information. 1450- Header describing the version information for interpreting the bl31\_param 1451structure 1452- Information about executing the BL33 image in the ``bl33_ep_info`` field 1453- Information about executing the BL32 image in the ``bl32_ep_info`` field 1454- Information about the type and extents of BL31 image in the 1455``bl31_image_info`` field 1456- Information about the type and extents of BL32 image in the 1457``bl32_image_info`` field 1458- Information about the type and extents of BL33 image in the 1459``bl33_image_info`` field 1460 1461The memory pointed by this structure and its sub-structures should be 1462accessible from BL31 initialisation code. BL31 might choose to copy the 1463necessary content, or maintain the structures until BL33 is initialised. 1464 1465Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1466~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1467 1468:: 1469 1470 Argument : void 1471 Return : entry_point_info * 1472 1473BL2 platform code returns a pointer which is used to populate the entry point 1474information for BL31 entry point. The location pointed by it should be 1475accessible from BL1 while processing the synchronous exception to run to BL31. 1476 1477In ARM standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1478structure in BL2 memory. 1479 1480Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1481~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1482 1483:: 1484 1485 Argument : image_info *, entry_point_info * 1486 Return : void 1487 1488In the normal boot flow, this function is called after loading BL31 image and 1489it can be used to overwrite the entry point set by loader and also set the 1490security state and SPSR which represents the entry point system state for BL31. 1491 1492When booting an EL3 payload instead, this function is called after populating 1493its entry point address and can be used for the same purpose for the payload 1494image. It receives a null pointer as its first argument in this case. 1495 1496Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1497~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1498 1499:: 1500 1501 Argument : image_info *, entry_point_info * 1502 Return : void 1503 1504This function is called after loading BL32 image and it can be used to 1505overwrite the entry point set by loader and also set the security state 1506and SPSR which represents the entry point system state for BL32. 1507 1508Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1509~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1510 1511:: 1512 1513 Argument : image_info *, entry_point_info * 1514 Return : void 1515 1516This function is called after loading BL33 image and it can be used to 1517overwrite the entry point set by loader and also set the security state 1518and SPSR which represents the entry point system state for BL33. 1519 1520In the preloaded BL33 alternative boot flow, this function is called after 1521populating its entry point address. It is passed a null pointer as its first 1522argument in this case. 1523 1524Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1525~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1526 1527:: 1528 1529 Argument : meminfo * 1530 Return : void 1531 1532This function is used to get the memory limits where BL2 can load the 1533BL32 image. The meminfo provided by this is used by load\_image() to 1534validate whether the BL32 image can be loaded with in the given 1535memory from the given base. 1536 1537Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1538~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1539 1540:: 1541 1542 Argument : meminfo * 1543 Return : void 1544 1545This function is used to get the memory limits where BL2 can load the 1546BL33 image. The meminfo provided by this is used by load\_image() to 1547validate whether the BL33 image can be loaded with in the given 1548memory from the given base. 1549 1550This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1551build options are used. 1552 1553Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1554~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1555 1556:: 1557 1558 Argument : void 1559 Return : void 1560 1561Once BL2 has populated all the structures that needs to be read by BL1 1562and BL31 including the bl31\_params structures and its sub-structures, 1563the bl31\_ep\_info structure and any platform specific data. It flushes 1564all these data to the main memory so that it is available when we jump to 1565later Bootloader stages with MMU off 1566 1567Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1569 1570:: 1571 1572 Argument : void 1573 Return : uintptr_t 1574 1575As previously described, BL2 is responsible for arranging for control to be 1576passed to a normal world BL image through BL31. This function returns the 1577entrypoint of that image, which BL31 uses to jump to it. 1578 1579BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1580 1581This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1582build options are used. 1583 1584FWU Boot Loader Stage 2 (BL2U) 1585------------------------------ 1586 1587The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1588process and is executed only by the primary CPU. BL1 passes control to BL2U at 1589``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1590 1591#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1592 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1593 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1594 should be copied from. Subsequent handling of the SCP\_BL2U image is 1595 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1596 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1597 1598#. Any platform specific setup required to perform the FWU process. For 1599 example, ARM standard platforms initialize the TZC controller so that the 1600 normal world can access DDR memory. 1601 1602The following functions must be implemented by the platform port to enable 1603BL2U to perform the tasks mentioned above. 1604 1605Function : bl2u\_early\_platform\_setup() [mandatory] 1606~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1607 1608:: 1609 1610 Argument : meminfo *mem_info, void *plat_info 1611 Return : void 1612 1613This function executes with the MMU and data caches disabled. It is only 1614called by the primary CPU. The arguments to this function is the address 1615of the ``meminfo`` structure and platform specific info provided by BL1. 1616 1617The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1618private storage as the original memory may be subsequently overwritten by BL2U. 1619 1620On ARM CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1621to extract SCP\_BL2U image information, which is then copied into a private 1622variable. 1623 1624Function : bl2u\_plat\_arch\_setup() [mandatory] 1625~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1626 1627:: 1628 1629 Argument : void 1630 Return : void 1631 1632This function executes with the MMU and data caches disabled. It is only 1633called by the primary CPU. 1634 1635The purpose of this function is to perform any architectural initialization 1636that varies across platforms, for example enabling the MMU (since the memory 1637map differs across platforms). 1638 1639Function : bl2u\_platform\_setup() [mandatory] 1640~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1641 1642:: 1643 1644 Argument : void 1645 Return : void 1646 1647This function may execute with the MMU and data caches enabled if the platform 1648port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1649called by the primary CPU. 1650 1651The purpose of this function is to perform any platform initialization 1652specific to BL2U. 1653 1654In ARM standard platforms, this function performs security setup, including 1655configuration of the TrustZone controller to allow non-secure masters access 1656to most of DRAM. Part of DRAM is reserved for secure world use. 1657 1658Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1659~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1660 1661:: 1662 1663 Argument : void 1664 Return : int 1665 1666This function is used to perform any platform-specific actions required to 1667handle the SCP firmware. Typically it transfers the image into SCP memory using 1668a platform-specific protocol and waits until SCP executes it and signals to the 1669Application Processor (AP) for BL2U execution to continue. 1670 1671This function returns 0 on success, a negative error code otherwise. 1672This function is included if SCP\_BL2U\_BASE is defined. 1673 1674Boot Loader Stage 3-1 (BL31) 1675---------------------------- 1676 1677During cold boot, the BL31 stage is executed only by the primary CPU. This is 1678determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1679control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1680CPUs. BL31 executes at EL3 and is responsible for: 1681 1682#. Re-initializing all architectural and platform state. Although BL1 performs 1683 some of this initialization, BL31 remains resident in EL3 and must ensure 1684 that EL3 architectural and platform state is completely initialized. It 1685 should make no assumptions about the system state when it receives control. 1686 1687#. Passing control to a normal world BL image, pre-loaded at a platform- 1688 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1689 populated in memory to do this. 1690 1691#. Providing runtime firmware services. Currently, BL31 only implements a 1692 subset of the Power State Coordination Interface (PSCI) API as a runtime 1693 service. See Section 3.3 below for details of porting the PSCI 1694 implementation. 1695 1696#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1697 specific address by BL2. BL31 exports a set of apis that allow runtime 1698 services to specify the security state in which the next image should be 1699 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1700 structure populated by BL2 to do this. 1701 1702If BL31 is a reset vector, It also needs to handle the reset as specified in 1703section 2.2 before the tasks described above. 1704 1705The following functions must be implemented by the platform port to enable BL31 1706to perform the above tasks. 1707 1708Function : bl31\_early\_platform\_setup() [mandatory] 1709~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1710 1711:: 1712 1713 Argument : bl31_params *, void * 1714 Return : void 1715 1716This function executes with the MMU and data caches disabled. It is only called 1717by the primary CPU. The arguments to this function are: 1718 1719- The address of the ``bl31_params`` structure populated by BL2. 1720- An opaque pointer that the platform may use as needed. 1721 1722The platform can copy the contents of the ``bl31_params`` structure and its 1723sub-structures into private variables if the original memory may be 1724subsequently overwritten by BL31 and similarly the ``void *`` pointing 1725to the platform data also needs to be saved. 1726 1727In ARM standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1728in BL2 memory. BL31 copies the information in this pointer to internal data 1729structures. It also performs the following: 1730 1731- Initialize a UART (PL011 console), which enables access to the ``printf`` 1732 family of functions in BL31. 1733 1734- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1735 CCI slave interface corresponding to the cluster that includes the primary 1736 CPU. 1737 1738Function : bl31\_plat\_arch\_setup() [mandatory] 1739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1740 1741:: 1742 1743 Argument : void 1744 Return : void 1745 1746This function executes with the MMU and data caches disabled. It is only called 1747by the primary CPU. 1748 1749The purpose of this function is to perform any architectural initialization 1750that varies across platforms. 1751 1752On ARM standard platforms, this function enables the MMU. 1753 1754Function : bl31\_platform\_setup() [mandatory] 1755~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1756 1757:: 1758 1759 Argument : void 1760 Return : void 1761 1762This function may execute with the MMU and data caches enabled if the platform 1763port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1764called by the primary CPU. 1765 1766The purpose of this function is to complete platform initialization so that both 1767BL31 runtime services and normal world software can function correctly. 1768 1769On ARM standard platforms, this function does the following: 1770 1771- Initialize the generic interrupt controller. 1772 1773 Depending on the GIC driver selected by the platform, the appropriate GICv2 1774 or GICv3 initialization will be done, which mainly consists of: 1775 1776 - Enable secure interrupts in the GIC CPU interface. 1777 - Disable the legacy interrupt bypass mechanism. 1778 - Configure the priority mask register to allow interrupts of all priorities 1779 to be signaled to the CPU interface. 1780 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1781 - Target all secure SPIs to CPU0. 1782 - Enable these secure interrupts in the GIC distributor. 1783 - Configure all other interrupts as non-secure. 1784 - Enable signaling of secure interrupts in the GIC distributor. 1785 1786- Enable system-level implementation of the generic timer counter through the 1787 memory mapped interface. 1788 1789- Grant access to the system counter timer module 1790 1791- Initialize the power controller device. 1792 1793 In particular, initialise the locks that prevent concurrent accesses to the 1794 power controller device. 1795 1796Function : bl31\_plat\_runtime\_setup() [optional] 1797~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1798 1799:: 1800 1801 Argument : void 1802 Return : void 1803 1804The purpose of this function is allow the platform to perform any BL31 runtime 1805setup just prior to BL31 exit during cold boot. The default weak 1806implementation of this function will invoke ``console_uninit()`` which will 1807suppress any BL31 runtime logs. 1808 1809In ARM Standard platforms, this function will initialize the BL31 runtime 1810console which will cause all further BL31 logs to be output to the 1811runtime console. 1812 1813Function : bl31\_get\_next\_image\_info() [mandatory] 1814~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1815 1816:: 1817 1818 Argument : unsigned int 1819 Return : entry_point_info * 1820 1821This function may execute with the MMU and data caches enabled if the platform 1822port does the necessary initializations in ``bl31_plat_arch_setup()``. 1823 1824This function is called by ``bl31_main()`` to retrieve information provided by 1825BL2 for the next image in the security state specified by the argument. BL31 1826uses this information to pass control to that image in the specified security 1827state. This function must return a pointer to the ``entry_point_info`` structure 1828(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1829should return NULL otherwise. 1830 1831Function : plat\_get\_syscnt\_freq2() [mandatory] 1832~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1833 1834:: 1835 1836 Argument : void 1837 Return : unsigned int 1838 1839This function is used by the architecture setup code to retrieve the counter 1840frequency for the CPU's generic timer. This value will be programmed into the 1841``CNTFRQ_EL0`` register. In ARM standard platforms, it returns the base frequency 1842of the system counter, which is retrieved from the first entry in the frequency 1843modes table. 1844 1845#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 1846~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1847 1848When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1849bytes) aligned to the cache line boundary that should be allocated per-cpu to 1850accommodate all the bakery locks. 1851 1852If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1853calculates the size of the ``bakery_lock`` input section, aligns it to the 1854nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1855and stores the result in a linker symbol. This constant prevents a platform 1856from relying on the linker and provide a more efficient mechanism for 1857accessing per-cpu bakery lock information. 1858 1859If this constant is defined and its value is not equal to the value 1860calculated by the linker then a link time assertion is raised. A compile time 1861assertion is raised if the value of the constant is not aligned to the cache 1862line boundary. 1863 1864Power State Coordination Interface (in BL31) 1865-------------------------------------------- 1866 1867The ARM Trusted Firmware's implementation of the PSCI API is based around the 1868concept of a *power domain*. A *power domain* is a CPU or a logical group of 1869CPUs which share some state on which power management operations can be 1870performed as specified by `PSCI`_. Each CPU in the system is assigned a cpu 1871index which is a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. 1872The *power domains* are arranged in a hierarchical tree structure and 1873each *power domain* can be identified in a system by the cpu index of any CPU 1874that is part of that domain and a *power domain level*. A processing element 1875(for example, a CPU) is at level 0. If the *power domain* node above a CPU is 1876a logical grouping of CPUs that share some state, then level 1 is that group 1877of CPUs (for example, a cluster), and level 2 is a group of clusters 1878(for example, the system). More details on the power domain topology and its 1879organization can be found in `Power Domain Topology Design`_. 1880 1881BL31's platform initialization code exports a pointer to the platform-specific 1882power management operations required for the PSCI implementation to function 1883correctly. This information is populated in the ``plat_psci_ops`` structure. The 1884PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 1885power management operations on the power domains. For example, the target 1886CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 1887handler (if present) is called for the CPU power domain. 1888 1889The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 1890describe composite power states specific to a platform. The PSCI implementation 1891defines a generic representation of the power-state parameter viz which is an 1892array of local power states where each index corresponds to a power domain 1893level. Each entry contains the local power state the power domain at that power 1894level could enter. It depends on the ``validate_power_state()`` handler to 1895convert the power-state parameter (possibly encoding a composite power state) 1896passed in a PSCI ``CPU_SUSPEND`` call to this representation. 1897 1898The following functions form part of platform port of PSCI functionality. 1899 1900Function : plat\_psci\_stat\_accounting\_start() [optional] 1901~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1902 1903:: 1904 1905 Argument : const psci_power_state_t * 1906 Return : void 1907 1908This is an optional hook that platforms can implement for residency statistics 1909accounting before entering a low power state. The ``pwr_domain_state`` field of 1910``state_info`` (first argument) can be inspected if stat accounting is done 1911differently at CPU level versus higher levels. As an example, if the element at 1912index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1913state, special hardware logic may be programmed in order to keep track of the 1914residency statistics. For higher levels (array indices > 0), the residency 1915statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1916default implementation will use PMF to capture timestamps. 1917 1918Function : plat\_psci\_stat\_accounting\_stop() [optional] 1919~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1920 1921:: 1922 1923 Argument : const psci_power_state_t * 1924 Return : void 1925 1926This is an optional hook that platforms can implement for residency statistics 1927accounting after exiting from a low power state. The ``pwr_domain_state`` field 1928of ``state_info`` (first argument) can be inspected if stat accounting is done 1929differently at CPU level versus higher levels. As an example, if the element at 1930index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1931state, special hardware logic may be programmed in order to keep track of the 1932residency statistics. For higher levels (array indices > 0), the residency 1933statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1934default implementation will use PMF to capture timestamps. 1935 1936Function : plat\_psci\_stat\_get\_residency() [optional] 1937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1938 1939:: 1940 1941 Argument : unsigned int, const psci_power_state_t *, int 1942 Return : u_register_t 1943 1944This is an optional interface that is is invoked after resuming from a low power 1945state and provides the time spent resident in that low power state by the power 1946domain at a particular power domain level. When a CPU wakes up from suspend, 1947all its parent power domain levels are also woken up. The generic PSCI code 1948invokes this function for each parent power domain that is resumed and it 1949identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 1950argument) describes the low power state that the power domain has resumed from. 1951The current CPU is the first CPU in the power domain to resume from the low 1952power state and the ``last_cpu_idx`` (third parameter) is the index of the last 1953CPU in the power domain to suspend and may be needed to calculate the residency 1954for that power domain. 1955 1956Function : plat\_get\_target\_pwr\_state() [optional] 1957~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1958 1959:: 1960 1961 Argument : unsigned int, const plat_local_state_t *, unsigned int 1962 Return : plat_local_state_t 1963 1964The PSCI generic code uses this function to let the platform participate in 1965state coordination during a power management operation. The function is passed 1966a pointer to an array of platform specific local power state ``states`` (second 1967argument) which contains the requested power state for each CPU at a particular 1968power domain level ``lvl`` (first argument) within the power domain. The function 1969is expected to traverse this array of upto ``ncpus`` (third argument) and return 1970a coordinated target power state by the comparing all the requested power 1971states. The target power state should not be deeper than any of the requested 1972power states. 1973 1974A weak definition of this API is provided by default wherein it assumes 1975that the platform assigns a local state value in order of increasing depth 1976of the power state i.e. for two power states X & Y, if X < Y 1977then X represents a shallower power state than Y. As a result, the 1978coordinated target local power state for a power domain will be the minimum 1979of the requested local power state values. 1980 1981Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 1982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1983 1984:: 1985 1986 Argument : void 1987 Return : const unsigned char * 1988 1989This function returns a pointer to the byte array containing the power domain 1990topology tree description. The format and method to construct this array are 1991described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 1992requires this array to be described by the platform, either statically or 1993dynamically, to initialize the power domain topology tree. In case the array 1994is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 1995plat\_my\_core\_pos() should also be implemented suitably so that the topology 1996tree description matches the CPU indices returned by these APIs. These APIs 1997together form the platform interface for the PSCI topology framework. 1998 1999Function : plat\_setup\_psci\_ops() [mandatory] 2000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2001 2002:: 2003 2004 Argument : uintptr_t, const plat_psci_ops ** 2005 Return : int 2006 2007This function may execute with the MMU and data caches enabled if the platform 2008port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2009called by the primary CPU. 2010 2011This function is called by PSCI initialization code. Its purpose is to let 2012the platform layer know about the warm boot entrypoint through the 2013``sec_entrypoint`` (first argument) and to export handler routines for 2014platform-specific psci power management actions by populating the passed 2015pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2016 2017A description of each member of this structure is given below. Please refer to 2018the ARM FVP specific implementation of these handlers in 2019`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2020platform wants to support, the associated operation or operations in this 2021structure must be provided and implemented (Refer section 4 of 2022`Firmware Design`_ for the PSCI API supported in Trusted Firmware). To disable 2023a PSCI function in a platform port, the operation should be removed from this 2024structure instead of providing an empty implementation. 2025 2026plat\_psci\_ops.cpu\_standby() 2027.............................. 2028 2029Perform the platform-specific actions to enter the standby state for a cpu 2030indicated by the passed argument. This provides a fast path for CPU standby 2031wherein overheads of PSCI state management and lock acquistion is avoided. 2032For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2033the suspend state type specified in the ``power-state`` parameter should be 2034STANDBY and the target power domain level specified should be the CPU. The 2035handler should put the CPU into a low power retention state (usually by 2036issuing a wfi instruction) and ensure that it can be woken up from that 2037state by a normal interrupt. The generic code expects the handler to succeed. 2038 2039plat\_psci\_ops.pwr\_domain\_on() 2040................................. 2041 2042Perform the platform specific actions to power on a CPU, specified 2043by the ``MPIDR`` (first argument). The generic code expects the platform to 2044return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2045 2046plat\_psci\_ops.pwr\_domain\_off() 2047.................................. 2048 2049Perform the platform specific actions to prepare to power off the calling CPU 2050and its higher parent power domain levels as indicated by the ``target_state`` 2051(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2052 2053The ``target_state`` encodes the platform coordinated target local power states 2054for the CPU power domain and its parent power domain levels. The handler 2055needs to perform power management operation corresponding to the local state 2056at each power level. 2057 2058For this handler, the local power state for the CPU power domain will be a 2059power down state where as it could be either power down, retention or run state 2060for the higher power domain levels depending on the result of state 2061coordination. The generic code expects the handler to succeed. 2062 2063plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2064................................................................. 2065 2066This optional function may be used as a performance optimization to replace 2067or complement pwr_domain_suspend() on some platforms. Its calling semantics 2068are identical to pwr_domain_suspend(), except the PSCI implementation only 2069calls this function when suspending to a power down state, and it guarantees 2070that data caches are enabled. 2071 2072When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2073before calling pwr_domain_suspend(). If the target_state corresponds to a 2074power down state and it is safe to perform some or all of the platform 2075specific actions in that function with data caches enabled, it may be more 2076efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2077= 1, data caches remain enabled throughout, and so there is no advantage to 2078moving platform specific actions to this function. 2079 2080plat\_psci\_ops.pwr\_domain\_suspend() 2081...................................... 2082 2083Perform the platform specific actions to prepare to suspend the calling 2084CPU and its higher parent power domain levels as indicated by the 2085``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2086API implementation. 2087 2088The ``target_state`` has a similar meaning as described in 2089the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2090target local power states for the CPU power domain and its parent 2091power domain levels. The handler needs to perform power management operation 2092corresponding to the local state at each power level. The generic code 2093expects the handler to succeed. 2094 2095The difference between turning a power domain off versus suspending it 2096is that in the former case, the power domain is expected to re-initialize 2097its state when it is next powered on (see ``pwr_domain_on_finish()``). In the 2098latter case, the power domain is expected to save enough state so that it can 2099resume execution by restoring this state when its powered on (see 2100``pwr_domain_suspend_finish()``). 2101 2102plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2103............................................. 2104 2105This is an optional function and, if implemented, is expected to perform 2106platform specific actions including the ``wfi`` invocation which allows the 2107CPU to powerdown. Since this function is invoked outside the PSCI locks, 2108the actions performed in this hook must be local to the CPU or the platform 2109must ensure that races between multiple CPUs cannot occur. 2110 2111The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2112operation and it encodes the platform coordinated target local power states for 2113the CPU power domain and its parent power domain levels. This function must 2114not return back to the caller. 2115 2116If this function is not implemented by the platform, PSCI generic 2117implementation invokes ``psci_power_down_wfi()`` for power down. 2118 2119plat\_psci\_ops.pwr\_domain\_on\_finish() 2120......................................... 2121 2122This function is called by the PSCI implementation after the calling CPU is 2123powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2124It performs the platform-specific setup required to initialize enough state for 2125this CPU to enter the normal world and also provide secure runtime firmware 2126services. 2127 2128The ``target_state`` (first argument) is the prior state of the power domains 2129immediately before the CPU was turned on. It indicates which power domains 2130above the CPU might require initialization due to having previously been in 2131low power states. The generic code expects the handler to succeed. 2132 2133plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2134.............................................. 2135 2136This function is called by the PSCI implementation after the calling CPU is 2137powered on and released from reset in response to an asynchronous wakeup 2138event, for example a timer interrupt that was programmed by the CPU during the 2139``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2140setup required to restore the saved state for this CPU to resume execution 2141in the normal world and also provide secure runtime firmware services. 2142 2143The ``target_state`` (first argument) has a similar meaning as described in 2144the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2145to succeed. 2146 2147plat\_psci\_ops.system\_off() 2148............................. 2149 2150This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2151call. It performs the platform-specific system poweroff sequence after 2152notifying the Secure Payload Dispatcher. 2153 2154plat\_psci\_ops.system\_reset() 2155............................... 2156 2157This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2158call. It performs the platform-specific system reset sequence after 2159notifying the Secure Payload Dispatcher. 2160 2161plat\_psci\_ops.validate\_power\_state() 2162........................................ 2163 2164This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2165call to validate the ``power_state`` parameter of the PSCI API and if valid, 2166populate it in ``req_state`` (second argument) array as power domain level 2167specific local states. If the ``power_state`` is invalid, the platform must 2168return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2169normal world PSCI client. 2170 2171plat\_psci\_ops.validate\_ns\_entrypoint() 2172.......................................... 2173 2174This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2175``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2176parameter passed by the normal world. If the ``entry_point`` is invalid, 2177the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2178propagated back to the normal world PSCI client. 2179 2180plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2181................................................. 2182 2183This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2184call to get the ``req_state`` parameter from platform which encodes the power 2185domain level specific local states to suspend to system affinity level. The 2186``req_state`` will be utilized to do the PSCI state coordination and 2187``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2188enter system suspend. 2189 2190plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2191........................................... 2192 2193This is an optional function and, if implemented, is invoked by the PSCI 2194implementation to convert the ``local_state`` (first argument) at a specified 2195``pwr_lvl`` (second argument) to an index between 0 and 2196``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2197supports more than two local power states at each power domain level, that is 2198``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2199local power states. 2200 2201plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2202.................................................... 2203 2204This is an optional function and, if implemented, verifies the ``power_state`` 2205(second argument) parameter of the PSCI API corresponding to a target power 2206domain. The target power domain is identified by using both ``MPIDR`` (first 2207argument) and the power domain level encoded in ``power_state``. The power domain 2208level specific local states are to be extracted from ``power_state`` and be 2209populated in the ``output_state`` (third argument) array. The functionality 2210is similar to the ``validate_power_state`` function described above and is 2211envisaged to be used in case the validity of ``power_state`` depend on the 2212targeted power domain. If the ``power_state`` is invalid for the targeted power 2213domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2214function is not implemented, then the generic implementation relies on 2215``validate_power_state`` function to translate the ``power_state``. 2216 2217This function can also be used in case the platform wants to support local 2218power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2219APIs as described in Section 5.18 of `PSCI`_. 2220 2221plat\_psci\_ops.get\_node\_hw\_state() 2222...................................... 2223 2224This is an optional function. If implemented this function is intended to return 2225the power state of a node (identified by the first parameter, the ``MPIDR``) in 2226the power domain topology (identified by the second parameter, ``power_level``), 2227as retrieved from a power controller or equivalent component on the platform. 2228Upon successful completion, the implementation must map and return the final 2229status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2230must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2231appropriate. 2232 2233Implementations are not expected to handle ``power_levels`` greater than 2234``PLAT_MAX_PWR_LVL``. 2235 2236Interrupt Management framework (in BL31) 2237---------------------------------------- 2238 2239BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2240generated in either security state and targeted to EL1 or EL2 in the non-secure 2241state or EL3/S-EL1 in the secure state. The design of this framework is 2242described in the `IMF Design Guide`_ 2243 2244A platform should export the following APIs to support the IMF. The following 2245text briefly describes each api and its implementation in ARM standard 2246platforms. The API implementation depends upon the type of interrupt controller 2247present in the platform. ARM standard platform layer supports both 2248`ARM Generic Interrupt Controller version 2.0 (GICv2)`_ 2249and `3.0 (GICv3)`_. Juno builds the ARM 2250Standard layer to use GICv2 and the FVP can be configured to use either GICv2 or 2251GICv3 depending on the build flag ``FVP_USE_GIC_DRIVER`` (See FVP platform 2252specific build options in `User Guide`_ for more details). 2253 2254Function : plat\_interrupt\_type\_to\_line() [mandatory] 2255~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2256 2257:: 2258 2259 Argument : uint32_t, uint32_t 2260 Return : uint32_t 2261 2262The ARM processor signals an interrupt exception either through the IRQ or FIQ 2263interrupt line. The specific line that is signaled depends on how the interrupt 2264controller (IC) reports different interrupt types from an execution context in 2265either security state. The IMF uses this API to determine which interrupt line 2266the platform IC uses to signal each type of interrupt supported by the framework 2267from a given security state. This API must be invoked at EL3. 2268 2269The first parameter will be one of the ``INTR_TYPE_*`` values (see 2270`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2271security state of the originating execution context. The return result is the 2272bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2273FIQ=2. 2274 2275In the case of ARM standard platforms using GICv2, S-EL1 interrupts are 2276configured as FIQs and Non-secure interrupts as IRQs from either security 2277state. 2278 2279In the case of ARM standard platforms using GICv3, the interrupt line to be 2280configured depends on the security state of the execution context when the 2281interrupt is signalled and are as follows: 2282 2283- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2284 NS-EL0/1/2 context. 2285- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2286 in the NS-EL0/1/2 context. 2287- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2288 context. 2289 2290Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2291~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2292 2293:: 2294 2295 Argument : void 2296 Return : uint32_t 2297 2298This API returns the type of the highest priority pending interrupt at the 2299platform IC. The IMF uses the interrupt type to retrieve the corresponding 2300handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2301pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2302``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2303 2304In the case of ARM standard platforms using GICv2, the *Highest Priority 2305Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2306the pending interrupt. The type of interrupt depends upon the id value as 2307follows. 2308 2309#. id < 1022 is reported as a S-EL1 interrupt 2310#. id = 1022 is reported as a Non-secure interrupt. 2311#. id = 1023 is reported as an invalid interrupt type. 2312 2313In the case of ARM standard platforms using GICv3, the system register 2314``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2315is read to determine the id of the pending interrupt. The type of interrupt 2316depends upon the id value as follows. 2317 2318#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2319#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2320#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2321#. All other interrupt id's are reported as EL3 interrupt. 2322 2323Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2324~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2325 2326:: 2327 2328 Argument : void 2329 Return : uint32_t 2330 2331This API returns the id of the highest priority pending interrupt at the 2332platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2333pending. 2334 2335In the case of ARM standard platforms using GICv2, the *Highest Priority 2336Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2337pending interrupt. The id that is returned by API depends upon the value of 2338the id read from the interrupt controller as follows. 2339 2340#. id < 1022. id is returned as is. 2341#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2342 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2343 This id is returned by the API. 2344#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2345 2346In the case of ARM standard platforms using GICv3, if the API is invoked from 2347EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2348group 0 Register*, is read to determine the id of the pending interrupt. The id 2349that is returned by API depends upon the value of the id read from the 2350interrupt controller as follows. 2351 2352#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2353#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2354 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2355 Register* is read to determine the id of the group 1 interrupt. This id 2356 is returned by the API as long as it is a valid interrupt id 2357#. If the id is any of the special interrupt identifiers, 2358 ``INTR_ID_UNAVAILABLE`` is returned. 2359 2360When the API invoked from S-EL1 for GICv3 systems, the id read from system 2361register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2362Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2363``INTR_ID_UNAVAILABLE`` is returned. 2364 2365Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2366~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2367 2368:: 2369 2370 Argument : void 2371 Return : uint32_t 2372 2373This API is used by the CPU to indicate to the platform IC that processing of 2374the highest pending interrupt has begun. It should return the id of the 2375interrupt which is being processed. 2376 2377This function in ARM standard platforms using GICv2, reads the *Interrupt 2378Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2379priority pending interrupt from pending to active in the interrupt controller. 2380It returns the value read from the ``GICC_IAR``. This value is the id of the 2381interrupt whose state has been changed. 2382 2383In the case of ARM standard platforms using GICv3, if the API is invoked 2384from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2385Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2386reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2387group 1*. The read changes the state of the highest pending interrupt from 2388pending to active in the interrupt controller. The value read is returned 2389and is the id of the interrupt whose state has been changed. 2390 2391The TSP uses this API to start processing of the secure physical timer 2392interrupt. 2393 2394Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2395~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2396 2397:: 2398 2399 Argument : uint32_t 2400 Return : void 2401 2402This API is used by the CPU to indicate to the platform IC that processing of 2403the interrupt corresponding to the id (passed as the parameter) has 2404finished. The id should be the same as the id returned by the 2405``plat_ic_acknowledge_interrupt()`` API. 2406 2407ARM standard platforms write the id to the *End of Interrupt Register* 2408(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2409system register in case of GICv3 depending on where the API is invoked from, 2410EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2411controller. 2412 2413The TSP uses this API to finish processing of the secure physical timer 2414interrupt. 2415 2416Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2417~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2418 2419:: 2420 2421 Argument : uint32_t 2422 Return : uint32_t 2423 2424This API returns the type of the interrupt id passed as the parameter. 2425``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2426interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2427returned depending upon how the interrupt has been configured by the platform 2428IC. This API must be invoked at EL3. 2429 2430ARM standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2431and Non-secure interrupts as Group1 interrupts. It reads the group value 2432corresponding to the interrupt id from the relevant *Interrupt Group Register* 2433(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2434 2435In the case of ARM standard platforms using GICv3, both the *Interrupt Group 2436Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2437(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2438as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2439 2440Crash Reporting mechanism (in BL31) 2441----------------------------------- 2442 2443BL31 implements a crash reporting mechanism which prints the various registers 2444of the CPU to enable quick crash analysis and debugging. It requires that a 2445console is designated as the crash console by the platform which will be used to 2446print the register dump. 2447 2448The following functions must be implemented by the platform if it wants crash 2449reporting mechanism in BL31. The functions are implemented in assembly so that 2450they can be invoked without a C Runtime stack. 2451 2452Function : plat\_crash\_console\_init 2453~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2454 2455:: 2456 2457 Argument : void 2458 Return : int 2459 2460This API is used by the crash reporting mechanism to initialize the crash 2461console. It must only use the general purpose registers x0 to x4 to do the 2462initialization and returns 1 on success. 2463 2464Function : plat\_crash\_console\_putc 2465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2466 2467:: 2468 2469 Argument : int 2470 Return : int 2471 2472This API is used by the crash reporting mechanism to print a character on the 2473designated crash console. It must only use general purpose registers x1 and 2474x2 to do its work. The parameter and the return value are in general purpose 2475register x0. 2476 2477Function : plat\_crash\_console\_flush 2478~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2479 2480:: 2481 2482 Argument : void 2483 Return : int 2484 2485This API is used by the crash reporting mechanism to force write of all buffered 2486data on the designated crash console. It should only use general purpose 2487registers x0 and x1 to do its work. The return value is 0 on successful 2488completion; otherwise the return value is -1. 2489 2490Build flags 2491----------- 2492 2493- **ENABLE\_PLAT\_COMPAT** 2494 All the platforms ports conforming to this API specification should define 2495 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2496 be disabled. For more details on compatibility layer, refer 2497 `Migration Guide`_. 2498 2499There are some build flags which can be defined by the platform to control 2500inclusion or exclusion of certain BL stages from the FIP image. These flags 2501need to be defined in the platform makefile which will get included by the 2502build system. 2503 2504- **NEED\_BL33** 2505 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2506 build option should be supplied as a build option. The platform has the 2507 option of excluding the BL33 image in the ``fip`` image by defining this flag 2508 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2509 are used, this flag will be set to ``no`` automatically. 2510 2511C Library 2512--------- 2513 2514To avoid subtle toolchain behavioral dependencies, the header files provided 2515by the compiler are not used. The software is built with the ``-nostdinc`` flag 2516to ensure no headers are included from the toolchain inadvertently. Instead the 2517required headers are included in the ARM Trusted Firmware source tree. The 2518library only contains those C library definitions required by the local 2519implementation. If more functionality is required, the needed library functions 2520will need to be added to the local implementation. 2521 2522Versions of `FreeBSD`_ headers can be found in ``include/lib/stdlib``. Some of 2523these headers have been cut down in order to simplify the implementation. In 2524order to minimize changes to the header files, the `FreeBSD`_ layout has been 2525maintained. The generic C library definitions can be found in 2526``include/lib/stdlib`` with more system and machine specific declarations in 2527``include/lib/stdlib/sys`` and ``include/lib/stdlib/machine``. 2528 2529The local C library implementations can be found in ``lib/stdlib``. In order to 2530extend the C library these files may need to be modified. It is recommended to 2531use a release version of `FreeBSD`_ as a starting point. 2532 2533The C library header files in the `FreeBSD`_ source tree are located in the 2534``include`` and ``sys/sys`` directories. `FreeBSD`_ machine specific definitions 2535can be found in the ``sys/<machine-type>`` directories. These files define things 2536like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 2537port for `FreeBSD`_ does not yet exist, the machine specific definitions are 2538based on existing machine types with similar properties (for example SPARC64). 2539 2540Where possible, C library function implementations were taken from `FreeBSD`_ 2541as found in the ``lib/libc`` directory. 2542 2543A copy of the `FreeBSD`_ sources can be downloaded with ``git``. 2544 2545:: 2546 2547 git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 2548 2549Storage abstraction layer 2550------------------------- 2551 2552In order to improve platform independence and portability an storage abstraction 2553layer is used to load data from non-volatile platform storage. 2554 2555Each platform should register devices and their drivers via the Storage layer. 2556These drivers then need to be initialized by bootloader phases as 2557required in their respective ``blx_platform_setup()`` functions. Currently 2558storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2559function uses the storage layer to access non-volatile platform storage. 2560 2561It is mandatory to implement at least one storage driver. For the ARM 2562development platforms the Firmware Image Package (FIP) driver is provided as 2563the default means to load data from storage (see the "Firmware Image Package" 2564section in the `User Guide`_). The storage layer is described in the header file 2565``include/drivers/io/io_storage.h``. The implementation of the common library 2566is in ``drivers/io/io_storage.c`` and the driver files are located in 2567``drivers/io/``. 2568 2569Each IO driver must provide ``io_dev_*`` structures, as described in 2570``drivers/io/io_driver.h``. These are returned via a mandatory registration 2571function that is called on platform initialization. The semi-hosting driver 2572implementation in ``io_semihosting.c`` can be used as an example. 2573 2574The Storage layer provides mechanisms to initialize storage devices before 2575IO operations are called. The basic operations supported by the layer 2576include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2577Drivers do not have to implement all operations, but each platform must 2578provide at least one driver for a device capable of supporting generic 2579operations such as loading a bootloader image. 2580 2581The current implementation only allows for known images to be loaded by the 2582firmware. These images are specified by using their identifiers, as defined in 2583[include/plat/common/platform\_def.h] (or a separate header file included from 2584there). The platform layer (``plat_get_image_source()``) then returns a reference 2585to a device and a driver-specific ``spec`` which will be understood by the driver 2586to allow access to the image data. 2587 2588The layer is designed in such a way that is it possible to chain drivers with 2589other drivers. For example, file-system drivers may be implemented on top of 2590physical block devices, both represented by IO devices with corresponding 2591drivers. In such a case, the file-system "binding" with the block device may 2592be deferred until the file-system device is initialised. 2593 2594The abstraction currently depends on structures being statically allocated 2595by the drivers and callers, as the system does not yet provide a means of 2596dynamically allocating memory. This may also have the affect of limiting the 2597amount of open resources per driver. 2598 2599-------------- 2600 2601*Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.* 2602 2603.. _Migration Guide: platform-migration-guide.rst 2604.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2605.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2606.. _User Guide: user-guide.rst 2607.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 2608.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 2609.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2610.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 2611.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2612.. _Power Domain Topology Design: psci-pd-tree.rst 2613.. _include/common/bl\_common.h: ../include/common/bl_common.h 2614.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2615.. _Firmware Design: firmware-design.rst 2616.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2617.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2618.. _IMF Design Guide: interrupt-framework-design.rst 2619.. _ARM Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2620.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2621.. _FreeBSD: http://www.freebsd.org 2622