1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a53.h> 10#include <hi6220.h> 11#include <hisi_sram_map.h> 12 13 .global pm_asm_code 14 .global pm_asm_code_end 15 .global v7_asm 16 .global v7_asm_end 17 18func pm_asm_code _align=3 19 mov x0, 0 20 msr oslar_el1, x0 21 22 mrs x0, CORTEX_A53_ACTLR_EL1 23 bic x0, x0, #(CORTEX_A53_ACTLR_RADIS | CORTEX_A53_ACTLR_L1RADIS) 24 orr x0, x0, #0x180000 25 orr x0, x0, #0xe000 26 msr CORTEX_A53_ACTLR_EL1, x0 27 28 mrs x3, actlr_el3 29 orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT 30 msr actlr_el3, x3 31 32 mrs x3, actlr_el2 33 orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT 34 msr actlr_el2, x3 35 36 ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD 37 mrs x0, mpidr_el1 38 and x1, x0, #MPIDR_CPU_MASK 39 and x0, x0, #MPIDR_CLUSTER_MASK 40 add x0, x1, x0, LSR #6 41pen: ldr x4, [x3, x0, LSL #3] 42 cbz x4, pen 43 44 mov x0, #0x0 45 mov x1, #0x0 46 mov x2, #0x0 47 mov x3, #0x0 48 br x4 49 50 .ltorg 51 52pm_asm_code_end: 53endfunc pm_asm_code 54 55 /* 56 * By default, all cores in Hi6220 reset with aarch32 mode. 57 * Now hardcode ARMv7 instructions to execute warm reset for 58 * switching aarch64 mode. 59 */ 60 .align 3 61 .section .rodata.v7_asm, "aS" 62v7_asm: 63 .word 0xE1A00000 // nop 64 .word 0xE3A02003 // mov r2, #3 65 .word 0xEE0C2F50 // mcr 15, 0, r2, cr12, cr0, {2} 66 .word 0xE320F003 // wfi 67 68 .ltorg 69v7_asm_end: 70