1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if ENABLE_ASSERTIONS 18 unsigned long long xlat_arch_get_max_supported_pa(void) 19 { 20 /* Physical address space size for long descriptor format. */ 21 return (1ull << 40) - 1ull; 22 } 23 #endif /* ENABLE_ASSERTIONS*/ 24 25 int is_mmu_enabled(void) 26 { 27 return (read_sctlr() & SCTLR_M_BIT) != 0; 28 } 29 30 #if PLAT_XLAT_TABLES_DYNAMIC 31 32 void xlat_arch_tlbi_va(uintptr_t va) 33 { 34 /* 35 * Ensure the translation table write has drained into memory before 36 * invalidating the TLB entry. 37 */ 38 dsbishst(); 39 40 tlbimvaais(TLBI_ADDR(va)); 41 } 42 43 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime __unused) 44 { 45 /* 46 * Ensure the translation table write has drained into memory before 47 * invalidating the TLB entry. 48 */ 49 dsbishst(); 50 51 tlbimvaais(TLBI_ADDR(va)); 52 } 53 54 void xlat_arch_tlbi_va_sync(void) 55 { 56 /* Invalidate all entries from branch predictors. */ 57 bpiallis(); 58 59 /* 60 * A TLB maintenance instruction can complete at any time after 61 * it is issued, but is only guaranteed to be complete after the 62 * execution of DSB by the PE that executed the TLB maintenance 63 * instruction. After the TLB invalidate instruction is 64 * complete, no new memory accesses using the invalidated TLB 65 * entries will be observed by any observer of the system 66 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 67 * "Ordering and completion of TLB maintenance instructions". 68 */ 69 dsbish(); 70 71 /* 72 * The effects of a completed TLB maintenance instruction are 73 * only guaranteed to be visible on the PE that executed the 74 * instruction after the execution of an ISB instruction by the 75 * PE that executed the TLB maintenance instruction. 76 */ 77 isb(); 78 } 79 80 #endif /* PLAT_XLAT_TABLES_DYNAMIC */ 81 82 int xlat_arch_current_el(void) 83 { 84 /* 85 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 86 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 87 */ 88 return 3; 89 } 90 91 uint64_t xlat_arch_get_xn_desc(int el __unused) 92 { 93 return UPPER_ATTRS(XN); 94 } 95 96 /******************************************************************************* 97 * Function for enabling the MMU in Secure PL1, assuming that the page tables 98 * have already been created. 99 ******************************************************************************/ 100 void enable_mmu_arch(unsigned int flags, 101 uint64_t *base_table, 102 unsigned long long max_pa, 103 uintptr_t max_va) 104 { 105 u_register_t mair0, ttbcr, sctlr; 106 uint64_t ttbr0; 107 108 assert(IS_IN_SECURE()); 109 110 sctlr = read_sctlr(); 111 assert((sctlr & SCTLR_M_BIT) == 0); 112 113 /* Invalidate TLBs at the current exception level */ 114 tlbiall(); 115 116 /* Set attributes in the right indices of the MAIR */ 117 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 118 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 119 ATTR_IWBWA_OWBWA_NTR_INDEX); 120 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 121 ATTR_NON_CACHEABLE_INDEX); 122 123 /* 124 * Configure the control register for stage 1 of the PL1&0 translation 125 * regime. 126 */ 127 128 /* Use the Long-descriptor translation table format. */ 129 ttbcr = TTBCR_EAE_BIT; 130 131 /* 132 * Disable translation table walk for addresses that are translated 133 * using TTBR1. Therefore, only TTBR0 is used. 134 */ 135 ttbcr |= TTBCR_EPD1_BIT; 136 137 /* 138 * Limit the input address ranges and memory region sizes translated 139 * using TTBR0 to the given virtual address space size, if smaller than 140 * 32 bits. 141 */ 142 if (max_va != UINT32_MAX) { 143 uintptr_t virtual_addr_space_size = max_va + 1; 144 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 145 /* 146 * __builtin_ctzll(0) is undefined but here we are guaranteed 147 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 148 */ 149 ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size); 150 } 151 152 /* 153 * Set the cacheability and shareability attributes for memory 154 * associated with translation table walks using TTBR0. 155 */ 156 if (flags & XLAT_TABLE_NC) { 157 /* Inner & outer non-cacheable non-shareable. */ 158 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 159 TTBCR_RGN0_INNER_NC; 160 } else { 161 /* Inner & outer WBWA & shareable. */ 162 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 163 TTBCR_RGN0_INNER_WBA; 164 } 165 166 /* Set TTBR0 bits as well */ 167 ttbr0 = (uint64_t)(uintptr_t) base_table; 168 #if ARM_ARCH_AT_LEAST(8, 2) 169 /* 170 * Enable CnP bit so as to share page tables with all PEs. 171 * Mandatory for ARMv8.2 implementations. 172 */ 173 ttbr0 |= TTBR_CNP_BIT; 174 #endif 175 176 /* Now program the relevant system registers */ 177 write_mair0(mair0); 178 write_ttbcr(ttbcr); 179 write64_ttbr0(ttbr0); 180 write64_ttbr1(0); 181 182 /* 183 * Ensure all translation table writes have drained 184 * into memory, the TLB invalidation is complete, 185 * and translation register writes are committed 186 * before enabling the MMU 187 */ 188 dsbish(); 189 isb(); 190 191 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 192 193 if (flags & DISABLE_DCACHE) 194 sctlr &= ~SCTLR_C_BIT; 195 else 196 sctlr |= SCTLR_C_BIT; 197 198 write_sctlr(sctlr); 199 200 /* Ensure the MMU enable takes effect immediately */ 201 isb(); 202 } 203