1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <sys/types.h> 14 #include <utils.h> 15 #include <utils_def.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 #if defined(IMAGE_BL1) || defined(IMAGE_BL31) 20 # define IMAGE_EL 3 21 #else 22 # define IMAGE_EL 1 23 #endif 24 25 static unsigned long long calc_physical_addr_size_bits( 26 unsigned long long max_addr) 27 { 28 /* Physical address can't exceed 48 bits */ 29 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 30 31 /* 48 bits address */ 32 if (max_addr & ADDR_MASK_44_TO_47) 33 return TCR_PS_BITS_256TB; 34 35 /* 44 bits address */ 36 if (max_addr & ADDR_MASK_42_TO_43) 37 return TCR_PS_BITS_16TB; 38 39 /* 42 bits address */ 40 if (max_addr & ADDR_MASK_40_TO_41) 41 return TCR_PS_BITS_4TB; 42 43 /* 40 bits address */ 44 if (max_addr & ADDR_MASK_36_TO_39) 45 return TCR_PS_BITS_1TB; 46 47 /* 36 bits address */ 48 if (max_addr & ADDR_MASK_32_TO_35) 49 return TCR_PS_BITS_64GB; 50 51 return TCR_PS_BITS_4GB; 52 } 53 54 #if ENABLE_ASSERTIONS 55 /* Physical Address ranges supported in the AArch64 Memory Model */ 56 static const unsigned int pa_range_bits_arr[] = { 57 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 58 PARANGE_0101 59 }; 60 61 unsigned long long xlat_arch_get_max_supported_pa(void) 62 { 63 u_register_t pa_range = read_id_aa64mmfr0_el1() & 64 ID_AA64MMFR0_EL1_PARANGE_MASK; 65 66 /* All other values are reserved */ 67 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 68 69 return (1ull << pa_range_bits_arr[pa_range]) - 1ull; 70 } 71 #endif /* ENABLE_ASSERTIONS*/ 72 73 int is_mmu_enabled(void) 74 { 75 #if IMAGE_EL == 1 76 assert(IS_IN_EL(1)); 77 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 78 #elif IMAGE_EL == 3 79 assert(IS_IN_EL(3)); 80 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 81 #endif 82 } 83 84 void xlat_arch_tlbi_va(uintptr_t va) 85 { 86 #if IMAGE_EL == 1 87 assert(IS_IN_EL(1)); 88 xlat_arch_tlbi_va_regime(va, EL1_EL0_REGIME); 89 #elif IMAGE_EL == 3 90 assert(IS_IN_EL(3)); 91 xlat_arch_tlbi_va_regime(va, EL3_REGIME); 92 #endif 93 } 94 95 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime) 96 { 97 /* 98 * Ensure the translation table write has drained into memory before 99 * invalidating the TLB entry. 100 */ 101 dsbishst(); 102 103 /* 104 * This function only supports invalidation of TLB entries for the EL3 105 * and EL1&0 translation regimes. 106 * 107 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 108 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 109 */ 110 if (xlat_regime == EL1_EL0_REGIME) { 111 assert(xlat_arch_current_el() >= 1); 112 tlbivaae1is(TLBI_ADDR(va)); 113 } else { 114 assert(xlat_regime == EL3_REGIME); 115 assert(xlat_arch_current_el() >= 3); 116 tlbivae3is(TLBI_ADDR(va)); 117 } 118 } 119 120 void xlat_arch_tlbi_va_sync(void) 121 { 122 /* 123 * A TLB maintenance instruction can complete at any time after 124 * it is issued, but is only guaranteed to be complete after the 125 * execution of DSB by the PE that executed the TLB maintenance 126 * instruction. After the TLB invalidate instruction is 127 * complete, no new memory accesses using the invalidated TLB 128 * entries will be observed by any observer of the system 129 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 130 * "Ordering and completion of TLB maintenance instructions". 131 */ 132 dsbish(); 133 134 /* 135 * The effects of a completed TLB maintenance instruction are 136 * only guaranteed to be visible on the PE that executed the 137 * instruction after the execution of an ISB instruction by the 138 * PE that executed the TLB maintenance instruction. 139 */ 140 isb(); 141 } 142 143 int xlat_arch_current_el(void) 144 { 145 int el = GET_EL(read_CurrentEl()); 146 147 assert(el > 0); 148 149 return el; 150 } 151 152 uint64_t xlat_arch_get_xn_desc(int el) 153 { 154 if (el == 3) { 155 return UPPER_ATTRS(XN); 156 } else { 157 assert(el == 1); 158 return UPPER_ATTRS(PXN); 159 } 160 } 161 162 /******************************************************************************* 163 * Macro generating the code for the function enabling the MMU in the given 164 * exception level, assuming that the pagetables have already been created. 165 * 166 * _el: Exception level at which the function will run 167 * _tlbi_fct: Function to invalidate the TLBs at the current 168 * exception level 169 ******************************************************************************/ 170 #define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ 171 static void enable_mmu_internal_el##_el(int flags, \ 172 uint64_t mair, \ 173 uint64_t tcr, \ 174 uint64_t ttbr) \ 175 { \ 176 uint32_t sctlr = read_sctlr_el##_el(); \ 177 assert((sctlr & SCTLR_M_BIT) == 0); \ 178 \ 179 /* Invalidate TLBs at the current exception level */ \ 180 _tlbi_fct(); \ 181 \ 182 write_mair_el##_el(mair); \ 183 write_tcr_el##_el(tcr); \ 184 \ 185 /* Set TTBR bits as well */ \ 186 if (ARM_ARCH_AT_LEAST(8, 2)) { \ 187 /* Enable CnP bit so as to share page tables */ \ 188 /* with all PEs. This is mandatory for */ \ 189 /* ARMv8.2 implementations. */ \ 190 ttbr |= TTBR_CNP_BIT; \ 191 } \ 192 write_ttbr0_el##_el(ttbr); \ 193 \ 194 /* Ensure all translation table writes have drained */ \ 195 /* into memory, the TLB invalidation is complete, */ \ 196 /* and translation register writes are committed */ \ 197 /* before enabling the MMU */ \ 198 dsbish(); \ 199 isb(); \ 200 \ 201 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 202 if (flags & DISABLE_DCACHE) \ 203 sctlr &= ~SCTLR_C_BIT; \ 204 else \ 205 sctlr |= SCTLR_C_BIT; \ 206 \ 207 write_sctlr_el##_el(sctlr); \ 208 \ 209 /* Ensure the MMU enable takes effect immediately */ \ 210 isb(); \ 211 } 212 213 /* Define EL1 and EL3 variants of the function enabling the MMU */ 214 #if IMAGE_EL == 1 215 DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) 216 #elif IMAGE_EL == 3 217 DEFINE_ENABLE_MMU_EL(3, tlbialle3) 218 #endif 219 220 void enable_mmu_arch(unsigned int flags, 221 uint64_t *base_table, 222 unsigned long long max_pa, 223 uintptr_t max_va) 224 { 225 uint64_t mair, ttbr, tcr; 226 227 /* Set attributes in the right indices of the MAIR. */ 228 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 229 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 230 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 231 232 ttbr = (uint64_t) base_table; 233 234 /* 235 * Set TCR bits as well. 236 */ 237 238 /* 239 * Limit the input address ranges and memory region sizes translated 240 * using TTBR0 to the given virtual address space size. 241 */ 242 assert(max_va < UINTPTR_MAX); 243 uintptr_t virtual_addr_space_size = max_va + 1; 244 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 245 /* 246 * __builtin_ctzll(0) is undefined but here we are guaranteed that 247 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 248 */ 249 tcr = 64 - __builtin_ctzll(virtual_addr_space_size); 250 251 /* 252 * Set the cacheability and shareability attributes for memory 253 * associated with translation table walks. 254 */ 255 if (flags & XLAT_TABLE_NC) { 256 /* Inner & outer non-cacheable non-shareable. */ 257 tcr |= TCR_SH_NON_SHAREABLE | 258 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 259 } else { 260 /* Inner & outer WBWA & shareable. */ 261 tcr |= TCR_SH_INNER_SHAREABLE | 262 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 263 } 264 265 /* 266 * It is safer to restrict the max physical address accessible by the 267 * hardware as much as possible. 268 */ 269 unsigned long long tcr_ps_bits = calc_physical_addr_size_bits(max_pa); 270 271 #if IMAGE_EL == 1 272 assert(IS_IN_EL(1)); 273 /* 274 * TCR_EL1.EPD1: Disable translation table walk for addresses that are 275 * translated using TTBR1_EL1. 276 */ 277 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 278 enable_mmu_internal_el1(flags, mair, tcr, ttbr); 279 #elif IMAGE_EL == 3 280 assert(IS_IN_EL(3)); 281 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 282 enable_mmu_internal_el3(flags, mair, tcr, ttbr); 283 #endif 284 } 285