xref: /rk3399_ARM-atf/make_helpers/defaults.mk (revision 5722b78cdb4a69d08c3c585aae2fb8dd9cbb9bfc)
1#
2# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
13# The AArch32 Secure Payload to be built as BL32 image
14AARCH32_SP			:= none
15
16# The Target build architecture. Supported values are: aarch64, aarch32.
17ARCH				:= aarch64
18
19# ARM Architecture major and minor versions: 8.0 by default.
20ARM_ARCH_MAJOR			:= 8
21ARM_ARCH_MINOR			:= 0
22
23# Determine the version of ARM GIC architecture to use for interrupt management
24# in EL3. The platform port can change this value if needed.
25ARM_GIC_ARCH			:= 2
26
27# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
28ASM_ASSERTION			:= 0
29
30# Base commit to perform code check on
31BASE_COMMIT			:= origin/master
32
33# By default, consider that the platform may release several CPUs out of reset.
34# The platform Makefile is free to override this value.
35COLD_BOOT_SINGLE_CPU		:= 0
36
37# For Chain of Trust
38CREATE_KEYS			:= 1
39
40# Build flag to include AArch32 registers in cpu context save and restore during
41# world switch. This flag must be set to 0 for AArch64-only platforms.
42CTX_INCLUDE_AARCH32_REGS	:= 1
43
44# Include FP registers in cpu context
45CTX_INCLUDE_FPREGS		:= 0
46
47# Debug build
48DEBUG				:= 0
49
50# Build platform
51DEFAULT_PLAT			:= fvp
52
53# Flag to enable Performance Measurement Framework
54ENABLE_PMF			:= 0
55
56# Flag to enable PSCI STATs functionality
57ENABLE_PSCI_STAT		:= 0
58
59# Flag to enable runtime instrumentation using PMF
60ENABLE_RUNTIME_INSTRUMENTATION	:= 0
61
62# Flag to enable stack corruption protection
63ENABLE_STACK_PROTECTOR		:= 0
64
65# Build flag to treat usage of deprecated platform and framework APIs as error.
66ERROR_DEPRECATED		:= 0
67
68# Byte alignment that each component in FIP is aligned to
69FIP_ALIGN			:= 0
70
71# Default FIP file name
72FIP_NAME			:= fip.bin
73
74# Default FWU_FIP file name
75FWU_FIP_NAME			:= fwu_fip.bin
76
77# For Chain of Trust
78GENERATE_COT			:= 0
79
80# Whether system coherency is managed in hardware, without explicit software
81# operations.
82HW_ASSISTED_COHERENCY		:= 0
83
84# Flag to enable new version of image loading
85LOAD_IMAGE_V2			:= 0
86
87# NS timer register save and restore
88NS_TIMER_SWITCH			:= 0
89
90# Build PL011 UART driver in minimal generic UART mode
91PL011_GENERIC_UART		:= 0
92
93# By default, consider that the platform's reset address is not programmable.
94# The platform Makefile is free to override this value.
95PROGRAMMABLE_RESET_ADDRESS	:= 0
96
97# Flag used to choose the power state format viz Extended State-ID or the
98# Original format.
99PSCI_EXTENDED_STATE_ID		:= 0
100
101# By default, BL1 acts as the reset handler, not BL31
102RESET_TO_BL31			:= 0
103
104# For Chain of Trust
105SAVE_KEYS			:= 0
106
107# Whether code and read-only data should be put on separate memory pages. The
108# platform Makefile is free to override this value.
109SEPARATE_CODE_AND_RODATA	:= 0
110
111# SPD choice
112SPD				:= none
113
114# Flag to introduce an infinite loop in BL1 just before it exits into the next
115# image. This is meant to help debugging the post-BL2 phase.
116SPIN_ON_BL1_EXIT		:= 0
117
118# Flags to build TF with Trusted Boot support
119TRUSTED_BOARD_BOOT		:= 0
120
121# Build option to choose whether Trusted firmware uses Coherent memory or not.
122USE_COHERENT_MEM		:= 1
123
124# Use tbbr_oid.h instead of platform_oid.h
125USE_TBBR_DEFS			= $(ERROR_DEPRECATED)
126
127# Build verbosity
128V				:= 0
129
130# Whether to enable D-Cache early during warm boot. This is usually
131# applicable for platforms wherein interconnect programming is not
132# required to enable cache coherency after warm reset (eg: single cluster
133# platforms).
134WARMBOOT_ENABLE_DCACHE_EARLY	:= 0
135
136# By default, enable Statistical Profiling Extensions.
137# The top level Makefile will disable this feature depending on
138# the target architecture and version number.
139ENABLE_SPE_FOR_LOWER_ELS	:= 1
140
141# SPE is enabled by default but only supported on AArch64 8.2 onwards.
142# Disable it in all other cases.
143ifeq (${ARCH},aarch32)
144    override ENABLE_SPE_FOR_LOWER_ELS := 0
145else
146    ifeq (${ARM_ARCH_MAJOR},8)
147        ifeq ($(ARM_ARCH_MINOR),$(filter $(ARM_ARCH_MINOR),0 1))
148            ENABLE_SPE_FOR_LOWER_ELS := 0
149        endif
150    endif
151endif
152