1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PSCI_H__ 8 #define __PSCI_H__ 9 10 #include <bakery_lock.h> 11 #include <bl_common.h> 12 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 13 #if ENABLE_PLAT_COMPAT 14 #include <psci_compat.h> 15 #endif 16 #include <psci_lib.h> /* To maintain compatibility for SPDs */ 17 #include <utils_def.h> 18 19 /******************************************************************************* 20 * Number of power domains whose state this PSCI implementation can track 21 ******************************************************************************/ 22 #ifdef PLAT_NUM_PWR_DOMAINS 23 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 24 #else 25 #define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) 26 #endif 27 28 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 29 PLATFORM_CORE_COUNT) 30 31 /* This is the power level corresponding to a CPU */ 32 #define PSCI_CPU_PWR_LVL (0) 33 34 /* 35 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 36 * uses the old power_state parameter format which has 2 bits to specify the 37 * power level, this constant is defined to be 3. 38 */ 39 #define PSCI_MAX_PWR_LVL U(3) 40 41 /******************************************************************************* 42 * Defines for runtime services function ids 43 ******************************************************************************/ 44 #define PSCI_VERSION U(0x84000000) 45 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 46 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 47 #define PSCI_CPU_OFF U(0x84000002) 48 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 49 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 50 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 51 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 52 #define PSCI_MIG_AARCH32 U(0x84000005) 53 #define PSCI_MIG_AARCH64 U(0xc4000005) 54 #define PSCI_MIG_INFO_TYPE U(0x84000006) 55 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 56 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 57 #define PSCI_SYSTEM_OFF U(0x84000008) 58 #define PSCI_SYSTEM_RESET U(0x84000009) 59 #define PSCI_FEATURES U(0x8400000A) 60 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 61 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 62 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 63 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 64 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 65 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 66 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 67 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 68 #define PSCI_MEM_PROTECT U(0x84000013) 69 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 70 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 71 72 /* Macro to help build the psci capabilities bitfield */ 73 #define define_psci_cap(x) (U(1) << (x & U(0x1f))) 74 75 /* 76 * Number of PSCI calls (above) implemented 77 */ 78 #if ENABLE_PSCI_STAT 79 #define PSCI_NUM_CALLS U(22) 80 #else 81 #define PSCI_NUM_CALLS U(18) 82 #endif 83 84 /* The macros below are used to identify PSCI calls from the SMC function ID */ 85 #define PSCI_FID_MASK U(0xffe0) 86 #define PSCI_FID_VALUE U(0) 87 #define is_psci_fid(_fid) \ 88 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 89 90 /******************************************************************************* 91 * PSCI Migrate and friends 92 ******************************************************************************/ 93 #define PSCI_TOS_UP_MIG_CAP U(0) 94 #define PSCI_TOS_NOT_UP_MIG_CAP U(1) 95 #define PSCI_TOS_NOT_PRESENT_MP U(2) 96 97 /******************************************************************************* 98 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 99 ******************************************************************************/ 100 #define PSTATE_ID_SHIFT U(0) 101 102 #if PSCI_EXTENDED_STATE_ID 103 #define PSTATE_VALID_MASK U(0xB0000000) 104 #define PSTATE_TYPE_SHIFT U(30) 105 #define PSTATE_ID_MASK U(0xfffffff) 106 #else 107 #define PSTATE_VALID_MASK U(0xFCFE0000) 108 #define PSTATE_TYPE_SHIFT U(16) 109 #define PSTATE_PWR_LVL_SHIFT U(24) 110 #define PSTATE_ID_MASK U(0xffff) 111 #define PSTATE_PWR_LVL_MASK U(0x3) 112 113 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 114 PSTATE_PWR_LVL_MASK) 115 #define psci_make_powerstate(state_id, type, pwrlvl) \ 116 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 117 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 118 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 119 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 120 121 #define PSTATE_TYPE_STANDBY U(0x0) 122 #define PSTATE_TYPE_POWERDOWN U(0x1) 123 #define PSTATE_TYPE_MASK U(0x1) 124 125 #define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ 126 PSTATE_ID_MASK) 127 #define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \ 128 PSTATE_TYPE_MASK) 129 #define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK) 130 131 /******************************************************************************* 132 * PSCI CPU_FEATURES feature flag specific defines 133 ******************************************************************************/ 134 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 135 #define FF_PSTATE_SHIFT U(1) 136 #define FF_PSTATE_ORIG U(0) 137 #define FF_PSTATE_EXTENDED U(1) 138 #if PSCI_EXTENDED_STATE_ID 139 #define FF_PSTATE FF_PSTATE_EXTENDED 140 #else 141 #define FF_PSTATE FF_PSTATE_ORIG 142 #endif 143 144 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 145 #define FF_MODE_SUPPORT_SHIFT U(0) 146 #define FF_SUPPORTS_OS_INIT_MODE U(1) 147 148 /******************************************************************************* 149 * PSCI version 150 ******************************************************************************/ 151 #define PSCI_MAJOR_VER (U(1) << 16) 152 #define PSCI_MINOR_VER U(0x0) 153 154 /******************************************************************************* 155 * PSCI error codes 156 ******************************************************************************/ 157 #define PSCI_E_SUCCESS 0 158 #define PSCI_E_NOT_SUPPORTED -1 159 #define PSCI_E_INVALID_PARAMS -2 160 #define PSCI_E_DENIED -3 161 #define PSCI_E_ALREADY_ON -4 162 #define PSCI_E_ON_PENDING -5 163 #define PSCI_E_INTERN_FAIL -6 164 #define PSCI_E_NOT_PRESENT -7 165 #define PSCI_E_DISABLED -8 166 #define PSCI_E_INVALID_ADDRESS -9 167 168 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 169 170 #ifndef __ASSEMBLY__ 171 172 #include <stdint.h> 173 #include <types.h> 174 175 /* 176 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 177 * CPU. The definitions of these states can be found in Section 5.7.1 in the 178 * PSCI specification (ARM DEN 0022C). 179 */ 180 typedef enum { 181 AFF_STATE_ON = U(0), 182 AFF_STATE_OFF = U(1), 183 AFF_STATE_ON_PENDING = U(2) 184 } aff_info_state_t; 185 186 /* 187 * These are the power states reported by PSCI_NODE_HW_STATE API for the 188 * specified CPU. The definitions of these states can be found in Section 5.15.3 189 * of PSCI specification (ARM DEN 0022C). 190 */ 191 typedef enum { 192 HW_ON = U(0), 193 HW_OFF = U(1), 194 HW_STANDBY = U(2) 195 } node_hw_state_t; 196 197 /* 198 * Macro to represent invalid affinity level within PSCI. 199 */ 200 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 201 202 /* 203 * Type for representing the local power state at a particular level. 204 */ 205 typedef uint8_t plat_local_state_t; 206 207 /* The local state macro used to represent RUN state. */ 208 #define PSCI_LOCAL_STATE_RUN U(0) 209 210 /* 211 * Macro to test whether the plat_local_state is RUN state 212 */ 213 #define is_local_state_run(plat_local_state) \ 214 ((plat_local_state) == PSCI_LOCAL_STATE_RUN) 215 216 /* 217 * Macro to test whether the plat_local_state is RETENTION state 218 */ 219 #define is_local_state_retn(plat_local_state) \ 220 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \ 221 ((plat_local_state) <= PLAT_MAX_RET_STATE)) 222 223 /* 224 * Macro to test whether the plat_local_state is OFF state 225 */ 226 #define is_local_state_off(plat_local_state) \ 227 (((plat_local_state) > PLAT_MAX_RET_STATE) && \ 228 ((plat_local_state) <= PLAT_MAX_OFF_STATE)) 229 230 /***************************************************************************** 231 * This data structure defines the representation of the power state parameter 232 * for its exchange between the generic PSCI code and the platform port. For 233 * example, it is used by the platform port to specify the requested power 234 * states during a power management operation. It is used by the generic code to 235 * inform the platform about the target power states that each level should 236 * enter. 237 ****************************************************************************/ 238 typedef struct psci_power_state { 239 /* 240 * The pwr_domain_state[] stores the local power state at each level 241 * for the CPU. 242 */ 243 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 244 } psci_power_state_t; 245 246 /******************************************************************************* 247 * Structure used to store per-cpu information relevant to the PSCI service. 248 * It is populated in the per-cpu data array. In return we get a guarantee that 249 * this information will not reside on a cache line shared with another cpu. 250 ******************************************************************************/ 251 typedef struct psci_cpu_data { 252 /* State as seen by PSCI Affinity Info API */ 253 aff_info_state_t aff_info_state; 254 255 /* 256 * Highest power level which takes part in a power management 257 * operation. 258 */ 259 unsigned char target_pwrlvl; 260 261 /* The local power state of this CPU */ 262 plat_local_state_t local_state; 263 } psci_cpu_data_t; 264 265 /******************************************************************************* 266 * Structure populated by platform specific code to export routines which 267 * perform common low level power management functions 268 ******************************************************************************/ 269 typedef struct plat_psci_ops { 270 void (*cpu_standby)(plat_local_state_t cpu_state); 271 int (*pwr_domain_on)(u_register_t mpidr); 272 void (*pwr_domain_off)(const psci_power_state_t *target_state); 273 void (*pwr_domain_suspend_pwrdown_early)( 274 const psci_power_state_t *target_state); 275 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 276 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 277 void (*pwr_domain_suspend_finish)( 278 const psci_power_state_t *target_state); 279 void (*pwr_domain_pwr_down_wfi)( 280 const psci_power_state_t *target_state) __dead2; 281 void (*system_off)(void) __dead2; 282 void (*system_reset)(void) __dead2; 283 int (*validate_power_state)(unsigned int power_state, 284 psci_power_state_t *req_state); 285 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 286 void (*get_sys_suspend_power_state)( 287 psci_power_state_t *req_state); 288 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 289 int pwrlvl); 290 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 291 unsigned int power_state, 292 psci_power_state_t *output_state); 293 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 294 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 295 int (*read_mem_protect)(int *val); 296 int (*write_mem_protect)(int val); 297 } plat_psci_ops_t; 298 299 /******************************************************************************* 300 * Function & Data prototypes 301 ******************************************************************************/ 302 unsigned int psci_version(void); 303 int psci_cpu_on(u_register_t target_cpu, 304 uintptr_t entrypoint, 305 u_register_t context_id); 306 int psci_cpu_suspend(unsigned int power_state, 307 uintptr_t entrypoint, 308 u_register_t context_id); 309 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 310 int psci_cpu_off(void); 311 int psci_affinity_info(u_register_t target_affinity, 312 unsigned int lowest_affinity_level); 313 int psci_migrate(u_register_t target_cpu); 314 int psci_migrate_info_type(void); 315 long psci_migrate_info_up_cpu(void); 316 int psci_node_hw_state(u_register_t target_cpu, 317 unsigned int power_level); 318 int psci_features(unsigned int psci_fid); 319 void __dead2 psci_power_down_wfi(void); 320 void psci_arch_setup(void); 321 322 /* 323 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in 324 * AArch64. 325 */ 326 void psci_entrypoint(void) __deprecated; 327 328 #endif /*__ASSEMBLY__*/ 329 330 #endif /* __PSCI_H__ */ 331