refactor(cm): move EL3 registers to global contextCurrently, EL3 context registers are duplicated per-world per-cpu.Some registers have the same value across all CPUs, so this patchmoves these re
refactor(cm): move EL3 registers to global contextCurrently, EL3 context registers are duplicated per-world per-cpu.Some registers have the same value across all CPUs, so this patchmoves these registers out into a per-world context to reducememory usage.Change-Id: I91294e3d5f4af21a58c23599af2bdbd2a747c54aSigned-off-by: Elizabeth Ho <elizabeth.ho@arm.com>Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() onlyThese bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affectEL2 (and lower) execution. Each feat_init_el3() i
refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() onlyThese bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affectEL2 (and lower) execution. Each feat_init_el3() is called long beforeany lower EL has had a chance to execute, so setting the bits at resetis redundant. Removing them from reset code also improves readability ofthe immutable EL3 state.Preserve the original intention for the TTA bit of "enabled for NS anddisabled everywhere else" (inferred from commit messages d4582d3088 and2031d6166a and the comment). This is because CPTR_EL3 will be contextedand so everyone will eventually get whatever NS has anyway.Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>Change-Id: I3d24b45d3ea80882c8e450b2d9db9d5531facec1
refactor(cpufeat): separate the EL2 and EL3 enablement codeCombining the EL2 and EL3 enablement code necessitates that it must becalled at el3_exit, which is the only place with enough context to
refactor(cpufeat): separate the EL2 and EL3 enablement codeCombining the EL2 and EL3 enablement code necessitates that it must becalled at el3_exit, which is the only place with enough context to makethe decision of what needs to be set.Decouple them to allow them to be called from elsewhere.Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>Change-Id: I147764c42771e7d4100699ec8fae98dac0a505c0
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKEDAt the moment we only support access to the trace unit by systemregisters (SYS_REG_TRACE) to be either unconditionally compiled in, or
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKEDAt the moment we only support access to the trace unit by systemregisters (SYS_REG_TRACE) to be either unconditionally compiled in, orto be not supported at all.Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), byadding is_feat_sys_reg_trace_supported(). That function considers bothbuild time settings and runtime information (if needed), and is usedbefore we access SYS_REG_TRACE related registers.The FVP platform decided to compile in support unconditionally (=1),even though this is an optional feature, so it is not available with theFVP model's default command line.Change that to the now supported dynamic option (=2), so the rightdecision can be made by the code at runtime.Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2Signed-off-by: Andre Przywara <andre.przywara@arm.com>
feat(sys_reg_trace): enable trace system registers access from lower NS ELsIntroduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable tracesystem registers access in NS-EL2, or NS-EL1 (when N
feat(sys_reg_trace): enable trace system registers access from lower NS ELsIntroduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable tracesystem registers access in NS-EL2, or NS-EL1 (when NS-EL2 isimplemented but unused).Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18dSigned-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>