1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 139 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 140 if (GET_RW(ep->spsr) != MODE_RW_64) { 141 ERROR("S-EL2 can not be used in AArch32\n."); 142 panic(); 143 } 144 145 scr_el3 |= SCR_EEL2_BIT; 146 } 147 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* 151 * Initialize EL1 context registers unless SPMC is running 152 * at S-EL2. 153 */ 154 #if !SPMD_SPM_AT_SEL2 155 setup_el1_context(ctx, ep); 156 #endif 157 158 manage_extensions_secure(ctx); 159 } 160 161 #if ENABLE_RME 162 /****************************************************************************** 163 * This function performs initializations that are specific to REALM state 164 * and updates the cpu context specified by 'ctx'. 165 *****************************************************************************/ 166 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 167 { 168 u_register_t scr_el3; 169 el3_state_t *state; 170 171 state = get_el3state_ctx(ctx); 172 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 173 174 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 175 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 182 } 183 #endif /* ENABLE_RME */ 184 185 /****************************************************************************** 186 * This function performs initializations that are specific to NON-SECURE state 187 * and updates the cpu context specified by 'ctx'. 188 *****************************************************************************/ 189 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 190 { 191 u_register_t scr_el3; 192 el3_state_t *state; 193 194 state = get_el3state_ctx(ctx); 195 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 196 197 /* SCR_NS: Set the NS bit */ 198 scr_el3 |= SCR_NS_BIT; 199 200 #if !CTX_INCLUDE_PAUTH_REGS 201 /* 202 * If the pointer authentication registers aren't saved during world 203 * switches the value of the registers can be leaked from the Secure to 204 * the Non-secure world. To prevent this, rather than enabling pointer 205 * authentication everywhere, we only enable it in the Non-secure world. 206 * 207 * If the Secure world wants to use pointer authentication, 208 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 209 */ 210 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 211 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 212 213 /* Allow access to Allocation Tags when MTE is implemented. */ 214 scr_el3 |= SCR_ATA_BIT; 215 216 #if HANDLE_EA_EL3_FIRST_NS 217 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 218 scr_el3 |= SCR_EA_BIT; 219 #endif 220 221 #if RAS_TRAP_NS_ERR_REC_ACCESS 222 /* 223 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 224 * and RAS ERX registers from EL1 and EL2(from any security state) 225 * are trapped to EL3. 226 * Set here to trap only for NS EL1/EL2 227 * 228 */ 229 scr_el3 |= SCR_TERR_BIT; 230 #endif 231 232 if (is_feat_csv2_2_supported()) { 233 /* Enable access to the SCXTNUM_ELx registers. */ 234 scr_el3 |= SCR_EnSCXT_BIT; 235 } 236 237 #ifdef IMAGE_BL31 238 /* 239 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 240 * indicated by the interrupt routing model for BL31. 241 */ 242 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 243 #endif 244 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 245 246 /* Initialize EL1 context registers */ 247 setup_el1_context(ctx, ep); 248 249 /* Initialize EL2 context registers */ 250 #if CTX_INCLUDE_EL2_REGS 251 252 /* 253 * Initialize SCTLR_EL2 context register using Endianness value 254 * taken from the entrypoint attribute. 255 */ 256 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 257 sctlr_el2 |= SCTLR_EL2_RES1; 258 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 259 sctlr_el2); 260 261 /* 262 * Program the ICC_SRE_EL2 to make sure the correct bits are set 263 * when restoring NS context. 264 */ 265 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 266 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 267 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 268 icc_sre_el2); 269 270 if (is_feat_hcx_supported()) { 271 /* 272 * Initialize register HCRX_EL2 with its init value. 273 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 274 * chance that this can lead to unexpected behavior in lower 275 * ELs that have not been updated since the introduction of 276 * this feature if not properly initialized, especially when 277 * it comes to those bits that enable/disable traps. 278 */ 279 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 280 HCRX_EL2_INIT_VAL); 281 } 282 #endif /* CTX_INCLUDE_EL2_REGS */ 283 284 manage_extensions_nonsecure(ctx); 285 } 286 287 /******************************************************************************* 288 * The following function performs initialization of the cpu_context 'ctx' 289 * for first use that is common to all security states, and sets the 290 * initial entrypoint state as specified by the entry_point_info structure. 291 * 292 * The EE and ST attributes are used to configure the endianness and secure 293 * timer availability for the new execution context. 294 ******************************************************************************/ 295 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 296 { 297 u_register_t scr_el3; 298 el3_state_t *state; 299 gp_regs_t *gp_regs; 300 301 /* Clear any residual register values from the context */ 302 zeromem(ctx, sizeof(*ctx)); 303 304 /* 305 * SCR_EL3 was initialised during reset sequence in macro 306 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 307 * affect the next EL. 308 * 309 * The following fields are initially set to zero and then updated to 310 * the required value depending on the state of the SPSR_EL3 and the 311 * Security state and entrypoint attributes of the next EL. 312 */ 313 scr_el3 = read_scr(); 314 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 315 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 316 317 /* 318 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 319 * Exception level as specified by SPSR. 320 */ 321 if (GET_RW(ep->spsr) == MODE_RW_64) { 322 scr_el3 |= SCR_RW_BIT; 323 } 324 325 /* 326 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 327 * Secure timer registers to EL3, from AArch64 state only, if specified 328 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 329 * bit always behaves as 1 (i.e. secure physical timer register access 330 * is not trapped) 331 */ 332 if (EP_GET_ST(ep->h.attr) != 0U) { 333 scr_el3 |= SCR_ST_BIT; 334 } 335 336 /* 337 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 338 * SCR_EL3.HXEn. 339 */ 340 if (is_feat_hcx_supported()) { 341 scr_el3 |= SCR_HXEn_BIT; 342 } 343 344 /* 345 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 346 * registers are trapped to EL3. 347 */ 348 #if ENABLE_FEAT_RNG_TRAP 349 scr_el3 |= SCR_TRNDR_BIT; 350 #endif 351 352 #if FAULT_INJECTION_SUPPORT 353 /* Enable fault injection from lower ELs */ 354 scr_el3 |= SCR_FIEN_BIT; 355 #endif 356 357 /* 358 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 359 */ 360 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 361 scr_el3 |= SCR_TCR2EN_BIT; 362 } 363 364 /* 365 * SCR_EL3.PIEN: Enable permission indirection and overlay 366 * registers for AArch64 if present. 367 */ 368 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 369 scr_el3 |= SCR_PIEN_BIT; 370 } 371 372 /* 373 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 374 */ 375 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 376 scr_el3 |= SCR_GCSEn_BIT; 377 } 378 379 /* 380 * CPTR_EL3 was initialized out of reset, copy that value to the 381 * context register. 382 */ 383 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 384 385 /* 386 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 387 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 388 * next mode is Hyp. 389 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 390 * same conditions as HVC instructions and when the processor supports 391 * ARMv8.6-FGT. 392 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 393 * CNTPOFF_EL2 register under the same conditions as HVC instructions 394 * and when the processor supports ECV. 395 */ 396 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 397 || ((GET_RW(ep->spsr) != MODE_RW_64) 398 && (GET_M32(ep->spsr) == MODE32_hyp))) { 399 scr_el3 |= SCR_HCE_BIT; 400 401 if (is_feat_fgt_supported()) { 402 scr_el3 |= SCR_FGTEN_BIT; 403 } 404 405 if (is_feat_ecv_supported()) { 406 scr_el3 |= SCR_ECVEN_BIT; 407 } 408 } 409 410 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 411 if (is_feat_twed_supported()) { 412 /* Set delay in SCR_EL3 */ 413 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 414 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 415 << SCR_TWEDEL_SHIFT); 416 417 /* Enable WFE delay */ 418 scr_el3 |= SCR_TWEDEn_BIT; 419 } 420 421 /* 422 * Populate EL3 state so that we've the right context 423 * before doing ERET 424 */ 425 state = get_el3state_ctx(ctx); 426 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 427 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 428 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 429 430 /* 431 * Store the X0-X7 value from the entrypoint into the context 432 * Use memcpy as we are in control of the layout of the structures 433 */ 434 gp_regs = get_gpregs_ctx(ctx); 435 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 436 } 437 438 /******************************************************************************* 439 * Context management library initialization routine. This library is used by 440 * runtime services to share pointers to 'cpu_context' structures for secure 441 * non-secure and realm states. Management of the structures and their associated 442 * memory is not done by the context management library e.g. the PSCI service 443 * manages the cpu context used for entry from and exit to the non-secure state. 444 * The Secure payload dispatcher service manages the context(s) corresponding to 445 * the secure state. It also uses this library to get access to the non-secure 446 * state cpu context pointers. 447 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 448 * which will be used for programming an entry into a lower EL. The same context 449 * will be used to save state upon exception entry from that EL. 450 ******************************************************************************/ 451 void __init cm_init(void) 452 { 453 /* 454 * The context management library has only global data to initialize, but 455 * that will be done when the BSS is zeroed out. 456 */ 457 } 458 459 /******************************************************************************* 460 * This is the high-level function used to initialize the cpu_context 'ctx' for 461 * first use. It performs initializations that are common to all security states 462 * and initializations specific to the security state specified in 'ep' 463 ******************************************************************************/ 464 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 465 { 466 unsigned int security_state; 467 468 assert(ctx != NULL); 469 470 /* 471 * Perform initializations that are common 472 * to all security states 473 */ 474 setup_context_common(ctx, ep); 475 476 security_state = GET_SECURITY_STATE(ep->h.attr); 477 478 /* Perform security state specific initializations */ 479 switch (security_state) { 480 case SECURE: 481 setup_secure_context(ctx, ep); 482 break; 483 #if ENABLE_RME 484 case REALM: 485 setup_realm_context(ctx, ep); 486 break; 487 #endif 488 case NON_SECURE: 489 setup_ns_context(ctx, ep); 490 break; 491 default: 492 ERROR("Invalid security state\n"); 493 panic(); 494 break; 495 } 496 } 497 498 /******************************************************************************* 499 * Enable architecture extensions on first entry to Non-secure world. 500 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 501 * it is zero. This function updates some registers in-place and its contents 502 * are being prepared to be moved to cm_manage_extensions_el3 and 503 * cm_manage_extensions_nonsecure. 504 ******************************************************************************/ 505 static void manage_extensions_nonsecure_mixed(bool el2_unused, cpu_context_t *ctx) 506 { 507 #if IMAGE_BL31 508 if (is_feat_amu_supported()) { 509 amu_enable(el2_unused, ctx); 510 } 511 #endif /* IMAGE_BL31 */ 512 } 513 514 /******************************************************************************* 515 * Enable architecture extensions for EL3 execution. This function only updates 516 * registers in-place which are expected to either never change or be 517 * overwritten by el3_exit. 518 ******************************************************************************/ 519 #if IMAGE_BL31 520 void cm_manage_extensions_el3(void) 521 { 522 if (is_feat_spe_supported()) { 523 spe_init_el3(); 524 } 525 526 if (is_feat_sme_supported()) { 527 sme_init_el3(); 528 } 529 530 if (is_feat_mpam_supported()) { 531 mpam_init_el3(); 532 } 533 534 if (is_feat_trbe_supported()) { 535 trbe_init_el3(); 536 } 537 538 if (is_feat_brbe_supported()) { 539 brbe_init_el3(); 540 } 541 542 if (is_feat_trf_supported()) { 543 trf_init_el3(); 544 } 545 546 pmuv3_init_el3(); 547 } 548 #endif /* IMAGE_BL31 */ 549 550 /******************************************************************************* 551 * Enable architecture extensions on first entry to Non-secure world. 552 ******************************************************************************/ 553 static void manage_extensions_nonsecure(cpu_context_t *ctx) 554 { 555 #if IMAGE_BL31 556 /* Enable SVE and FPU/SIMD */ 557 if (is_feat_sve_supported()) { 558 sve_enable(ctx); 559 } 560 561 if (is_feat_sme_supported()) { 562 sme_enable(ctx); 563 } 564 565 if (is_feat_sys_reg_trace_supported()) { 566 sys_reg_trace_enable(ctx); 567 } 568 569 pmuv3_enable(ctx); 570 #endif /* IMAGE_BL31 */ 571 } 572 573 /******************************************************************************* 574 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 575 * world when EL2 is empty and unused. 576 ******************************************************************************/ 577 static void manage_extensions_nonsecure_el2_unused(void) 578 { 579 #if IMAGE_BL31 580 if (is_feat_spe_supported()) { 581 spe_init_el2_unused(); 582 } 583 584 if (is_feat_mpam_supported()) { 585 mpam_init_el2_unused(); 586 } 587 588 if (is_feat_trbe_supported()) { 589 trbe_init_el2_unused(); 590 } 591 592 if (is_feat_sys_reg_trace_supported()) { 593 sys_reg_trace_init_el2_unused(); 594 } 595 596 if (is_feat_trf_supported()) { 597 trf_init_el2_unused(); 598 } 599 600 pmuv3_init_el2_unused(); 601 602 if (is_feat_sve_supported()) { 603 sve_init_el2_unused(); 604 } 605 606 if (is_feat_sme_supported()) { 607 sme_init_el2_unused(); 608 } 609 #endif /* IMAGE_BL31 */ 610 } 611 612 /******************************************************************************* 613 * Enable architecture extensions on first entry to Secure world. 614 ******************************************************************************/ 615 static void manage_extensions_secure(cpu_context_t *ctx) 616 { 617 #if IMAGE_BL31 618 if (is_feat_sve_supported()) { 619 if (ENABLE_SVE_FOR_SWD) { 620 /* 621 * Enable SVE and FPU in secure context, secure manager must 622 * ensure that the SVE and FPU register contexts are properly 623 * managed. 624 */ 625 sve_enable(ctx); 626 } else { 627 /* 628 * Disable SVE and FPU in secure context so non-secure world 629 * can safely use them. 630 */ 631 sve_disable(ctx); 632 } 633 } 634 635 if (is_feat_sme_supported()) { 636 if (ENABLE_SME_FOR_SWD) { 637 /* 638 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 639 * must ensure SME, SVE, and FPU/SIMD context properly managed. 640 */ 641 sme_init_el3(); 642 sme_enable(ctx); 643 } else { 644 /* 645 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 646 * world can safely use the associated registers. 647 */ 648 sme_disable(ctx); 649 } 650 } 651 #endif /* IMAGE_BL31 */ 652 } 653 654 /******************************************************************************* 655 * The following function initializes the cpu_context for a CPU specified by 656 * its `cpu_idx` for first use, and sets the initial entrypoint state as 657 * specified by the entry_point_info structure. 658 ******************************************************************************/ 659 void cm_init_context_by_index(unsigned int cpu_idx, 660 const entry_point_info_t *ep) 661 { 662 cpu_context_t *ctx; 663 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 664 cm_setup_context(ctx, ep); 665 } 666 667 /******************************************************************************* 668 * The following function initializes the cpu_context for the current CPU 669 * for first use, and sets the initial entrypoint state as specified by the 670 * entry_point_info structure. 671 ******************************************************************************/ 672 void cm_init_my_context(const entry_point_info_t *ep) 673 { 674 cpu_context_t *ctx; 675 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 676 cm_setup_context(ctx, ep); 677 } 678 679 /******************************************************************************* 680 * Prepare the CPU system registers for first entry into realm, secure, or 681 * normal world. 682 * 683 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 684 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 685 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 686 * For all entries, the EL1 registers are initialized from the cpu_context 687 ******************************************************************************/ 688 void cm_prepare_el3_exit(uint32_t security_state) 689 { 690 u_register_t sctlr_elx, scr_el3, mdcr_el2; 691 cpu_context_t *ctx = cm_get_context(security_state); 692 bool el2_unused = false; 693 uint64_t hcr_el2 = 0U; 694 695 assert(ctx != NULL); 696 697 if (security_state == NON_SECURE) { 698 uint64_t el2_implemented = el_implemented(2); 699 700 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 701 CTX_SCR_EL3); 702 703 if (((scr_el3 & SCR_HCE_BIT) != 0U) 704 || (el2_implemented != EL_IMPL_NONE)) { 705 /* 706 * If context is not being used for EL2, initialize 707 * HCRX_EL2 with its init value here. 708 */ 709 if (is_feat_hcx_supported()) { 710 write_hcrx_el2(HCRX_EL2_INIT_VAL); 711 } 712 } 713 714 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 715 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 716 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 717 CTX_SCTLR_EL1); 718 sctlr_elx &= SCTLR_EE_BIT; 719 sctlr_elx |= SCTLR_EL2_RES1; 720 #if ERRATA_A75_764081 721 /* 722 * If workaround of errata 764081 for Cortex-A75 is used 723 * then set SCTLR_EL2.IESB to enable Implicit Error 724 * Synchronization Barrier. 725 */ 726 sctlr_elx |= SCTLR_IESB_BIT; 727 #endif 728 write_sctlr_el2(sctlr_elx); 729 } else if (el2_implemented != EL_IMPL_NONE) { 730 el2_unused = true; 731 732 /* 733 * EL2 present but unused, need to disable safely. 734 * SCTLR_EL2 can be ignored in this case. 735 * 736 * Set EL2 register width appropriately: Set HCR_EL2 737 * field to match SCR_EL3.RW. 738 */ 739 if ((scr_el3 & SCR_RW_BIT) != 0U) 740 hcr_el2 |= HCR_RW_BIT; 741 742 /* 743 * For Armv8.3 pointer authentication feature, disable 744 * traps to EL2 when accessing key registers or using 745 * pointer authentication instructions from lower ELs. 746 */ 747 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 748 749 write_hcr_el2(hcr_el2); 750 751 /* 752 * Initialise CPTR_EL2 setting all fields rather than 753 * relying on the hw. All fields have architecturally 754 * UNKNOWN reset values. 755 */ 756 write_cptr_el2(CPTR_EL2_RESET_VAL); 757 758 /* 759 * Initialise CNTHCTL_EL2. All fields are 760 * architecturally UNKNOWN on reset and are set to zero 761 * except for field(s) listed below. 762 * 763 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 764 * Hyp mode of Non-secure EL0 and EL1 accesses to the 765 * physical timer registers. 766 * 767 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 768 * Hyp mode of Non-secure EL0 and EL1 accesses to the 769 * physical counter registers. 770 */ 771 write_cnthctl_el2(CNTHCTL_RESET_VAL | 772 EL1PCEN_BIT | EL1PCTEN_BIT); 773 774 /* 775 * Initialise CNTVOFF_EL2 to zero as it resets to an 776 * architecturally UNKNOWN value. 777 */ 778 write_cntvoff_el2(0); 779 780 /* 781 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 782 * MPIDR_EL1 respectively. 783 */ 784 write_vpidr_el2(read_midr_el1()); 785 write_vmpidr_el2(read_mpidr_el1()); 786 787 /* 788 * Initialise VTTBR_EL2. All fields are architecturally 789 * UNKNOWN on reset. 790 * 791 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 792 * 2 address translation is disabled, cache maintenance 793 * operations depend on the VMID. 794 * 795 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 796 * translation is disabled. 797 */ 798 write_vttbr_el2(VTTBR_RESET_VAL & 799 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 800 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 801 802 /* 803 * Initialise MDCR_EL2, setting all fields rather than 804 * relying on hw. Some fields are architecturally 805 * UNKNOWN on reset. 806 * 807 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 808 * EL1 System register accesses to the Debug ROM 809 * registers are not trapped to EL2. 810 * 811 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 812 * System register accesses to the powerdown debug 813 * registers are not trapped to EL2. 814 * 815 * MDCR_EL2.TDA: Set to zero so that System register 816 * accesses to the debug registers do not trap to EL2. 817 * 818 * MDCR_EL2.TDE: Set to zero so that debug exceptions 819 * are not routed to EL2. 820 */ 821 mdcr_el2 = ((MDCR_EL2_RESET_VAL) & 822 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 823 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT)); 824 825 write_mdcr_el2(mdcr_el2); 826 827 /* 828 * Initialise HSTR_EL2. All fields are architecturally 829 * UNKNOWN on reset. 830 * 831 * HSTR_EL2.T<n>: Set all these fields to zero so that 832 * Non-secure EL0 or EL1 accesses to System registers 833 * do not trap to EL2. 834 */ 835 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 836 /* 837 * Initialise CNTHP_CTL_EL2. All fields are 838 * architecturally UNKNOWN on reset. 839 * 840 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 841 * physical timer and prevent timer interrupts. 842 */ 843 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 844 ~(CNTHP_CTL_ENABLE_BIT)); 845 846 manage_extensions_nonsecure_el2_unused(); 847 } 848 manage_extensions_nonsecure_mixed(el2_unused, ctx); 849 } 850 851 cm_el1_sysregs_context_restore(security_state); 852 cm_set_next_eret_context(security_state); 853 } 854 855 #if CTX_INCLUDE_EL2_REGS 856 857 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 858 { 859 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 860 if (is_feat_amu_supported()) { 861 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 862 } 863 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 864 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 865 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 866 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 867 } 868 869 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 870 { 871 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 872 if (is_feat_amu_supported()) { 873 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 874 } 875 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 876 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 877 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 878 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 879 } 880 881 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 882 { 883 u_register_t mpam_idr = read_mpamidr_el1(); 884 885 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 886 887 /* 888 * The context registers that we intend to save would be part of the 889 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 890 */ 891 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 892 return; 893 } 894 895 /* 896 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 897 * MPAMIDR_HAS_HCR_BIT == 1. 898 */ 899 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 900 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 901 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 902 903 /* 904 * The number of MPAMVPM registers is implementation defined, their 905 * number is stored in the MPAMIDR_EL1 register. 906 */ 907 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 908 case 7: 909 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 910 __fallthrough; 911 case 6: 912 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 913 __fallthrough; 914 case 5: 915 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 916 __fallthrough; 917 case 4: 918 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 919 __fallthrough; 920 case 3: 921 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 922 __fallthrough; 923 case 2: 924 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 925 __fallthrough; 926 case 1: 927 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 928 break; 929 } 930 } 931 932 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 933 { 934 u_register_t mpam_idr = read_mpamidr_el1(); 935 936 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 937 938 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 939 return; 940 } 941 942 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 943 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 944 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 945 946 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 947 case 7: 948 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 949 __fallthrough; 950 case 6: 951 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 952 __fallthrough; 953 case 5: 954 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 955 __fallthrough; 956 case 4: 957 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 958 __fallthrough; 959 case 3: 960 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 961 __fallthrough; 962 case 2: 963 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 964 __fallthrough; 965 case 1: 966 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 967 break; 968 } 969 } 970 971 /******************************************************************************* 972 * Save EL2 sysreg context 973 ******************************************************************************/ 974 void cm_el2_sysregs_context_save(uint32_t security_state) 975 { 976 u_register_t scr_el3 = read_scr(); 977 978 /* 979 * Always save the non-secure and realm EL2 context, only save the 980 * S-EL2 context if S-EL2 is enabled. 981 */ 982 if ((security_state != SECURE) || 983 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 984 cpu_context_t *ctx; 985 el2_sysregs_t *el2_sysregs_ctx; 986 987 ctx = cm_get_context(security_state); 988 assert(ctx != NULL); 989 990 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 991 992 el2_sysregs_context_save_common(el2_sysregs_ctx); 993 #if CTX_INCLUDE_MTE_REGS 994 el2_sysregs_context_save_mte(el2_sysregs_ctx); 995 #endif 996 if (is_feat_mpam_supported()) { 997 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 998 } 999 1000 if (is_feat_fgt_supported()) { 1001 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1002 } 1003 1004 if (is_feat_ecv_v2_supported()) { 1005 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 1006 read_cntpoff_el2()); 1007 } 1008 1009 if (is_feat_vhe_supported()) { 1010 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 1011 read_contextidr_el2()); 1012 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 1013 read_ttbr1_el2()); 1014 } 1015 1016 if (is_feat_ras_supported()) { 1017 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, 1018 read_vdisr_el2()); 1019 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, 1020 read_vsesr_el2()); 1021 } 1022 1023 if (is_feat_nv2_supported()) { 1024 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1025 read_vncr_el2()); 1026 } 1027 1028 if (is_feat_trf_supported()) { 1029 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1030 } 1031 1032 if (is_feat_csv2_2_supported()) { 1033 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1034 read_scxtnum_el2()); 1035 } 1036 1037 if (is_feat_hcx_supported()) { 1038 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1039 } 1040 if (is_feat_tcr2_supported()) { 1041 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1042 } 1043 if (is_feat_sxpie_supported()) { 1044 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1045 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1046 } 1047 if (is_feat_s2pie_supported()) { 1048 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1049 } 1050 if (is_feat_sxpoe_supported()) { 1051 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1052 } 1053 if (is_feat_gcs_supported()) { 1054 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1055 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1056 } 1057 } 1058 } 1059 1060 /******************************************************************************* 1061 * Restore EL2 sysreg context 1062 ******************************************************************************/ 1063 void cm_el2_sysregs_context_restore(uint32_t security_state) 1064 { 1065 u_register_t scr_el3 = read_scr(); 1066 1067 /* 1068 * Always restore the non-secure and realm EL2 context, only restore the 1069 * S-EL2 context if S-EL2 is enabled. 1070 */ 1071 if ((security_state != SECURE) || 1072 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1073 cpu_context_t *ctx; 1074 el2_sysregs_t *el2_sysregs_ctx; 1075 1076 ctx = cm_get_context(security_state); 1077 assert(ctx != NULL); 1078 1079 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1080 1081 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1082 #if CTX_INCLUDE_MTE_REGS 1083 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 1084 #endif 1085 if (is_feat_mpam_supported()) { 1086 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1087 } 1088 1089 if (is_feat_fgt_supported()) { 1090 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1091 } 1092 1093 if (is_feat_ecv_v2_supported()) { 1094 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1095 CTX_CNTPOFF_EL2)); 1096 } 1097 1098 if (is_feat_vhe_supported()) { 1099 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1100 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1101 } 1102 1103 if (is_feat_ras_supported()) { 1104 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1105 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1106 } 1107 1108 if (is_feat_nv2_supported()) { 1109 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1110 } 1111 if (is_feat_trf_supported()) { 1112 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1113 } 1114 1115 if (is_feat_csv2_2_supported()) { 1116 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1117 CTX_SCXTNUM_EL2)); 1118 } 1119 1120 if (is_feat_hcx_supported()) { 1121 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1122 } 1123 if (is_feat_tcr2_supported()) { 1124 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1125 } 1126 if (is_feat_sxpie_supported()) { 1127 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1128 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1129 } 1130 if (is_feat_s2pie_supported()) { 1131 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1132 } 1133 if (is_feat_sxpoe_supported()) { 1134 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1135 } 1136 if (is_feat_gcs_supported()) { 1137 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1138 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1139 } 1140 } 1141 } 1142 #endif /* CTX_INCLUDE_EL2_REGS */ 1143 1144 /******************************************************************************* 1145 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1146 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1147 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1148 * cm_prepare_el3_exit function. 1149 ******************************************************************************/ 1150 void cm_prepare_el3_exit_ns(void) 1151 { 1152 #if CTX_INCLUDE_EL2_REGS 1153 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1154 assert(ctx != NULL); 1155 1156 /* Assert that EL2 is used. */ 1157 #if ENABLE_ASSERTIONS 1158 el3_state_t *state = get_el3state_ctx(ctx); 1159 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1160 #endif 1161 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1162 (el_implemented(2U) != EL_IMPL_NONE)); 1163 1164 /* 1165 * Currently some extensions are configured using 1166 * direct register updates. Therefore, do this here 1167 * instead of when setting up context. 1168 */ 1169 manage_extensions_nonsecure_mixed(0, ctx); 1170 1171 /* 1172 * Set the NS bit to be able to access the ICC_SRE_EL2 1173 * register when restoring context. 1174 */ 1175 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1176 1177 /* 1178 * Ensure the NS bit change is committed before the EL2/EL1 1179 * state restoration. 1180 */ 1181 isb(); 1182 1183 /* Restore EL2 and EL1 sysreg contexts */ 1184 cm_el2_sysregs_context_restore(NON_SECURE); 1185 cm_el1_sysregs_context_restore(NON_SECURE); 1186 cm_set_next_eret_context(NON_SECURE); 1187 #else 1188 cm_prepare_el3_exit(NON_SECURE); 1189 #endif /* CTX_INCLUDE_EL2_REGS */ 1190 } 1191 1192 /******************************************************************************* 1193 * The next four functions are used by runtime services to save and restore 1194 * EL1 context on the 'cpu_context' structure for the specified security 1195 * state. 1196 ******************************************************************************/ 1197 void cm_el1_sysregs_context_save(uint32_t security_state) 1198 { 1199 cpu_context_t *ctx; 1200 1201 ctx = cm_get_context(security_state); 1202 assert(ctx != NULL); 1203 1204 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1205 1206 #if IMAGE_BL31 1207 if (security_state == SECURE) 1208 PUBLISH_EVENT(cm_exited_secure_world); 1209 else 1210 PUBLISH_EVENT(cm_exited_normal_world); 1211 #endif 1212 } 1213 1214 void cm_el1_sysregs_context_restore(uint32_t security_state) 1215 { 1216 cpu_context_t *ctx; 1217 1218 ctx = cm_get_context(security_state); 1219 assert(ctx != NULL); 1220 1221 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1222 1223 #if IMAGE_BL31 1224 if (security_state == SECURE) 1225 PUBLISH_EVENT(cm_entering_secure_world); 1226 else 1227 PUBLISH_EVENT(cm_entering_normal_world); 1228 #endif 1229 } 1230 1231 /******************************************************************************* 1232 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1233 * given security state with the given entrypoint 1234 ******************************************************************************/ 1235 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1236 { 1237 cpu_context_t *ctx; 1238 el3_state_t *state; 1239 1240 ctx = cm_get_context(security_state); 1241 assert(ctx != NULL); 1242 1243 /* Populate EL3 state so that ERET jumps to the correct entry */ 1244 state = get_el3state_ctx(ctx); 1245 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1246 } 1247 1248 /******************************************************************************* 1249 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1250 * pertaining to the given security state 1251 ******************************************************************************/ 1252 void cm_set_elr_spsr_el3(uint32_t security_state, 1253 uintptr_t entrypoint, uint32_t spsr) 1254 { 1255 cpu_context_t *ctx; 1256 el3_state_t *state; 1257 1258 ctx = cm_get_context(security_state); 1259 assert(ctx != NULL); 1260 1261 /* Populate EL3 state so that ERET jumps to the correct entry */ 1262 state = get_el3state_ctx(ctx); 1263 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1264 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1265 } 1266 1267 /******************************************************************************* 1268 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1269 * pertaining to the given security state using the value and bit position 1270 * specified in the parameters. It preserves all other bits. 1271 ******************************************************************************/ 1272 void cm_write_scr_el3_bit(uint32_t security_state, 1273 uint32_t bit_pos, 1274 uint32_t value) 1275 { 1276 cpu_context_t *ctx; 1277 el3_state_t *state; 1278 u_register_t scr_el3; 1279 1280 ctx = cm_get_context(security_state); 1281 assert(ctx != NULL); 1282 1283 /* Ensure that the bit position is a valid one */ 1284 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1285 1286 /* Ensure that the 'value' is only a bit wide */ 1287 assert(value <= 1U); 1288 1289 /* 1290 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1291 * and set it to its new value. 1292 */ 1293 state = get_el3state_ctx(ctx); 1294 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1295 scr_el3 &= ~(1UL << bit_pos); 1296 scr_el3 |= (u_register_t)value << bit_pos; 1297 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1298 } 1299 1300 /******************************************************************************* 1301 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1302 * given security state. 1303 ******************************************************************************/ 1304 u_register_t cm_get_scr_el3(uint32_t security_state) 1305 { 1306 cpu_context_t *ctx; 1307 el3_state_t *state; 1308 1309 ctx = cm_get_context(security_state); 1310 assert(ctx != NULL); 1311 1312 /* Populate EL3 state so that ERET jumps to the correct entry */ 1313 state = get_el3state_ctx(ctx); 1314 return read_ctx_reg(state, CTX_SCR_EL3); 1315 } 1316 1317 /******************************************************************************* 1318 * This function is used to program the context that's used for exception 1319 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1320 * the required security state 1321 ******************************************************************************/ 1322 void cm_set_next_eret_context(uint32_t security_state) 1323 { 1324 cpu_context_t *ctx; 1325 1326 ctx = cm_get_context(security_state); 1327 assert(ctx != NULL); 1328 1329 cm_set_next_context(ctx); 1330 } 1331