1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_ASGI1R S3_0_C12_C11_6 83 #define ICC_SRE_EL1 S3_0_C12_C12_5 84 #define ICC_SRE_EL2 S3_4_C12_C9_5 85 #define ICC_SRE_EL3 S3_6_C12_C12_5 86 #define ICC_CTLR_EL1 S3_0_C12_C12_4 87 #define ICC_CTLR_EL3 S3_6_C12_C12_4 88 #define ICC_PMR_EL1 S3_0_C4_C6_0 89 #define ICC_RPR_EL1 S3_0_C12_C11_3 90 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 91 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 92 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 93 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 94 #define ICC_IAR0_EL1 S3_0_c12_c8_0 95 #define ICC_IAR1_EL1 S3_0_c12_c12_0 96 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 97 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 98 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 99 100 /******************************************************************************* 101 * Definitions for EL2 system registers for save/restore routine 102 ******************************************************************************/ 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C6_0 113 #define MPAMVPM1_EL2 S3_4_C10_C6_1 114 #define MPAMVPM2_EL2 S3_4_C10_C6_2 115 #define MPAMVPM3_EL2 S3_4_C10_C6_3 116 #define MPAMVPM4_EL2 S3_4_C10_C6_4 117 #define MPAMVPM5_EL2 S3_4_C10_C6_5 118 #define MPAMVPM6_EL2 S3_4_C10_C6_6 119 #define MPAMVPM7_EL2 S3_4_C10_C6_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 125 #define TTBR1_EL2 S3_4_C2_C0_1 126 127 /******************************************************************************* 128 * Generic timer memory mapped registers & offsets 129 ******************************************************************************/ 130 #define CNTCR_OFF U(0x000) 131 #define CNTCV_OFF U(0x008) 132 #define CNTFID_OFF U(0x020) 133 134 #define CNTCR_EN (U(1) << 0) 135 #define CNTCR_HDBG (U(1) << 1) 136 #define CNTCR_FCREQ(x) ((x) << 8) 137 138 /******************************************************************************* 139 * System register bit definitions 140 ******************************************************************************/ 141 /* CLIDR definitions */ 142 #define LOUIS_SHIFT U(21) 143 #define LOC_SHIFT U(24) 144 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 145 #define CLIDR_FIELD_WIDTH U(3) 146 147 /* CSSELR definitions */ 148 #define LEVEL_SHIFT U(1) 149 150 /* Data cache set/way op type defines */ 151 #define DCISW U(0x0) 152 #define DCCISW U(0x1) 153 #if ERRATA_A53_827319 154 #define DCCSW DCCISW 155 #else 156 #define DCCSW U(0x2) 157 #endif 158 159 /* ID_AA64PFR0_EL1 definitions */ 160 #define ID_AA64PFR0_EL0_SHIFT U(0) 161 #define ID_AA64PFR0_EL1_SHIFT U(4) 162 #define ID_AA64PFR0_EL2_SHIFT U(8) 163 #define ID_AA64PFR0_EL3_SHIFT U(12) 164 165 #define ID_AA64PFR0_AMU_SHIFT U(44) 166 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 167 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 168 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 169 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 170 171 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 172 173 #define ID_AA64PFR0_GIC_SHIFT U(24) 174 #define ID_AA64PFR0_GIC_WIDTH U(4) 175 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 176 177 #define ID_AA64PFR0_SVE_SHIFT U(32) 178 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 179 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 180 #define ID_AA64PFR0_SVE_LENGTH U(4) 181 182 #define ID_AA64PFR0_SEL2_SHIFT U(36) 183 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 184 185 #define ID_AA64PFR0_MPAM_SHIFT U(40) 186 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 187 188 #define ID_AA64PFR0_DIT_SHIFT U(48) 189 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 190 #define ID_AA64PFR0_DIT_LENGTH U(4) 191 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 192 193 #define ID_AA64PFR0_CSV2_SHIFT U(56) 194 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 195 #define ID_AA64PFR0_CSV2_LENGTH U(4) 196 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 197 198 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 199 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 200 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 201 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 202 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 203 204 #define ID_AA64PFR0_RAS_SHIFT U(28) 205 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 206 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 207 #define ID_AA64PFR0_RAS_LENGTH U(4) 208 209 /* Exception level handling */ 210 #define EL_IMPL_NONE ULL(0) 211 #define EL_IMPL_A64ONLY ULL(1) 212 #define EL_IMPL_A64_A32 ULL(2) 213 214 /* ID_AA64DFR0_EL1.TraceVer definitions */ 215 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 216 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 217 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 218 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 219 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 220 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 221 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 222 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 223 224 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 225 #define ID_AA64DFR0_PMS_SHIFT U(32) 226 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 227 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 228 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 229 230 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 231 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 232 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 233 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 234 235 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 236 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 237 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 238 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 239 240 /* ID_AA64DFR0_EL1.BRBE definitions */ 241 #define ID_AA64DFR0_BRBE_SHIFT U(52) 242 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 243 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 244 245 /* ID_AA64ISAR0_EL1 definitions */ 246 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 247 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 248 249 /* ID_AA64ISAR1_EL1 definitions */ 250 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 251 252 #define ID_AA64ISAR1_GPI_SHIFT U(28) 253 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 254 #define ID_AA64ISAR1_GPA_SHIFT U(24) 255 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 256 257 #define ID_AA64ISAR1_API_SHIFT U(8) 258 #define ID_AA64ISAR1_API_MASK ULL(0xf) 259 #define ID_AA64ISAR1_APA_SHIFT U(4) 260 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 261 262 #define ID_AA64ISAR1_SB_SHIFT U(36) 263 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 264 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 265 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 266 267 /* ID_AA64ISAR2_EL1 definitions */ 268 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 269 270 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 271 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 272 273 #define ID_AA64ISAR2_APA3_SHIFT U(12) 274 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 275 276 /* ID_AA64MMFR0_EL1 definitions */ 277 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 278 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 279 280 #define PARANGE_0000 U(32) 281 #define PARANGE_0001 U(36) 282 #define PARANGE_0010 U(40) 283 #define PARANGE_0011 U(42) 284 #define PARANGE_0100 U(44) 285 #define PARANGE_0101 U(48) 286 #define PARANGE_0110 U(52) 287 288 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 289 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 290 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 291 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 292 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 293 294 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 295 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 296 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 297 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 298 299 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 300 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 301 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 302 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 303 304 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 305 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 306 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 307 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 308 309 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 310 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 311 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 312 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 313 314 /* ID_AA64MMFR1_EL1 definitions */ 315 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 316 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 317 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 318 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 319 320 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 321 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 322 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 323 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 324 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 325 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 326 327 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 328 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 329 330 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 331 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 332 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 333 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 334 335 /* ID_AA64MMFR2_EL1 definitions */ 336 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 337 338 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 339 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 340 341 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 342 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 343 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 344 345 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 346 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 347 348 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 349 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 350 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 351 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 352 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 353 354 /* ID_AA64MMFR3_EL1 definitions */ 355 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 356 357 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 358 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 359 360 /* ID_AA64PFR1_EL1 definitions */ 361 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 362 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 363 364 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 365 366 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 367 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 368 369 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 370 371 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 372 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 373 374 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 375 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 376 377 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 378 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 379 380 /* Memory Tagging Extension is not implemented */ 381 #define MTE_UNIMPLEMENTED U(0) 382 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 383 #define MTE_IMPLEMENTED_EL0 U(1) 384 /* FEAT_MTE2: Full MTE is implemented */ 385 #define MTE_IMPLEMENTED_ELX U(2) 386 /* 387 * FEAT_MTE3: MTE is implemented with support for 388 * asymmetric Tag Check Fault handling 389 */ 390 #define MTE_IMPLEMENTED_ASY U(3) 391 392 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 393 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 394 395 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 396 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 397 398 /* ID_PFR1_EL1 definitions */ 399 #define ID_PFR1_VIRTEXT_SHIFT U(12) 400 #define ID_PFR1_VIRTEXT_MASK U(0xf) 401 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 402 & ID_PFR1_VIRTEXT_MASK) 403 404 /* SCTLR definitions */ 405 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 406 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 407 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 408 409 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 410 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 411 412 #define SCTLR_AARCH32_EL1_RES1 \ 413 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 414 (U(1) << 4) | (U(1) << 3)) 415 416 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 417 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 418 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 419 420 #define SCTLR_M_BIT (ULL(1) << 0) 421 #define SCTLR_A_BIT (ULL(1) << 1) 422 #define SCTLR_C_BIT (ULL(1) << 2) 423 #define SCTLR_SA_BIT (ULL(1) << 3) 424 #define SCTLR_SA0_BIT (ULL(1) << 4) 425 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 426 #define SCTLR_nAA_BIT (ULL(1) << 6) 427 #define SCTLR_ITD_BIT (ULL(1) << 7) 428 #define SCTLR_SED_BIT (ULL(1) << 8) 429 #define SCTLR_UMA_BIT (ULL(1) << 9) 430 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 431 #define SCTLR_EOS_BIT (ULL(1) << 11) 432 #define SCTLR_I_BIT (ULL(1) << 12) 433 #define SCTLR_EnDB_BIT (ULL(1) << 13) 434 #define SCTLR_DZE_BIT (ULL(1) << 14) 435 #define SCTLR_UCT_BIT (ULL(1) << 15) 436 #define SCTLR_NTWI_BIT (ULL(1) << 16) 437 #define SCTLR_NTWE_BIT (ULL(1) << 18) 438 #define SCTLR_WXN_BIT (ULL(1) << 19) 439 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 440 #define SCTLR_IESB_BIT (ULL(1) << 21) 441 #define SCTLR_EIS_BIT (ULL(1) << 22) 442 #define SCTLR_SPAN_BIT (ULL(1) << 23) 443 #define SCTLR_E0E_BIT (ULL(1) << 24) 444 #define SCTLR_EE_BIT (ULL(1) << 25) 445 #define SCTLR_UCI_BIT (ULL(1) << 26) 446 #define SCTLR_EnDA_BIT (ULL(1) << 27) 447 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 448 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 449 #define SCTLR_EnIB_BIT (ULL(1) << 30) 450 #define SCTLR_EnIA_BIT (ULL(1) << 31) 451 #define SCTLR_BT0_BIT (ULL(1) << 35) 452 #define SCTLR_BT1_BIT (ULL(1) << 36) 453 #define SCTLR_BT_BIT (ULL(1) << 36) 454 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 455 #define SCTLR_TCF0_SHIFT U(38) 456 #define SCTLR_TCF0_MASK ULL(3) 457 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 458 459 /* Tag Check Faults in EL0 have no effect on the PE */ 460 #define SCTLR_TCF0_NO_EFFECT U(0) 461 /* Tag Check Faults in EL0 cause a synchronous exception */ 462 #define SCTLR_TCF0_SYNC U(1) 463 /* Tag Check Faults in EL0 are asynchronously accumulated */ 464 #define SCTLR_TCF0_ASYNC U(2) 465 /* 466 * Tag Check Faults in EL0 cause a synchronous exception on reads, 467 * and are asynchronously accumulated on writes 468 */ 469 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 470 471 #define SCTLR_TCF_SHIFT U(40) 472 #define SCTLR_TCF_MASK ULL(3) 473 474 /* Tag Check Faults in EL1 have no effect on the PE */ 475 #define SCTLR_TCF_NO_EFFECT U(0) 476 /* Tag Check Faults in EL1 cause a synchronous exception */ 477 #define SCTLR_TCF_SYNC U(1) 478 /* Tag Check Faults in EL1 are asynchronously accumulated */ 479 #define SCTLR_TCF_ASYNC U(2) 480 /* 481 * Tag Check Faults in EL1 cause a synchronous exception on reads, 482 * and are asynchronously accumulated on writes 483 */ 484 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 485 486 #define SCTLR_ATA0_BIT (ULL(1) << 42) 487 #define SCTLR_ATA_BIT (ULL(1) << 43) 488 #define SCTLR_DSSBS_SHIFT U(44) 489 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 490 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 491 #define SCTLR_TWEDEL_SHIFT U(46) 492 #define SCTLR_TWEDEL_MASK ULL(0xf) 493 #define SCTLR_EnASR_BIT (ULL(1) << 54) 494 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 495 #define SCTLR_EnALS_BIT (ULL(1) << 56) 496 #define SCTLR_EPAN_BIT (ULL(1) << 57) 497 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 498 499 /* CPACR_EL1 definitions */ 500 #define CPACR_EL1_FPEN(x) ((x) << 20) 501 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 502 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 503 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 504 505 /* SCR definitions */ 506 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 507 #define SCR_NSE_SHIFT U(62) 508 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 509 #define SCR_GPF_BIT (UL(1) << 48) 510 #define SCR_TWEDEL_SHIFT U(30) 511 #define SCR_TWEDEL_MASK ULL(0xf) 512 #define SCR_TCR2EN_BIT (UL(1) << 43) 513 #define SCR_TRNDR_BIT (UL(1) << 40) 514 #define SCR_HXEn_BIT (UL(1) << 38) 515 #define SCR_ENTP2_SHIFT U(41) 516 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 517 #define SCR_AMVOFFEN_SHIFT U(35) 518 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 519 #define SCR_TWEDEn_BIT (UL(1) << 29) 520 #define SCR_ECVEN_BIT (UL(1) << 28) 521 #define SCR_FGTEN_BIT (UL(1) << 27) 522 #define SCR_ATA_BIT (UL(1) << 26) 523 #define SCR_EnSCXT_BIT (UL(1) << 25) 524 #define SCR_FIEN_BIT (UL(1) << 21) 525 #define SCR_EEL2_BIT (UL(1) << 18) 526 #define SCR_API_BIT (UL(1) << 17) 527 #define SCR_APK_BIT (UL(1) << 16) 528 #define SCR_TERR_BIT (UL(1) << 15) 529 #define SCR_TWE_BIT (UL(1) << 13) 530 #define SCR_TWI_BIT (UL(1) << 12) 531 #define SCR_ST_BIT (UL(1) << 11) 532 #define SCR_RW_BIT (UL(1) << 10) 533 #define SCR_SIF_BIT (UL(1) << 9) 534 #define SCR_HCE_BIT (UL(1) << 8) 535 #define SCR_SMD_BIT (UL(1) << 7) 536 #define SCR_EA_BIT (UL(1) << 3) 537 #define SCR_FIQ_BIT (UL(1) << 2) 538 #define SCR_IRQ_BIT (UL(1) << 1) 539 #define SCR_NS_BIT (UL(1) << 0) 540 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 541 #define SCR_RESET_VAL SCR_RES1_BITS 542 543 /* MDCR_EL3 definitions */ 544 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 545 #define MDCR_MPMX_BIT (ULL(1) << 35) 546 #define MDCR_MCCD_BIT (ULL(1) << 34) 547 #define MDCR_SBRBE_SHIFT U(32) 548 #define MDCR_SBRBE_MASK ULL(0x3) 549 #define MDCR_NSTB(x) ((x) << 24) 550 #define MDCR_NSTB_EL1 ULL(0x3) 551 #define MDCR_NSTBE (ULL(1) << 26) 552 #define MDCR_MTPME_BIT (ULL(1) << 28) 553 #define MDCR_TDCC_BIT (ULL(1) << 27) 554 #define MDCR_SCCD_BIT (ULL(1) << 23) 555 #define MDCR_EPMAD_BIT (ULL(1) << 21) 556 #define MDCR_EDAD_BIT (ULL(1) << 20) 557 #define MDCR_TTRF_BIT (ULL(1) << 19) 558 #define MDCR_STE_BIT (ULL(1) << 18) 559 #define MDCR_SPME_BIT (ULL(1) << 17) 560 #define MDCR_SDD_BIT (ULL(1) << 16) 561 #define MDCR_SPD32(x) ((x) << 14) 562 #define MDCR_SPD32_LEGACY ULL(0x0) 563 #define MDCR_SPD32_DISABLE ULL(0x2) 564 #define MDCR_SPD32_ENABLE ULL(0x3) 565 #define MDCR_NSPB(x) ((x) << 12) 566 #define MDCR_NSPB_EL1 ULL(0x3) 567 #define MDCR_TDOSA_BIT (ULL(1) << 10) 568 #define MDCR_TDA_BIT (ULL(1) << 9) 569 #define MDCR_TPM_BIT (ULL(1) << 6) 570 #define MDCR_EL3_RESET_VAL ULL(0x0) 571 572 /* MDCR_EL2 definitions */ 573 #define MDCR_EL2_MTPME (U(1) << 28) 574 #define MDCR_EL2_HLP (U(1) << 26) 575 #define MDCR_EL2_E2TB(x) ((x) << 24) 576 #define MDCR_EL2_E2TB_EL1 U(0x3) 577 #define MDCR_EL2_HCCD (U(1) << 23) 578 #define MDCR_EL2_TTRF (U(1) << 19) 579 #define MDCR_EL2_HPMD (U(1) << 17) 580 #define MDCR_EL2_TPMS (U(1) << 14) 581 #define MDCR_EL2_E2PB(x) ((x) << 12) 582 #define MDCR_EL2_E2PB_EL1 U(0x3) 583 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 584 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 585 #define MDCR_EL2_TDA_BIT (U(1) << 9) 586 #define MDCR_EL2_TDE_BIT (U(1) << 8) 587 #define MDCR_EL2_HPME_BIT (U(1) << 7) 588 #define MDCR_EL2_TPM_BIT (U(1) << 6) 589 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 590 #define MDCR_EL2_RESET_VAL U(0x0) 591 592 /* HSTR_EL2 definitions */ 593 #define HSTR_EL2_RESET_VAL U(0x0) 594 #define HSTR_EL2_T_MASK U(0xff) 595 596 /* CNTHP_CTL_EL2 definitions */ 597 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 598 #define CNTHP_CTL_RESET_VAL U(0x0) 599 600 /* VTTBR_EL2 definitions */ 601 #define VTTBR_RESET_VAL ULL(0x0) 602 #define VTTBR_VMID_MASK ULL(0xff) 603 #define VTTBR_VMID_SHIFT U(48) 604 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 605 #define VTTBR_BADDR_SHIFT U(0) 606 607 /* HCR definitions */ 608 #define HCR_RESET_VAL ULL(0x0) 609 #define HCR_AMVOFFEN_SHIFT U(51) 610 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 611 #define HCR_TEA_BIT (ULL(1) << 47) 612 #define HCR_API_BIT (ULL(1) << 41) 613 #define HCR_APK_BIT (ULL(1) << 40) 614 #define HCR_E2H_BIT (ULL(1) << 34) 615 #define HCR_HCD_BIT (ULL(1) << 29) 616 #define HCR_TGE_BIT (ULL(1) << 27) 617 #define HCR_RW_SHIFT U(31) 618 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 619 #define HCR_TWE_BIT (ULL(1) << 14) 620 #define HCR_TWI_BIT (ULL(1) << 13) 621 #define HCR_AMO_BIT (ULL(1) << 5) 622 #define HCR_IMO_BIT (ULL(1) << 4) 623 #define HCR_FMO_BIT (ULL(1) << 3) 624 625 /* ISR definitions */ 626 #define ISR_A_SHIFT U(8) 627 #define ISR_I_SHIFT U(7) 628 #define ISR_F_SHIFT U(6) 629 630 /* CNTHCTL_EL2 definitions */ 631 #define CNTHCTL_RESET_VAL U(0x0) 632 #define EVNTEN_BIT (U(1) << 2) 633 #define EL1PCEN_BIT (U(1) << 1) 634 #define EL1PCTEN_BIT (U(1) << 0) 635 636 /* CNTKCTL_EL1 definitions */ 637 #define EL0PTEN_BIT (U(1) << 9) 638 #define EL0VTEN_BIT (U(1) << 8) 639 #define EL0PCTEN_BIT (U(1) << 0) 640 #define EL0VCTEN_BIT (U(1) << 1) 641 #define EVNTEN_BIT (U(1) << 2) 642 #define EVNTDIR_BIT (U(1) << 3) 643 #define EVNTI_SHIFT U(4) 644 #define EVNTI_MASK U(0xf) 645 646 /* CPTR_EL3 definitions */ 647 #define TCPAC_BIT (U(1) << 31) 648 #define TAM_SHIFT U(30) 649 #define TAM_BIT (U(1) << TAM_SHIFT) 650 #define TTA_BIT (U(1) << 20) 651 #define ESM_BIT (U(1) << 12) 652 #define TFP_BIT (U(1) << 10) 653 #define CPTR_EZ_BIT (U(1) << 8) 654 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 655 ~(CPTR_EZ_BIT | ESM_BIT)) 656 657 /* CPTR_EL2 definitions */ 658 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 659 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 660 #define CPTR_EL2_TAM_SHIFT U(30) 661 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 662 #define CPTR_EL2_SMEN_MASK ULL(0x3) 663 #define CPTR_EL2_SMEN_SHIFT U(24) 664 #define CPTR_EL2_TTA_BIT (U(1) << 20) 665 #define CPTR_EL2_TSM_BIT (U(1) << 12) 666 #define CPTR_EL2_TFP_BIT (U(1) << 10) 667 #define CPTR_EL2_TZ_BIT (U(1) << 8) 668 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 669 670 /* VTCR_EL2 definitions */ 671 #define VTCR_RESET_VAL U(0x0) 672 #define VTCR_EL2_MSA (U(1) << 31) 673 674 /* CPSR/SPSR definitions */ 675 #define DAIF_FIQ_BIT (U(1) << 0) 676 #define DAIF_IRQ_BIT (U(1) << 1) 677 #define DAIF_ABT_BIT (U(1) << 2) 678 #define DAIF_DBG_BIT (U(1) << 3) 679 #define SPSR_DAIF_SHIFT U(6) 680 #define SPSR_DAIF_MASK U(0xf) 681 682 #define SPSR_AIF_SHIFT U(6) 683 #define SPSR_AIF_MASK U(0x7) 684 685 #define SPSR_E_SHIFT U(9) 686 #define SPSR_E_MASK U(0x1) 687 #define SPSR_E_LITTLE U(0x0) 688 #define SPSR_E_BIG U(0x1) 689 690 #define SPSR_T_SHIFT U(5) 691 #define SPSR_T_MASK U(0x1) 692 #define SPSR_T_ARM U(0x0) 693 #define SPSR_T_THUMB U(0x1) 694 695 #define SPSR_M_SHIFT U(4) 696 #define SPSR_M_MASK U(0x1) 697 #define SPSR_M_AARCH64 U(0x0) 698 #define SPSR_M_AARCH32 U(0x1) 699 #define SPSR_M_EL2H U(0x9) 700 701 #define SPSR_EL_SHIFT U(2) 702 #define SPSR_EL_WIDTH U(2) 703 704 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 705 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 706 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 707 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 708 709 #define SPSR_PAN_BIT BIT_64(22) 710 711 #define SPSR_DIT_BIT BIT(24) 712 713 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 714 715 #define DISABLE_ALL_EXCEPTIONS \ 716 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 717 718 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 719 720 /* 721 * RMR_EL3 definitions 722 */ 723 #define RMR_EL3_RR_BIT (U(1) << 1) 724 #define RMR_EL3_AA64_BIT (U(1) << 0) 725 726 /* 727 * HI-VECTOR address for AArch32 state 728 */ 729 #define HI_VECTOR_BASE U(0xFFFF0000) 730 731 /* 732 * TCR defintions 733 */ 734 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 735 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 736 #define TCR_EL1_IPS_SHIFT U(32) 737 #define TCR_EL2_PS_SHIFT U(16) 738 #define TCR_EL3_PS_SHIFT U(16) 739 740 #define TCR_TxSZ_MIN ULL(16) 741 #define TCR_TxSZ_MAX ULL(39) 742 #define TCR_TxSZ_MAX_TTST ULL(48) 743 744 #define TCR_T0SZ_SHIFT U(0) 745 #define TCR_T1SZ_SHIFT U(16) 746 747 /* (internal) physical address size bits in EL3/EL1 */ 748 #define TCR_PS_BITS_4GB ULL(0x0) 749 #define TCR_PS_BITS_64GB ULL(0x1) 750 #define TCR_PS_BITS_1TB ULL(0x2) 751 #define TCR_PS_BITS_4TB ULL(0x3) 752 #define TCR_PS_BITS_16TB ULL(0x4) 753 #define TCR_PS_BITS_256TB ULL(0x5) 754 755 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 756 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 757 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 758 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 759 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 760 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 761 762 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 763 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 764 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 765 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 766 767 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 768 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 769 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 770 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 771 772 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 773 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 774 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 775 776 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 777 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 778 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 779 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 780 781 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 782 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 783 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 784 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 785 786 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 787 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 788 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 789 790 #define TCR_TG0_SHIFT U(14) 791 #define TCR_TG0_MASK ULL(3) 792 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 793 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 794 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 795 796 #define TCR_TG1_SHIFT U(30) 797 #define TCR_TG1_MASK ULL(3) 798 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 799 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 800 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 801 802 #define TCR_EPD0_BIT (ULL(1) << 7) 803 #define TCR_EPD1_BIT (ULL(1) << 23) 804 805 #define MODE_SP_SHIFT U(0x0) 806 #define MODE_SP_MASK U(0x1) 807 #define MODE_SP_EL0 U(0x0) 808 #define MODE_SP_ELX U(0x1) 809 810 #define MODE_RW_SHIFT U(0x4) 811 #define MODE_RW_MASK U(0x1) 812 #define MODE_RW_64 U(0x0) 813 #define MODE_RW_32 U(0x1) 814 815 #define MODE_EL_SHIFT U(0x2) 816 #define MODE_EL_MASK U(0x3) 817 #define MODE_EL_WIDTH U(0x2) 818 #define MODE_EL3 U(0x3) 819 #define MODE_EL2 U(0x2) 820 #define MODE_EL1 U(0x1) 821 #define MODE_EL0 U(0x0) 822 823 #define MODE32_SHIFT U(0) 824 #define MODE32_MASK U(0xf) 825 #define MODE32_usr U(0x0) 826 #define MODE32_fiq U(0x1) 827 #define MODE32_irq U(0x2) 828 #define MODE32_svc U(0x3) 829 #define MODE32_mon U(0x6) 830 #define MODE32_abt U(0x7) 831 #define MODE32_hyp U(0xa) 832 #define MODE32_und U(0xb) 833 #define MODE32_sys U(0xf) 834 835 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 836 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 837 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 838 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 839 840 #define SPSR_64(el, sp, daif) \ 841 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 842 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 843 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 844 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 845 (~(SPSR_SSBS_BIT_AARCH64))) 846 847 #define SPSR_MODE32(mode, isa, endian, aif) \ 848 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 849 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 850 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 851 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 852 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 853 (~(SPSR_SSBS_BIT_AARCH32))) 854 855 /* 856 * TTBR Definitions 857 */ 858 #define TTBR_CNP_BIT ULL(0x1) 859 860 /* 861 * CTR_EL0 definitions 862 */ 863 #define CTR_CWG_SHIFT U(24) 864 #define CTR_CWG_MASK U(0xf) 865 #define CTR_ERG_SHIFT U(20) 866 #define CTR_ERG_MASK U(0xf) 867 #define CTR_DMINLINE_SHIFT U(16) 868 #define CTR_DMINLINE_MASK U(0xf) 869 #define CTR_L1IP_SHIFT U(14) 870 #define CTR_L1IP_MASK U(0x3) 871 #define CTR_IMINLINE_SHIFT U(0) 872 #define CTR_IMINLINE_MASK U(0xf) 873 874 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 875 876 /* Physical timer control register bit fields shifts and masks */ 877 #define CNTP_CTL_ENABLE_SHIFT U(0) 878 #define CNTP_CTL_IMASK_SHIFT U(1) 879 #define CNTP_CTL_ISTATUS_SHIFT U(2) 880 881 #define CNTP_CTL_ENABLE_MASK U(1) 882 #define CNTP_CTL_IMASK_MASK U(1) 883 #define CNTP_CTL_ISTATUS_MASK U(1) 884 885 /* Physical timer control macros */ 886 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 887 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 888 889 /* Exception Syndrome register bits and bobs */ 890 #define ESR_EC_SHIFT U(26) 891 #define ESR_EC_MASK U(0x3f) 892 #define ESR_EC_LENGTH U(6) 893 #define ESR_ISS_SHIFT U(0) 894 #define ESR_ISS_LENGTH U(25) 895 #define EC_UNKNOWN U(0x0) 896 #define EC_WFE_WFI U(0x1) 897 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 898 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 899 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 900 #define EC_AARCH32_CP14_LDC_STC U(0x6) 901 #define EC_FP_SIMD U(0x7) 902 #define EC_AARCH32_CP10_MRC U(0x8) 903 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 904 #define EC_ILLEGAL U(0xe) 905 #define EC_AARCH32_SVC U(0x11) 906 #define EC_AARCH32_HVC U(0x12) 907 #define EC_AARCH32_SMC U(0x13) 908 #define EC_AARCH64_SVC U(0x15) 909 #define EC_AARCH64_HVC U(0x16) 910 #define EC_AARCH64_SMC U(0x17) 911 #define EC_AARCH64_SYS U(0x18) 912 #define EC_IABORT_LOWER_EL U(0x20) 913 #define EC_IABORT_CUR_EL U(0x21) 914 #define EC_PC_ALIGN U(0x22) 915 #define EC_DABORT_LOWER_EL U(0x24) 916 #define EC_DABORT_CUR_EL U(0x25) 917 #define EC_SP_ALIGN U(0x26) 918 #define EC_AARCH32_FP U(0x28) 919 #define EC_AARCH64_FP U(0x2c) 920 #define EC_SERROR U(0x2f) 921 #define EC_BRK U(0x3c) 922 923 /* 924 * External Abort bit in Instruction and Data Aborts synchronous exception 925 * syndromes. 926 */ 927 #define ESR_ISS_EABORT_EA_BIT U(9) 928 929 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 930 931 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 932 #define RMR_RESET_REQUEST_SHIFT U(0x1) 933 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 934 935 /******************************************************************************* 936 * Definitions of register offsets, fields and macros for CPU system 937 * instructions. 938 ******************************************************************************/ 939 940 #define TLBI_ADDR_SHIFT U(12) 941 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 942 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 943 944 /******************************************************************************* 945 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 946 * system level implementation of the Generic Timer. 947 ******************************************************************************/ 948 #define CNTCTLBASE_CNTFRQ U(0x0) 949 #define CNTNSAR U(0x4) 950 #define CNTNSAR_NS_SHIFT(x) (x) 951 952 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 953 #define CNTACR_RPCT_SHIFT U(0x0) 954 #define CNTACR_RVCT_SHIFT U(0x1) 955 #define CNTACR_RFRQ_SHIFT U(0x2) 956 #define CNTACR_RVOFF_SHIFT U(0x3) 957 #define CNTACR_RWVT_SHIFT U(0x4) 958 #define CNTACR_RWPT_SHIFT U(0x5) 959 960 /******************************************************************************* 961 * Definitions of register offsets and fields in the CNTBaseN Frame of the 962 * system level implementation of the Generic Timer. 963 ******************************************************************************/ 964 /* Physical Count register. */ 965 #define CNTPCT_LO U(0x0) 966 /* Counter Frequency register. */ 967 #define CNTBASEN_CNTFRQ U(0x10) 968 /* Physical Timer CompareValue register. */ 969 #define CNTP_CVAL_LO U(0x20) 970 /* Physical Timer Control register. */ 971 #define CNTP_CTL U(0x2c) 972 973 /* PMCR_EL0 definitions */ 974 #define PMCR_EL0_RESET_VAL U(0x0) 975 #define PMCR_EL0_N_SHIFT U(11) 976 #define PMCR_EL0_N_MASK U(0x1f) 977 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 978 #define PMCR_EL0_LP_BIT (U(1) << 7) 979 #define PMCR_EL0_LC_BIT (U(1) << 6) 980 #define PMCR_EL0_DP_BIT (U(1) << 5) 981 #define PMCR_EL0_X_BIT (U(1) << 4) 982 #define PMCR_EL0_D_BIT (U(1) << 3) 983 #define PMCR_EL0_C_BIT (U(1) << 2) 984 #define PMCR_EL0_P_BIT (U(1) << 1) 985 #define PMCR_EL0_E_BIT (U(1) << 0) 986 987 /******************************************************************************* 988 * Definitions for system register interface to SVE 989 ******************************************************************************/ 990 #define ZCR_EL3 S3_6_C1_C2_0 991 #define ZCR_EL2 S3_4_C1_C2_0 992 993 /* ZCR_EL3 definitions */ 994 #define ZCR_EL3_LEN_MASK U(0xf) 995 996 /* ZCR_EL2 definitions */ 997 #define ZCR_EL2_LEN_MASK U(0xf) 998 999 /******************************************************************************* 1000 * Definitions for system register interface to SME as needed in EL3 1001 ******************************************************************************/ 1002 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1003 #define SMCR_EL3 S3_6_C1_C2_6 1004 1005 /* ID_AA64SMFR0_EL1 definitions */ 1006 #define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) 1007 1008 /* SMCR_ELx definitions */ 1009 #define SMCR_ELX_LEN_SHIFT U(0) 1010 #define SMCR_ELX_LEN_MASK U(0x1ff) 1011 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1012 1013 /******************************************************************************* 1014 * Definitions of MAIR encodings for device and normal memory 1015 ******************************************************************************/ 1016 /* 1017 * MAIR encodings for device memory attributes. 1018 */ 1019 #define MAIR_DEV_nGnRnE ULL(0x0) 1020 #define MAIR_DEV_nGnRE ULL(0x4) 1021 #define MAIR_DEV_nGRE ULL(0x8) 1022 #define MAIR_DEV_GRE ULL(0xc) 1023 1024 /* 1025 * MAIR encodings for normal memory attributes. 1026 * 1027 * Cache Policy 1028 * WT: Write Through 1029 * WB: Write Back 1030 * NC: Non-Cacheable 1031 * 1032 * Transient Hint 1033 * NTR: Non-Transient 1034 * TR: Transient 1035 * 1036 * Allocation Policy 1037 * RA: Read Allocate 1038 * WA: Write Allocate 1039 * RWA: Read and Write Allocate 1040 * NA: No Allocation 1041 */ 1042 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1043 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1044 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1045 #define MAIR_NORM_NC ULL(0x4) 1046 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1047 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1048 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1049 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1050 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1051 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1052 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1053 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1054 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1055 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1056 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1057 1058 #define MAIR_NORM_OUTER_SHIFT U(4) 1059 1060 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1061 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1062 1063 /* PAR_EL1 fields */ 1064 #define PAR_F_SHIFT U(0) 1065 #define PAR_F_MASK ULL(0x1) 1066 #define PAR_ADDR_SHIFT U(12) 1067 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1068 1069 /******************************************************************************* 1070 * Definitions for system register interface to SPE 1071 ******************************************************************************/ 1072 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1073 1074 /******************************************************************************* 1075 * Definitions for system register interface, shifts and masks for MPAM 1076 ******************************************************************************/ 1077 #define MPAMIDR_EL1 S3_0_C10_C4_4 1078 #define MPAM2_EL2 S3_4_C10_C5_0 1079 #define MPAMHCR_EL2 S3_4_C10_C4_0 1080 #define MPAM3_EL3 S3_6_C10_C5_0 1081 1082 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1083 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1084 /******************************************************************************* 1085 * Definitions for system register interface to AMU for FEAT_AMUv1 1086 ******************************************************************************/ 1087 #define AMCR_EL0 S3_3_C13_C2_0 1088 #define AMCFGR_EL0 S3_3_C13_C2_1 1089 #define AMCGCR_EL0 S3_3_C13_C2_2 1090 #define AMUSERENR_EL0 S3_3_C13_C2_3 1091 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1092 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1093 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1094 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1095 1096 /* Activity Monitor Group 0 Event Counter Registers */ 1097 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1098 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1099 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1100 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1101 1102 /* Activity Monitor Group 0 Event Type Registers */ 1103 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1104 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1105 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1106 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1107 1108 /* Activity Monitor Group 1 Event Counter Registers */ 1109 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1110 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1111 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1112 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1113 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1114 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1115 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1116 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1117 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1118 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1119 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1120 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1121 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1122 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1123 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1124 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1125 1126 /* Activity Monitor Group 1 Event Type Registers */ 1127 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1128 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1129 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1130 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1131 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1132 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1133 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1134 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1135 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1136 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1137 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1138 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1139 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1140 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1141 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1142 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1143 1144 /* AMCNTENSET0_EL0 definitions */ 1145 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1146 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1147 1148 /* AMCNTENSET1_EL0 definitions */ 1149 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1150 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1151 1152 /* AMCNTENCLR0_EL0 definitions */ 1153 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1154 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1155 1156 /* AMCNTENCLR1_EL0 definitions */ 1157 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1158 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1159 1160 /* AMCFGR_EL0 definitions */ 1161 #define AMCFGR_EL0_NCG_SHIFT U(28) 1162 #define AMCFGR_EL0_NCG_MASK U(0xf) 1163 #define AMCFGR_EL0_N_SHIFT U(0) 1164 #define AMCFGR_EL0_N_MASK U(0xff) 1165 1166 /* AMCGCR_EL0 definitions */ 1167 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1168 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1169 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1170 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1171 1172 /* MPAM register definitions */ 1173 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1174 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1175 1176 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1177 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1178 1179 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1180 1181 /******************************************************************************* 1182 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1183 ******************************************************************************/ 1184 1185 /* Definition for register defining which virtual offsets are implemented. */ 1186 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1187 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1188 #define AMCG1IDR_CTR_SHIFT U(0) 1189 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1190 #define AMCG1IDR_VOFF_SHIFT U(16) 1191 1192 /* New bit added to AMCR_EL0 */ 1193 #define AMCR_CG1RZ_SHIFT U(17) 1194 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1195 1196 /* 1197 * Definitions for virtual offset registers for architected activity monitor 1198 * event counters. 1199 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1200 */ 1201 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1202 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1203 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1204 1205 /* 1206 * Definitions for virtual offset registers for auxiliary activity monitor event 1207 * counters. 1208 */ 1209 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1210 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1211 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1212 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1213 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1214 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1215 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1216 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1217 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1218 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1219 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1220 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1221 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1222 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1223 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1224 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1225 1226 /******************************************************************************* 1227 * Realm management extension register definitions 1228 ******************************************************************************/ 1229 #define GPCCR_EL3 S3_6_C2_C1_6 1230 #define GPTBR_EL3 S3_6_C2_C1_4 1231 1232 /******************************************************************************* 1233 * RAS system registers 1234 ******************************************************************************/ 1235 #define DISR_EL1 S3_0_C12_C1_1 1236 #define DISR_A_BIT U(31) 1237 1238 #define ERRIDR_EL1 S3_0_C5_C3_0 1239 #define ERRIDR_MASK U(0xffff) 1240 1241 #define ERRSELR_EL1 S3_0_C5_C3_1 1242 1243 /* System register access to Standard Error Record registers */ 1244 #define ERXFR_EL1 S3_0_C5_C4_0 1245 #define ERXCTLR_EL1 S3_0_C5_C4_1 1246 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1247 #define ERXADDR_EL1 S3_0_C5_C4_3 1248 #define ERXPFGF_EL1 S3_0_C5_C4_4 1249 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1250 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1251 #define ERXMISC0_EL1 S3_0_C5_C5_0 1252 #define ERXMISC1_EL1 S3_0_C5_C5_1 1253 1254 #define ERXCTLR_ED_SHIFT U(0) 1255 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1256 #define ERXCTLR_UE_BIT (U(1) << 4) 1257 1258 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1259 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1260 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1261 1262 /******************************************************************************* 1263 * Armv8.3 Pointer Authentication Registers 1264 ******************************************************************************/ 1265 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1266 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1267 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1268 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1269 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1270 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1271 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1272 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1273 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1274 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1275 1276 /******************************************************************************* 1277 * Armv8.4 Data Independent Timing Registers 1278 ******************************************************************************/ 1279 #define DIT S3_3_C4_C2_5 1280 #define DIT_BIT BIT(24) 1281 1282 /******************************************************************************* 1283 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1284 ******************************************************************************/ 1285 #define SSBS S3_3_C4_C2_6 1286 1287 /******************************************************************************* 1288 * Armv8.5 - Memory Tagging Extension Registers 1289 ******************************************************************************/ 1290 #define TFSRE0_EL1 S3_0_C5_C6_1 1291 #define TFSR_EL1 S3_0_C5_C6_0 1292 #define RGSR_EL1 S3_0_C1_C0_5 1293 #define GCR_EL1 S3_0_C1_C0_6 1294 1295 /******************************************************************************* 1296 * Armv8.5 - Random Number Generator Registers 1297 ******************************************************************************/ 1298 #define RNDR S3_3_C2_C4_0 1299 #define RNDRRS S3_3_C2_C4_1 1300 1301 /******************************************************************************* 1302 * FEAT_HCX - Extended Hypervisor Configuration Register 1303 ******************************************************************************/ 1304 #define HCRX_EL2 S3_4_C1_C2_2 1305 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1306 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1307 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1308 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1309 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1310 1311 /******************************************************************************* 1312 * FEAT_TCR2 - Extended Translation Control Register 1313 ******************************************************************************/ 1314 #define TCR2_EL2 S3_4_C2_C0_3 1315 1316 /******************************************************************************* 1317 * Definitions for DynamicIQ Shared Unit registers 1318 ******************************************************************************/ 1319 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1320 1321 /* CLUSTERPWRDN_EL1 register definitions */ 1322 #define DSU_CLUSTER_PWR_OFF 0 1323 #define DSU_CLUSTER_PWR_ON 1 1324 #define DSU_CLUSTER_PWR_MASK U(1) 1325 1326 /******************************************************************************* 1327 * Definitions for CPU Power/Performance Management registers 1328 ******************************************************************************/ 1329 1330 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1331 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1332 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1333 1334 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1335 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1336 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1337 1338 #endif /* ARCH_H */ 1339