feat(firme): initial commit of FIRME service

This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.

This adds a new generic

feat(firme): initial commit of FIRME service

This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.

This adds a new generic granule transition function that replaces
the existing delegate/undelegate APIs that GPI_SET uses. It also
updates TRP to use GPI_SET when FIRME is supported.

FIRME spec is here, note that it is ALPHA2 quality so further changes
are to be expected:
https://developer.arm.com/documentation/den0149

Change-Id: I57b8ad7e87a0679e15c8247f8457f91f3254dedb
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(cros): add GSC, DRM, and Stable HUK SMC handlers

Add new SMC handlers to set the GSC counter key, DRM device key, and
Stable Hardware Unique Key for ChromeOS Widevine. These keys are then
passe

feat(cros): add GSC, DRM, and Stable HUK SMC handlers

Add new SMC handlers to set the GSC counter key, DRM device key, and
Stable Hardware Unique Key for ChromeOS Widevine. These keys are then
passed to the OP-TEE device tree node.

Change-Id: Id31f8101d9783e709c9984089674220d93596531
Signed-off-by: Yidi Lin <yidilin@google.com>

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feat(rmmd): expand RMM SMC return registers

This change expands the number of return registers
that RMM can use when returning from SMC calls,
increasing from 5 registers (x0-x4) to 8 registers (x0-

feat(rmmd): expand RMM SMC return registers

This change expands the number of return registers
that RMM can use when returning from SMC calls,
increasing from 5 registers (x0-x4) to 8 registers (x0-x7).
The RMM-EL3 Interface version is bumped to 2.0 as this
is an incompatible change.

This maintains SMCCC v1.2 compliance where x4-x7 are
preserved unless used as return values.
The responsibility for preserving these registers
when not used lies with RMM.

Changed TRP to handle additional return values x0-x7.

Change-Id: Ifd88a3bd68f53beb230e830f0d6e4365cedfd728
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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fix(cm): don't context switch GICv3 registers on NS<->RL transitions

The GICv3 is architectured to solely manage interrupts targeted to
Normal and Secure world. It doesn't manage interrupts targetin

fix(cm): don't context switch GICv3 registers on NS<->RL transitions

The GICv3 is architectured to solely manage interrupts targeted to
Normal and Secure world. It doesn't manage interrupts targeting the
more recently introduced Realm world. Hence the new RMMv2.0
specification mandates that EL3 should not save and restore
the GIC registers on a world switch. This change is not backward
compatible with RMMv1.x ABI.

Note the change in implementation of cm_el2_sysregs_context_save()
and cm_el2_sysregs_context_restore() API as GIC state is not
managed by these APIs anymore.

Add new build flag RMM_V1_COMPAT to support backward compatibility
with RMMv1.x. This flag is currently enabled by default.

This patch is a reworked version of the original patch at:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45658

NOTE: If RMM_V1_COMPAT is not enabled, then RMM_EL3_IFC_VERSION
is bumped to 1.0 which makes it incompatible with an RMM supporting
0.x.

Change-Id: If4c53b85ef31091c254b383ed7b32c39124f0dbb
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the

feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the FF-A v1.3 ALP2 specification.

The callback relies on helper utilities that enable the LSP to send
live activation framework messages to SPMC after performing several
sanity checks.

Change-Id: I2730433ec57c0c1163281eff9de729c6e93f3366
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
pla

feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
placeholders.

Subsequent patches will implement the required functionality.

BREAKING CHANGE: Temporarily fails to build

Change-Id: Id733eaa0e7a300386b720fcce99ea265fd382ab6
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live acti

feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live activation of a physical SP.

BREAKING CHANGE: Temporarily fails to build

Change-Id: I1b7dcf91e08fc7d85b47f2b39330d1351f8294dd
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spmd): support for extended partition info descriptor

This patch adds the support for extended partition info descriptor
added in FF-A v1.3 ALP2 specification. It enables the LSP, managed by
SP

feat(spmd): support for extended partition info descriptor

This patch adds the support for extended partition info descriptor
added in FF-A v1.3 ALP2 specification. It enables the LSP, managed by
SPMD, to query the properties of a physical SP.

This is necessary to implement support for live activation of an SP
uniquely identified by its Image UUID.

BREAKING CHANGE: Temporarily fails to build but recovers in subsequent
patches.

Change-Id: Ibb2dab3124ab1838fb954f3d47e11b52e82ca7ca
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "fix(services): add suffix 'U' to unsigned integers" into integration

fix(services): add suffix 'U' to unsigned integers

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type

fix(services): add suffix 'U' to unsigned integers

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Suffix "U" is added to unsigned integers to fix this violation.

Change-Id: Ida954957cd45b332a7643edde6804ac81447da02
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS wo

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.

Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for

feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.

Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a0

feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(spmd): support FFA DIRECT_REQ2 for logical SP

The FFA_MSG_SEND_DIRECT_REQ2 support is added in SPMD logical
SP. This is required by certain secure partitions that needs
this type of direct requ

feat(spmd): support FFA DIRECT_REQ2 for logical SP

The FFA_MSG_SEND_DIRECT_REQ2 support is added in SPMD logical
SP. This is required by certain secure partitions that needs
this type of direct request instead of older FFA_MSG_SEND_DIRECT_REQ.

The common logic is implemented in a helper function, the handlers
for FFA_MSG_SEND_DIRECT_REQ and FFA_MSG_SEND_DIRECT_REQ2 are just
wrappers with appropriate arguments.

Change-Id: Ia82923bcd4f6a6dbedd591b771b17b998b76d0c3
Signed-off-by: Bo Yan <byan@nvidia.com>

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Merge "feat(spm-mm): fix wrong range of SPM_MM" into integration

feat(rmmd): extend RMI function ID range validation

Add support for the extended RMI function number range (RMI_FNUM1)in
the is_rmi_fid() macro. The macro now validates FIDs in both:
- Original rang

feat(rmmd): extend RMI function ID range validation

Add support for the extended RMI function number range (RMI_FNUM1)in
the is_rmi_fid() macro. The macro now validates FIDs in both:
- Original range: 0x150 - 0x18F (RMI_FNUM_MIN_VALUE to RMI_FNUM_MAX_VALUE)
- Extended range: 0x1D0 - 0x2CF (RMI_FNUM1_MIN_VALUE to RMI_FNUM1_MAX_VALUE)

This change ensures proper identification and handling of RMI calls
across the full function ID space as defined by the RMM specification.

Change-Id: Ie65999ffeacc94057389e056761e57586f804b63
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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fix(smccc): ignore SCR_EEL2_BIT

Commit cbba59c41a99 ("enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM")
enables ARCH_FEATURE_AVAILABILITY by default when RME is enabled which
results into below asser

fix(smccc): ignore SCR_EEL2_BIT

Commit cbba59c41a99 ("enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM")
enables ARCH_FEATURE_AVAILABILITY by default when RME is enabled which
results into below assertion when RMM queries the features.

ERROR: Unexpected bits 0x40000 were set in register 1e1100!
ASSERT: services/arm_arch_svc/arm_arch_svc_setup.c:251

This happpens because SCR_EEL2_BIT is neither part of SCR_EL3_FEATS nor
part of SCR_EL3_IGNORED, as the SMCCC spec doesn't list SCR_EEL2_BIT as
reported, add it to SCR_EL3_IGNORED.

Change-Id: I0465744dc7f0ae589d6a8345c1cca63ac6f7f357
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

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feat(spm-mm): fix wrong range of SPM_MM

According to SMCCC specification [1],
Table 6-4: Reserved Standard Secure Service Call range,

fid 0x40-0x4f are reserved for Management Mode,
fid 0x50-0x5f a

feat(spm-mm): fix wrong range of SPM_MM

According to SMCCC specification [1],
Table 6-4: Reserved Standard Secure Service Call range,

fid 0x40-0x4f are reserved for Management Mode,
fid 0x50-0x5f are reserved for TRNG interface and
fid 0x60-0x7f are not reserved yet for Standard Secure Service Calls
and current SPM_MM's implementation uses the 0x40-0x4f and 0x60-0x7f fids.

However, the is_spm_mm_fid() is checking TRNG range too
so it returns false positive and
TRNG request couldn't be handled properly.

To resolve this, remove the TRNG range check in is_spm_mm_fid().

Link: https://developer.arm.com/documentation/den0028/latest/ [1]
Change-Id: Ide41cf3451412676f604e31f3d88aeb2e601c5f2
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from diffe

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime the
same component.

This patch checks if the plat_lfa_load_auth_image return -EAGAIN
indicating that the platform expects the LFA_PRIME call to be
issued again. This is done by returning LFA_SUCCESS and setting
flags[0] to 1, indicating that LFA_PRIME is incomplete and must
be called again.

Change-Id: Ia3046b5467c50c4c51392bac3fb9e9533f2438db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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fix(cpufeat): use of additional breakpoints

Extended Breakpoints access through mdcr_el3.ebwe is available
only when there are greater than 16 breakpoints implemented.
Otherwise the EBWE Bit is RES0

fix(cpufeat): use of additional breakpoints

Extended Breakpoints access through mdcr_el3.ebwe is available
only when there are greater than 16 breakpoints implemented.
Otherwise the EBWE Bit is RES0 and we could skip enabling Extended
Breakpoint access.

Ref: https://developer.arm.com/documentation/111107/2025-09/AArch64-Registers/MDCR-EL3--Monitor-Debug-Configuration-Register--EL3-?lang=en

Change-Id: I2b2147e83d65ee9b0492d3cf3adafd5c8cbe17f5
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa)

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa): rename component_id to lfa_component_id

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chore(lfa): rename component_id to lfa_component_id

Refactor the function lfa_is_prime_complete to use a more specific
parameter name, lfa_component_id, enhancing code clarity. This change
improves

chore(lfa): rename component_id to lfa_component_id

Refactor the function lfa_is_prime_complete to use a more specific
parameter name, lfa_component_id, enhancing code clarity. This change
improves readability and reduces potential confusion with other
component identifiers in the codebase.

Change-Id: I00285fce4b7149bd97d6386ef471e9d1598a3fed
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(smccc): fixed define when ENABLE_FEAT_FPMR is disabled

Define SCR_FEAT_FPMR as 0 when ENABLE_FEAT_FPMR is disabled to avoid
conditional build inconsistencies.

Signed-off-by: Arvind Ram Prakash

fix(smccc): fixed define when ENABLE_FEAT_FPMR is disabled

Define SCR_FEAT_FPMR as 0 when ENABLE_FEAT_FPMR is disabled to avoid
conditional build inconsistencies.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ibe71fa20fa4ffa98d8fff41517ccbf29755a58c3

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