1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 117 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 118 emitted (HINT space or not). Selects the branch protection features to use: 119- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 120- 1: Enables all types of branch protection features 121- 2: Return address signing to its standard level 122- 3: Extend the signing to include leaf functions 123- 4: Turn on branch target identification mechanism 124- 5: Enables all types of branch protection features, only if present in 125 hardware (FEAT_STATE_CHECK). 126 127 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 128 and resulting PAuth/BTI features. 129 130 +-------+--------------+-------+-----+ 131 | Value | GCC option | PAuth | BTI | 132 +=======+==============+=======+=====+ 133 | 0 | none | N | N | 134 +-------+--------------+-------+-----+ 135 | 1 | standard | Y | Y | 136 +-------+--------------+-------+-----+ 137 | 2 | pac-ret | Y | N | 138 +-------+--------------+-------+-----+ 139 | 3 | pac-ret+leaf | Y | N | 140 +-------+--------------+-------+-----+ 141 | 4 | bti | N | Y | 142 +-------+--------------+-------+-----+ 143 | 5 | dynamic | Y | Y | 144 +-------+--------------+-------+-----+ 145 146 This option defaults to 0. 147 Note that Pointer Authentication is enabled for Non-secure world 148 irrespective of the value of this option if the CPU supports it. 149 150- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 151 compilation of each build. It must be set to a C string (including quotes 152 where applicable). Defaults to a string that contains the time and date of 153 the compilation. 154 155- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 156 build to be uniquely identified. Defaults to the current git commit id. 157 158- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 159 160- ``CFLAGS``: Extra user options appended on the compiler's command line in 161 addition to the options set by the build system. 162 163- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 164 release several CPUs out of reset. It can take either 0 (several CPUs may be 165 brought up) or 1 (only one CPU will ever be brought up during cold reset). 166 Default is 0. If the platform always brings up a single CPU, there is no 167 need to distinguish between primary and secondary CPUs and the boot path can 168 be optimised. The ``plat_is_my_cpu_primary()`` and 169 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 170 to be implemented in this case. 171 172- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 173 Defaults to ``tbbr``. 174 175- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 176 register state when an unexpected exception occurs during execution of 177 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 178 this is only enabled for a debug build of the firmware. 179 180- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 181 certificate generation tool to create new keys in case no valid keys are 182 present or specified. Allowed options are '0' or '1'. Default is '1'. 183 184- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 185 the AArch32 system registers to be included when saving and restoring the 186 CPU context. The option must be set to 0 for AArch64-only platforms (that 187 is on hardware that does not implement AArch32, or at least not at EL1 and 188 higher ELs). Default value is 1. 189 190- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 191 registers to be included when saving and restoring the CPU context. Default 192 is 0. 193 194- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 195 Memory System Resource Partitioning and Monitoring (MPAM) 196 registers to be included when saving and restoring the CPU context. 197 Default is '0'. 198 199- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 200 registers to be saved/restored when entering/exiting an EL2 execution 201 context. This flag can take values 0 to 2, to align with the 202 ``ENABLE_FEAT`` mechanism. Default value is 0. 203 204- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 205 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 206 to be included when saving and restoring the CPU context as part of world 207 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 208 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 209 is 0. 210 211 Note that Pointer Authentication is enabled for Non-secure world irrespective 212 of the value of this flag if the CPU supports it. Alternatively, when 213 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 214 215- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 216 SVE registers to be included when saving and restoring the CPU context. Note 217 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 218 general, it is recommended to perform SVE context management in lower ELs 219 and skip in EL3 due to the additional cost of maintaining large data 220 structures to track the SVE state. Hence, the default value is 0. 221 222- ``DEBUG``: Chooses between a debug and release build. It can take either 0 223 (release) or 1 (debug) as values. 0 is the default. 224 225- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 226 authenticated decryption algorithm to be used to decrypt firmware/s during 227 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 228 this flag is ``none`` to disable firmware decryption which is an optional 229 feature as per TBBR. 230 231- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 232 of the binary image. If set to 1, then only the ELF image is built. 233 0 is the default. 234 235- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 236 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 237 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 238 mechanism. Default is ``0``. 239 240- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 241 Board Boot authentication at runtime. This option is meant to be enabled only 242 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 243 flag has to be enabled. 0 is the default. 244 245- ``E``: Boolean option to make warnings into errors. Default is 1. 246 247 When specifying higher warnings levels (``W=1`` and higher), this option 248 defaults to 0. This is done to encourage contributors to use them, as they 249 are expected to produce warnings that would otherwise fail the build. New 250 contributions are still expected to build with ``W=0`` and ``E=1`` (the 251 default). 252 253- ``EARLY_CONSOLE``: This option is used to enable early traces before default 254 console is properly setup. It introduces EARLY_* traces macros, that will 255 use the non-EARLY traces macros if the flag is enabled, or do nothing 256 otherwise. To use this feature, platforms will have to create the function 257 plat_setup_early_console(). 258 Default is 0 (disabled) 259 260- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 261 the normal boot flow. It must specify the entry point address of the EL3 262 payload. Please refer to the "Booting an EL3 payload" section for more 263 details. 264 265- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 266 (also known as group 1 counters). These are implementation-defined counters, 267 and as such require additional platform configuration. Default is 0. 268 269- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 270 are compiled out. For debug builds, this option defaults to 1, and calls to 271 ``assert()`` are left in place. For release builds, this option defaults to 0 272 and calls to ``assert()`` function are compiled out. This option can be set 273 independently of ``DEBUG``. It can also be used to hide any auxiliary code 274 that is only required for the assertion and does not fit in the assertion 275 itself. 276 277- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 278 dumps or not. It is supported in both AArch64 and AArch32. However, in 279 AArch32 the format of the frame records are not defined in the AAPCS and they 280 are defined by the implementation. This implementation of backtrace only 281 supports the format used by GCC when T32 interworking is disabled. For this 282 reason enabling this option in AArch32 will force the compiler to only 283 generate A32 code. This option is enabled by default only in AArch64 debug 284 builds, but this behaviour can be overridden in each platform's Makefile or 285 in the build command line. 286 287- ``ENABLE_FEAT`` 288 The Arm architecture defines several architecture extension features, 289 named FEAT_xxx in the architecure manual. Some of those features require 290 setup code in higher exception levels, other features might be used by TF-A 291 code itself. 292 Most of the feature flags defined in the TF-A build system permit to take 293 the values 0, 1 or 2, with the following meaning: 294 295 :: 296 297 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 298 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 299 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 300 301 When setting the flag to 0, the feature is disabled during compilation, 302 and the compiler's optimisation stage and the linker will try to remove 303 as much of this code as possible. 304 If it is defined to 1, the code will use the feature unconditionally, so the 305 CPU is expected to support that feature. The FEATURE_DETECTION debug 306 feature, if enabled, will verify this. 307 If the feature flag is set to 2, support for the feature will be compiled 308 in, but its existence will be checked at runtime, so it works on CPUs with 309 or without the feature. This is mostly useful for platforms which either 310 support multiple different CPUs, or where the CPU is configured at runtime, 311 like in emulators. 312 313- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 314 extensions. This flag can take the values 0 to 2, to align with the 315 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 316 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 317 and this option can be used to enable this feature on those systems as well. 318 This flag can take the values 0 to 2, the default is 0. 319 320- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 321 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 322 onwards. This flag can take the values 0 to 2, to align with the 323 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 324 325- ``ENABLE_FEAT_CLRBHB``: Numeric value to enable the CLRBHB instruction. 326 Clear Branch History clears the branch history for the current context to 327 the extent that branch history information created before the CLRBHB instruction 328 cannot be used by code. This is an optional architectural feature available on v8.0 329 onwards and is a mandatory feature from v8.9 onwards. 330 This flag can take the values of 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 331 Default value is ``0``. 332 333- ``ENABLE_FEAT_CPA2``: Numeric value to enable the ``FEAT_CPA2`` extension. 334 It enables checked pointer arithmetic in EL3, which will result in address 335 faults in the event that a pointer arithmetic overflow error occurs. This is 336 an optional feature starting from Arm v9.4 and This flag can take values 0 to 337 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 338 339- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 340 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 341 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 342 optional feature available on Arm v8.0 onwards. This flag can take values 343 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 344 Default value is ``0``. 345 346- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 347 extension. This feature is supported in AArch64 state only and is an optional 348 feature available in Arm v8.0 implementations. 349 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 350 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 351 mechanism. Default value is ``0``. 352 353- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 354 extension which allows the ability to implement more than 16 breakpoints 355 and/or watchpoints. This feature is mandatory from v8.9 and is optional 356 from v8.8. This flag can take the values of 0 to 2, to align with the 357 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 358 359- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 360 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 361 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 362 and upwards. This flag can take the values 0 to 2, to align with the 363 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 364 365- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 366 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 367 Physical Offset register) during EL2 to EL3 context save/restore operations. 368 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 369 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 370 mechanism. Default value is ``0``. 371 372- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 373 Mode Register feature, allowing access to the FPMR register. FPMR register 374 controls the behaviors of FP8 instructions. It is an optional architectural 375 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 376 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 377 378- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 379 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 380 Read Trap Register) during EL2 to EL3 context save/restore operations. 381 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 382 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 386 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 387 during EL2 to EL3 context save/restore operations. 388 Its an optional architectural feature and is available from v8.8 and upwards. 389 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 390 mechanism. Default value is ``0``. 391 392- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for 393 Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to 394 restrict overwriting certain EL3 registers after boot. 395 This lockdown is established by setting individual trap bits for 396 system registers that are not expected to be overwritten after boot. 397 This feature is an optional architectural feature and is available from 398 Armv9.4 onwards. This flag can take values from 0 to 2, aligning with 399 the ``ENABLE_FEAT`` mechanism. The default value is 0. 400 401 .. note:: 402 This feature currently traps access to all EL3 registers in 403 ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``, 404 ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and 405 ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``). 406 If additional traps need to be disabled for specific platforms, 407 please contact the Arm team on `TF-A public mailing list`_. 408 409- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 410 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 411 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 412 mandatory architectural feature and is enabled from v8.7 and upwards. This 413 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 414 mechanism. Default value is ``0``. 415 416- ``ENABLE_FEAT_IDTE3``: Numeric value to set SCR_EL3.TID3/TID5 bits which 417 enables trapping of ID register reads by lower ELs to EL3. This allows EL3 418 to control the feature visibility to lower ELs by returning a sanitized value 419 based on current feature enablement status. Hypervisors are expected to 420 cache ID register during their boot stage. This flag can take the 421 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 422 Default value is ``0``. This feature is EXPERIMENTAL. 423 424 .. note:: 425 This feature traps all lower EL accesses to Group 3 and Group 5 426 ID registers to EL3. This can incur a performance impact and platforms 427 should enable them only if they have a specific need. 428 429- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 430 of memory operations) when INIT_UNUSED_NS_EL2=1. 431 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 432 require any settings from EL3 as the controls are present in EL2 registers 433 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 434 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 435 EL3 should configure the EL2 registers. This flag 436 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 437 Default value is ``0``. 438 439- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 440 if the platform wants to use this feature and MTE2 is enabled at ELX. 441 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 442 mechanism. Default value is ``0``. 443 444- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 445 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 446 permission fault for any privileged data access from EL1/EL2 to virtual 447 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 448 mandatory architectural feature and is enabled from v8.1 and upwards. This 449 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 450 mechanism. Default value is ``0``. 451 452- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 453 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 454 onwards. This feature requires PAUTH to be enabled via the 455 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 456 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 457 458- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 459 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 460 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 461 mechanism. Default value is ``0``. 462 463- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 464 extension. This feature is only supported in AArch64 state. This flag can 465 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 466 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 467 Armv8.5 onwards. 468 469- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 470 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 471 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 472 later CPUs. It is enabled from v8.5 and upwards and if needed can be 473 overidden from platforms explicitly. 474 475- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 476 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 477 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 478 mechanism. Default is ``0``. 479 480- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 481 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 482 available on Arm v8.6. This flag can take values 0 to 2, to align with the 483 ``ENABLE_FEAT`` mechanism. Default is ``0``. 484 485 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 486 delayed by the amount of value in ``TWED_DELAY``. 487 488- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 489 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 490 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 491 architectural feature and is enabled from v8.1 and upwards. It can take 492 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 493 Default value is ``0``. 494 495- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 496 allow access to TCR2_EL2 (extended translation control) from EL2 as 497 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 498 mandatory architectural feature and is enabled from v8.9 and upwards. This 499 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 500 mechanism. Default value is ``0``. 501 502- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 503 at EL2 and below, and context switch relevant registers. This flag 504 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 505 mechanism. Default value is ``0``. 506 507- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 508 at EL2 and below, and context switch relevant registers. This flag 509 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 510 mechanism. Default value is ``0``. 511 512- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 513 at EL2 and below, and context switch relevant registers. This flag 514 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 515 mechanism. Default value is ``0``. 516 517- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 518 at EL2 and below, and context switch relevant registers. This flag 519 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 520 mechanism. Default value is ``0``. 521 522- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 523 allow use of Guarded Control Stack from EL2 as well as adding the GCS 524 registers to the EL2 context save/restore operations. This flag can take 525 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 526 Default value is ``0``. 527 528 - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU 529 interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually 530 exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported. 531 Default value is ``0``. 532 533- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 534 (Translation Hardening Extension) at EL2 and below, setting the bit 535 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 536 registers and context switch them. 537 Its an optional architectural feature and is available from v8.8 and upwards. 538 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 539 mechanism. Default value is ``0``. 540 541- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 542 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 543 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 544 context switch them. This feature is OPTIONAL from Armv8.0 implementations 545 and mandatory in Armv8.9 implementations. 546 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 547 mechanism. Default value is ``0``. 548 549- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 550 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 551 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 552 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 553 RCWSMASK_EL1. Its an optional architectural feature and is available from 554 9.3 and upwards. 555 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 556 mechanism. Default value is ``0``. 557 558- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 559 support. This option is currently only supported for AArch64. On GCC it only 560 applies to TF-A proper, and not its libraries. If LTO on libraries (except 561 the libc) is desired a platform can pass `-flto -ffat-lto-objects` as long as 562 GCC >= 14 is in use. Default is 0. 563 564- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 565 feature. MPAM is an optional Armv8.4 extension that enables various memory 566 system components and resources to define partitions; software running at 567 various ELs can assign themselves to desired partition to control their 568 performance aspects. 569 570 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 571 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 572 access their own MPAM registers without trapping into EL3. This option 573 doesn't make use of partitioning in EL3, however. Platform initialisation 574 code should configure and use partitions in EL3 as required. This option 575 defaults to ``2`` since MPAM is enabled by default for NS world only. 576 The flag is automatically disabled when the target 577 architecture is AArch32. 578 579- ``ENABLE_FEAT_MPAM_PE_BW_CTRL``: This option enables Armv9.3 MPAM 580 PE-side bandwidth controls and disables traps to EL3/EL2 (when 581 ``INIT_UNUSED_NS_EL2`` = 1). The flag accepts values from 0 to 2, in 582 line with the ``ENABLE_FEAT`` mechanism, and defaults to ``0``. 583 584- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 585 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 586 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 587 Default value is ``0``. 588 589- ``ENABLE_FEAT_AIE``: Numeric value to enable access to the (A)MAIR2 system 590 registers from non-secure world. This flag can take the values 0 to 2, to 591 align with the ``ENABLE_FEAT`` mechanism. 592 Default value is ``0``. 593 594- ``ENABLE_FEAT_PFAR``: Numeric value to enable access to the PFAR system 595 registers from non-secure world. This flag can take the values 0 to 2, to 596 align with the ``ENABLE_FEAT`` mechanism. 597 Default value is ``0``. 598 599- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 600 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 601 firmware to detect and limit high activity events to assist in SoC processor 602 power domain dynamic power budgeting and limit the triggering of whole-rail 603 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 604 605- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 606 support within generic code in TF-A. This option is currently only supported 607 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 608 in BL32 (SP_min) for AARCH32. Default is 0. 609 610- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 611 Measurement Framework(PMF). Default is 0. 612 613- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 614 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 615 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 616 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 617 software. 618 619- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 620 instrumentation which injects timestamp collection points into TF-A to 621 allow runtime performance to be measured. Currently, only PSCI is 622 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 623 as well. Default is 0. 624 625- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 626 extensions. This is an optional architectural feature for AArch64. 627 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 628 mechanism. The default is 2 but is automatically disabled when the target 629 architecture is AArch32. 630 631- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 632 (SVE) for the Non-secure world only. SVE is an optional architectural feature 633 for AArch64. This flag can take the values 0 to 2, to align with the 634 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 635 systems that have SPM_MM enabled. The default value is 2. 636 637 Note that when SVE is enabled for the Non-secure world, access 638 to SVE, SIMD and floating-point functionality from the Secure world is 639 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 640 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 641 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 642 world data in the Z-registers which are aliased by the SIMD and FP registers. 643 644- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 645 for the Secure world. SVE is an optional architectural feature for AArch64. 646 The default is 0 and it is automatically disabled when the target architecture 647 is AArch32. 648 649 .. note:: 650 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 651 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 652 ``CTX_INCLUDE_SVE_REGS`` is also needed. 653 654- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 655 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 656 default value is set to "none". "strong" is the recommended stack protection 657 level if this feature is desired. "none" disables the stack protection. For 658 all values other than "none", the ``plat_get_stack_protector_canary()`` 659 platform hook needs to be implemented. The value is passed as the last 660 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 661 662- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 663 option to enable the workarounds for all errata that TF-A implements. Normally 664 they should be explicitly enabled depending on each platform's needs. Not 665 recommended for release builds. This option is default set to 0. 666 667- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 668 flag depends on ``DECRYPTION_SUPPORT`` build flag. 669 670- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 671 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 672 673- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 674 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 675 on ``DECRYPTION_SUPPORT`` build flag. 676 677- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 678 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 679 build flag. 680 681- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 682 deprecated platform APIs, helper functions or drivers within Trusted 683 Firmware as error. It can take the value 1 (flag the use of deprecated 684 APIs as error) or 0. The default is 0. 685 686- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 687 configure an Arm® Ethos™-N NPU. To use this service the target platform's 688 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 689 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 690 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 691 692- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 693 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 694 ``TRUSTED_BOARD_BOOT`` to be enabled. 695 696- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 697 (```ethosn.bin```). This firmware image will be included in the FIP and 698 loaded at runtime. 699 700- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 701 targeted at EL3. When set ``0`` (default), no exceptions are expected or 702 handled at EL3, and a panic will result. The exception to this rule is when 703 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 704 occuring during normal world execution, are trapped to EL3. Any exception 705 trapped during secure world execution are trapped to the SPMC. This is 706 supported only for AArch64 builds. 707 708- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 709 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 710 Default value is 40 (LOG_LEVEL_INFO). 711 712- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 713 injection from lower ELs, and this build option enables lower ELs to use 714 Error Records accessed via System Registers to inject faults. This is 715 applicable only to AArch64 builds. 716 717 This feature is intended for testing purposes only, and is advisable to keep 718 disabled for production images. 719 720- ``FIP_NAME``: This is an optional build option which specifies the FIP 721 filename for the ``fip`` target. Default is ``fip.bin``. 722 723- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 724 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 725 726- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 727 728 :: 729 730 0: Encryption is done with Secret Symmetric Key (SSK) which is common 731 for a class of devices. 732 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 733 unique per device. 734 735 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 736 737- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 738 tool to create certificates as per the Chain of Trust described in 739 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 740 include the certificates in the FIP and FWU_FIP. Default value is '0'. 741 742 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 743 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 744 the corresponding certificates, and to include those certificates in the 745 FIP and FWU_FIP. 746 747 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 748 images will not include support for Trusted Board Boot. The FIP will still 749 include the corresponding certificates. This FIP can be used to verify the 750 Chain of Trust on the host machine through other mechanisms. 751 752 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 753 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 754 will not include the corresponding certificates, causing a boot failure. 755 756- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 757 inherent support for specific EL3 type interrupts. Setting this build option 758 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 759 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 760 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 761 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 762 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 763 the Secure Payload interrupts needs to be synchronously handed over to Secure 764 EL1 for handling. The default value of this option is ``0``, which means the 765 Group 0 interrupts are assumed to be handled by Secure EL1. 766 767- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 768 Interrupts, resulting from errors in NS world, will be always trapped in 769 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 770 will be trapped in the current exception level (or in EL1 if the current 771 exception level is EL0). 772 773- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 774 software operations are required for CPUs to enter and exit coherency. 775 However, newer systems exist where CPUs' entry to and exit from coherency 776 is managed in hardware. Such systems require software to only initiate these 777 operations, and the rest is managed in hardware, minimizing active software 778 management. In such systems, this boolean option enables TF-A to carry out 779 build and run-time optimizations during boot and power management operations. 780 This option defaults to 0 and if it is enabled, then it implies 781 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 782 783 If this flag is disabled while the platform which TF-A is compiled for 784 includes cores that manage coherency in hardware, then a compilation error is 785 generated. This is based on the fact that a system cannot have, at the same 786 time, cores that manage coherency in hardware and cores that don't. In other 787 words, a platform cannot have, at the same time, cores that require 788 ``HW_ASSISTED_COHERENCY=1`` and cores that require 789 ``HW_ASSISTED_COHERENCY=0``. 790 791 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 792 translation library (xlat tables v2) must be used; version 1 of translation 793 library is not supported. 794 795- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 796 implementation defined system register accesses from lower ELs. Default 797 value is ``0``. 798 799- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 800 bottom, higher addresses at the top. This build flag can be set to '1' to 801 invert this behavior. Lower addresses will be printed at the top and higher 802 addresses at the bottom. 803 804- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 805 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 806 by default. Platforms without NS-EL2 in use must enable this flag. 807 808- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 809 used for generating the PKCS keys and subsequent signing of the certificate. 810 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 811 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 812 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 813 compatibility. The default value of this flag is ``rsa`` which is the TBBR 814 compliant PKCS#1 RSA 2.1 scheme. 815 816- ``KEY_SIZE``: This build flag enables the user to select the key size for 817 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 818 depend on the chosen algorithm and the cryptographic module. 819 820 +---------------------------+------------------------------------+ 821 | KEY_ALG | Possible key sizes | 822 +===========================+====================================+ 823 | rsa | 1024 , 2048 (default), 3072, 4096 | 824 +---------------------------+------------------------------------+ 825 | ecdsa | 256 (default), 384 | 826 +---------------------------+------------------------------------+ 827 | ecdsa-brainpool-regular | 256 (default) | 828 +---------------------------+------------------------------------+ 829 | ecdsa-brainpool-twisted | 256 (default) | 830 +---------------------------+------------------------------------+ 831 832- ``HASH_ALG``: This build flag enables the user to select the secure hash 833 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 834 The default value of this flag is ``sha256``. 835 836- ``HW_CONFIG_BASE``: This option specifies the location in memory where the DTB 837 should either be loaded by BL2 or can be found by later stages. 838 839- ``LDFLAGS``: Extra user options appended to the linkers' command line in 840 addition to the one set by the build system. 841 842- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 843 output compiled into the build. This should be one of the following: 844 845 :: 846 847 0 (LOG_LEVEL_NONE) 848 10 (LOG_LEVEL_ERROR) 849 20 (LOG_LEVEL_NOTICE) 850 30 (LOG_LEVEL_WARNING) 851 40 (LOG_LEVEL_INFO) 852 50 (LOG_LEVEL_VERBOSE) 853 854 All log output up to and including the selected log level is compiled into 855 the build. The default value is 40 in debug builds and 20 in release builds. 856 857- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 858 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 859 provide trust that the code taking the measurements and recording them has 860 not been tampered with. 861 862 This option defaults to 0. 863 864- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 865 866 This option defaults to 0. 867 868- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 869 select the TPM interface. Currently only one interface is supported: 870 871 :: 872 873 FIFO_SPI 874 875- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 876 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 877 878- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 879 options to the compiler. An example usage: 880 881 .. code:: make 882 883 MARCH_DIRECTIVE := -march=armv8.5-a 884 885- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 886 options to the compiler currently supporting only of the options. 887 GCC documentation: 888 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 889 890 An example usage: 891 892 .. code:: make 893 894 HARDEN_SLS := 1 895 896 This option defaults to 0. 897 898- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 899 specifies a file that contains the Non-Trusted World private key in PEM 900 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 901 will be used to save the key. 902 903- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 904 optional. It is only needed if the platform makefile specifies that it 905 is required in order to build the ``fwu_fip`` target. 906 907- ``NS_TIMER_SWITCH``: (deprecated) Enable save and restore for non-secure 908 timer register contents upon world switch. It can take either 0 (don't save 909 and restore) or 1 (do save and restore). 0 is the default. An SPD may set 910 this to 1 if it wants the timer registers to be saved and restored. This 911 option has been deprecated since it breaks Linux preemption model. 912 913- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 914 for the BL image. It can be either 0 (include) or 1 (remove). The default 915 value is 0. 916 917- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 918 the underlying hardware is not a full PL011 UART but a minimally compliant 919 generic UART, which is a subset of the PL011. The driver will not access 920 any register that is not part of the SBSA generic UART specification. 921 Default value is 0 (a full PL011 compliant UART is present). 922 923- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 924 must be subdirectory of any depth under ``plat/``, and must contain a 925 platform makefile named ``platform.mk``. For example, to build TF-A for the 926 Arm Juno board, select PLAT=juno. 927 928- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 929 each core as well as the global context. The data includes the memory used 930 by each world and each privileged exception level. This build option is 931 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 932 933- ``PLAT_EXTRA_LD_SCRIPT``: Allows the platform to include a custom LD script 934 snippet for any custom sections that cannot be expressed otherwise. Defaults 935 to 0. 936 937- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 938 instead of the normal boot flow. When defined, it must specify the entry 939 point address for the preloaded BL33 image. This option is incompatible with 940 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 941 over ``PRELOADED_BL33_BASE``. 942 943- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 944 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 945 registers when the cluster goes through a power cycle. This is disabled by 946 default and platforms that require this feature have to enable them. 947 948- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 949 vector address can be programmed or is fixed on the platform. It can take 950 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 951 programmable reset address, it is expected that a CPU will start executing 952 code directly at the right address, both on a cold and warm reset. In this 953 case, there is no need to identify the entrypoint on boot and the boot path 954 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 955 does not need to be implemented in this case. 956 957- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 958 possible for the PSCI power-state parameter: original and extended State-ID 959 formats. This flag if set to 1, configures the generic PSCI layer to use the 960 extended format. The default value of this flag is 0, which means by default 961 the original power-state format is used by the PSCI implementation. This flag 962 should be specified by the platform makefile and it governs the return value 963 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 964 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 965 set to 1 as well. 966 967- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 968 OS-initiated mode. This option defaults to 0. 969 970- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 971 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 972 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 973 defaults to 0. 974 975- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 976 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 977 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 978 NOTE: This flag enables use of IESB capability to reduce entry latency into 979 EL3 even when RAS error handling is not performed on the platform. Hence this 980 flag is recommended to be turned on Armv8.2 and later CPUs. 981 982- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 983 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 984 entrypoint) or 1 (CPU reset to BL31 entrypoint). 985 The default value is 0. 986 987- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 988 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 989 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 990 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 991 992- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 993- blocks) covered by a single bit of the bitlock structure during RME GPT 994- operations. The lower the block size, the better opportunity for 995- parallelising GPT operations but at the cost of more bits being needed 996- for the bitlock structure. This numeric parameter can take the values 997- from 0 to 512 and must be a power of 2. The value of 0 is special and 998- and it chooses a single spinlock for all GPT L1 table entries. Default 999- value is 1 which corresponds to block size of 512MB per bit of bitlock 1000- structure. 1001 1002- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 1003 supported contiguous blocks in GPT Library. This parameter can take the 1004 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 1005 descriptors. Default value is 512. 1006 1007- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1008 file that contains the ROT private key in PEM format or a PKCS11 URI and 1009 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 1010 accepted and it will be used to save the key. 1011 1012- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 1013 certificate generation tool to save the keys used to establish the Chain of 1014 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 1015 1016- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 1017 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 1018 target. 1019 1020- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1021 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 1022 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 1023 1024- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 1025 optional. It is only needed if the platform makefile specifies that it 1026 is required in order to build the ``fwu_fip`` target. 1027 1028- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 1029 Delegated Exception Interface to BL31 image. This defaults to ``0``. 1030 1031 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 1032 set to ``1``. 1033 1034- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 1035 isolated on separate memory pages. This is a trade-off between security and 1036 memory usage. See "Isolating code and read-only data on separate memory 1037 pages" section in :ref:`Firmware Design`. This flag is disabled by default 1038 and affects all BL images. 1039 1040- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 1041 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 1042 allocated in RAM discontiguous from the loaded firmware image. When set, the 1043 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 1044 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 1045 sections are placed in RAM immediately following the loaded firmware image. 1046 1047- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 1048 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 1049 discontiguous from loaded firmware images. When set, the platform need to 1050 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 1051 flag is disabled by default and NOLOAD sections are placed in RAM immediately 1052 following the loaded firmware image. 1053 1054- ``SEPARATE_BL2_FIP``: This option enables the separation of the BL2 FIP image 1055 from the main FIP image. When this option is enabled, the BL2 FIP image is built 1056 as a separate FIP image. The default value is 0. 1057 1058- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 1059 data structures to be put in a dedicated memory region as decided by platform 1060 integrator. Default value is ``0`` which means the SIMD context is put in BSS 1061 section of EL3 firmware. 1062 1063- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 1064 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 1065 UEFI+ACPI this can provide a certain amount of OS forward compatibility 1066 with newer platforms that aren't ECAM compliant. 1067 1068- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 1069 This build option is only valid if ``ARCH=aarch64``. The value should be 1070 the path to the directory containing the SPD source, relative to 1071 ``services/spd/``; the directory is expected to contain a makefile called 1072 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1073 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1074 cannot be enabled when the ``SPM_MM`` option is enabled. 1075 1076- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1077 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1078 execution in BL1 just before handing over to BL31. At this point, all 1079 firmware images have been loaded in memory, and the MMU and caches are 1080 turned off. Refer to the "Debugging options" section for more details. 1081 1082- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1083 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1084 component runs at the EL3 exception level. The default value is ``0`` ( 1085 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1086 implementing the ``FEAT_SEL2`` extension). 1087 1088- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1089 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1090 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1091 1092- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1093 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1094 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1095 mechanism should be used. 1096 1097- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1098 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1099 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1100 extension. This is the default when enabling the SPM Dispatcher. When 1101 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1102 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1103 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1104 extension). 1105 1106- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1107 Partition Manager (SPM) implementation. The default value is ``0`` 1108 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1109 enabled (``SPD=spmd``). 1110 1111- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1112 description of secure partitions. The build system will parse this file and 1113 package all secure partition blobs into the FIP. This file is not 1114 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1115 1116- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1117 secure interrupts (caught through the FIQ line). Platforms can enable 1118 this directive if they need to handle such interruption. When enabled, 1119 the FIQ are handled in monitor mode and non secure world is not allowed 1120 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1121 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1122 1123- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1124 Platforms can configure this if they need to lower the hardware 1125 limit, for example due to asymmetric configuration or limitations of 1126 software run at lower ELs. The default is the architectural maximum 1127 of 2048 which should be suitable for most configurations, the 1128 hardware will limit the effective VL to the maximum physically supported 1129 VL. 1130 1131- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1132 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1133 1134- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1135 Boot feature. When set to '1', BL1 and BL2 images include support to load 1136 and verify the certificates and images in a FIP, and BL1 includes support 1137 for the Firmware Update. The default value is '0'. Generation and inclusion 1138 of certificates in the FIP and FWU_FIP depends upon the value of the 1139 ``GENERATE_COT`` option. 1140 1141 .. warning:: 1142 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1143 already exist in disk, they will be overwritten without further notice. 1144 1145- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1146 specifies a file that contains the Trusted World private key in PEM 1147 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1148 it will be used to save the key. 1149 1150- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1151 synchronous, (see "Initializing a BL32 Image" section in 1152 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1153 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1154 Default is 0. 1155 1156- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1157 routing model which routes non-secure interrupts asynchronously from TSP 1158 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1159 for saving and restoring the TSP context in this routing model. The 1160 default routing model (when the value is 0) is to route non-secure 1161 interrupts to TSP allowing it to save its context and hand over 1162 synchronously to EL3 via an SMC. 1163 1164 .. note:: 1165 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1166 must also be set to ``1``. 1167 1168- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1169 internal-trusted-storage) as SP in tb_fw_config device tree. 1170 1171- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1172 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1173 this delay. It can take values in the range (0-15). Default value is ``0`` 1174 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1175 Platforms need to explicitly update this value based on their requirements. 1176 1177- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1178 linker. When the ``LINKER`` build variable points to the armlink linker, 1179 this flag is enabled automatically. To enable support for armlink, platforms 1180 will have to provide a scatter file for the BL image. Currently, Tegra 1181 platforms use the armlink support to compile BL3-1 images. 1182 1183- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1184 memory region in the BL memory map or not (see "Use of Coherent memory in 1185 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1186 (Coherent memory region is included) or 0 (Coherent memory region is 1187 excluded). Default is 1. 1188 1189- ``USE_KERNEL_DT_CONVENTION``: When this option is enabled, the hardware 1190 device tree is passed to BL33 using register x0, aligning with the expectations 1191 of the Linux kernel on Arm platforms. If this option is disabled, a different 1192 register, typically x1, may be used instead. This build option is 1193 not necessary when firmware handoff is active (that is, when TRANSFER_LIST=1 1194 is set), and it will be removed once all platforms have transitioned to that 1195 convention. 1196 1197- ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver. 1198 The DSU driver allows save/restore of DSU PMU registers through 1199 ``PRESERVE_DSU_PMU_REGS`` build option, provides access to PMU registers at 1200 EL1 and allows platforms to configure powerdown and power settings of DSU. 1201 1202- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1203 firmware configuration framework. This will move the io_policies into a 1204 configuration device tree, instead of static structure in the code base. 1205 1206- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1207 at runtime using fconf. If this flag is enabled, COT descriptors are 1208 statically captured in tb_fw_config file in the form of device tree nodes 1209 and properties. Currently, COT descriptors used by BL2 are moved to the 1210 device tree and COT descriptors used by BL1 are retained in the code 1211 base statically. 1212 1213- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1214 runtime using firmware configuration framework. The platform specific SDEI 1215 shared and private events configuration is retrieved from device tree rather 1216 than static C structures at compile time. This is only supported if 1217 SDEI_SUPPORT build flag is enabled. 1218 1219- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1220 and Group1 secure interrupts using the firmware configuration framework. The 1221 platform specific secure interrupt property descriptor is retrieved from 1222 device tree in runtime rather than depending on static C structure at compile 1223 time. 1224 1225- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1226 This feature creates a library of functions to be placed in ROM and thus 1227 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1228 is 0. 1229 1230- ``V``: Verbose build. If assigned anything other than 0, the build commands 1231 are printed. Default is 0. 1232 1233- ``VERSION_STRING``: String used in the log output for each TF-A image. 1234 Defaults to a string formed by concatenating the version number, build type 1235 and build string. 1236 1237- ``W``: Warning level. Some compiler warning options of interest have been 1238 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1239 each level enabling more warning options. Default is 0. 1240 1241 This option is closely related to the ``E`` option, which enables 1242 ``-Werror``. 1243 1244 - ``W=0`` (default) 1245 1246 Enables a wide assortment of warnings, most notably ``-Wall`` and 1247 ``-Wextra``, as well as various bad practices and things that are likely to 1248 result in errors. Includes some compiler specific flags. No warnings are 1249 expected at this level for any build. 1250 1251 - ``W=1`` 1252 1253 Enables warnings we want the generic build to include but are too time 1254 consuming to fix at the moment. It re-enables warnings taken out for 1255 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1256 to eventually be merged into ``W=0``. Some warnings are expected on some 1257 builds, but new contributions should not introduce new ones. 1258 1259 - ``W=2`` (recommended) 1260 1261 Enables warnings we want the generic build to include but cannot be enabled 1262 due to external libraries. This level is expected to eventually be merged 1263 into ``W=0``. Lots of warnings are expected, primarily from external 1264 libraries like zlib and compiler-rt, but new controbutions should not 1265 introduce new ones. 1266 1267 - ``W=3`` 1268 1269 Enables warnings that are informative but not necessary and generally too 1270 verbose and frequently ignored. A very large number of warnings are 1271 expected. 1272 1273 The exact set of warning flags depends on the compiler and TF-A warning 1274 level, however they are all succinctly set in the top-level Makefile. Please 1275 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1276 individual flags. 1277 1278- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1279 the CPU after warm boot. This is applicable for platforms which do not 1280 require interconnect programming to enable cache coherency (eg: single 1281 cluster platforms). If this option is enabled, then warm boot path 1282 enables D-caches immediately after enabling MMU. This option defaults to 0. 1283 1284- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1285 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1286 The default value of this flag is ``0``. 1287 1288 ``AT`` speculative errata workaround disables stage1 page table walk for 1289 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1290 produces either the correct result or failure without TLB allocation. 1291 1292 This boolean option enables errata for all below CPUs. 1293 1294 +---------+--------------+-------------------------+ 1295 | Errata | CPU | Workaround Define | 1296 +=========+==============+=========================+ 1297 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1298 +---------+--------------+-------------------------+ 1299 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1300 +---------+--------------+-------------------------+ 1301 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1302 +---------+--------------+-------------------------+ 1303 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1304 +---------+--------------+-------------------------+ 1305 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1306 +---------+--------------+-------------------------+ 1307 1308 .. note:: 1309 This option is enabled by build only if platform sets any of above defines 1310 mentioned in ’Workaround Define' column in the table. 1311 If this option is enabled for the EL3 software then EL2 software also must 1312 implement this workaround due to the behaviour of the errata mentioned 1313 in new SDEN document which will get published soon. 1314 1315- ``ERRATA_SME_POWER_DOWN``: Boolean option to disable SME (PSTATE.{ZA,SM}=0) 1316 before power down and downgrade a suspend to power down request to a normal 1317 suspend request. This is necessary when software running at lower ELs requests 1318 power down without first clearing these bits. On affected cores, the CME 1319 connected to it will reject its power down request. The default value is 0. 1320 1321- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1322 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1323 This flag is disabled by default. 1324 1325- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1326 host machine where a custom installation of OpenSSL is located, which is used 1327 to build the certificate generation, firmware encryption and FIP tools. If 1328 this option is not set, the default OS installation will be used. 1329 1330- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1331 functions that wait for an arbitrary time length (udelay and mdelay). The 1332 default value is 0. 1333 1334- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1335 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1336 optional architectural feature for AArch64. This flag can take the values 1337 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1338 and it is automatically disabled when the target architecture is AArch32. 1339 1340- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1341 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1342 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1343 feature for AArch64. This flag can take the values 0 to 2, to align with the 1344 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1345 disabled when the target architecture is AArch32. 1346 1347- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1348 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1349 but unused). This feature is available if trace unit such as ETMv4.x, and 1350 ETE(extending ETM feature) is implemented. This flag can take the values 1351 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1352 1353- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1354 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1355 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1356 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1357 1358- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1359 ``plat_can_cmo`` which will return zero if cache management operations should 1360 be skipped and non-zero otherwise. By default, this option is disabled which 1361 means platform hook won't be checked and CMOs will always be performed when 1362 related functions are called. 1363 1364- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1365 firmware interface for the BL31 image. By default its disabled (``0``). 1366 1367- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1368 errata mitigation for platforms with a non-arm interconnect using the errata 1369 ABI. By default its disabled (``0``). 1370 1371- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1372 driver(s). By default it is disabled (``0``) because it constitutes an attack 1373 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1374 This option should only be enabled on a need basis if there is a use case for 1375 reading characters from the console. 1376 1377GIC driver options 1378-------------------- 1379 1380The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1381a numeric option that can take the following values: 1382 1383 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1384 code. Strongly discouraged for GIC based interrupt controllers. 1385 1386 - ``1``: enable the use of the generic GIC driver but do not include any files 1387 or function definitions. It is then the platform's responsibility to provide 1388 these. This is useful if the platform either has a custom GIC implementation 1389 or an alternative interrupt controller design. Use of this option is strongly 1390 discouraged for standard GIC implementations. 1391 1392 - ``2``: use the GICv2 driver 1393 1394 - ``3``: use the GICv3 driver. See the next section on how to further configure 1395 it. Use this option for GICv4 implementations. Requires calling 1396 ``gic_set_gicr_frames()``. 1397 1398 - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``. 1399 1400 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1401 context on a power domain state transition, as well as any GIC actions outside 1402 of the PSCI library's visibility are the platform's responsibility. The driver 1403 provides implementations of all necessary subroutines, they only need to be 1404 called as appropriate. 1405 1406GICv3 driver options 1407~~~~~~~~~~~~~~~~~~~~ 1408 1409``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1410old (deprecated) way of included them is using the directive: 1411``include drivers/arm/gic/v3/gicv3.mk`` 1412 1413The driver can be configured with the following options set in the platform 1414makefile: 1415 1416- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1417 Enabling this option will add runtime detection support for the 1418 GIC-600, so is safe to select even for a GIC500 implementation. 1419 This option defaults to 0. 1420 1421- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1422 for GIC-600 AE. Enabling this option will introduce support to initialize 1423 the FMU. Platforms should call the init function during boot to enable the 1424 FMU and its safety mechanisms. This option defaults to 0. 1425 1426- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1427 functionality. This option defaults to 0 1428 1429- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1430 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1431 functions. This is required for FVP platform which need to simulate GIC save 1432 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1433 1434- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1435 This option defaults to 0. 1436 1437- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1438 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1439 1440Debugging options 1441----------------- 1442 1443To compile a debug version and make the build more verbose use 1444 1445.. code:: shell 1446 1447 make PLAT=<platform> DEBUG=1 V=1 all 1448 1449AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1450(for example Arm-DS) might not support this and may need an older version of 1451DWARF symbols to be emitted by GCC. This can be achieved by using the 1452``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1453the version to 4 is recommended for Arm-DS. 1454 1455When debugging logic problems it might also be useful to disable all compiler 1456optimizations by using ``-O0``. 1457 1458.. warning:: 1459 Using ``-O0`` could cause output images to be larger and base addresses 1460 might need to be recalculated (see the **Memory layout on Arm development 1461 platforms** section in the :ref:`Firmware Design`). 1462 1463Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1464``LDFLAGS``: 1465 1466.. code:: shell 1467 1468 CFLAGS='-O0 -gdwarf-2' \ 1469 make PLAT=<platform> DEBUG=1 V=1 all 1470 1471Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1472ignored as the linker is called directly. 1473 1474It is also possible to introduce an infinite loop to help in debugging the 1475post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1476``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1477section. In this case, the developer may take control of the target using a 1478debugger when indicated by the console output. When using Arm-DS, the following 1479commands can be used: 1480 1481:: 1482 1483 # Stop target execution 1484 interrupt 1485 1486 # 1487 # Prepare your debugging environment, e.g. set breakpoints 1488 # 1489 1490 # Jump over the debug loop 1491 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1492 1493 # Resume execution 1494 continue 1495 1496.. _build_options_experimental: 1497 1498Experimental build options 1499--------------------------- 1500 1501Common build options 1502~~~~~~~~~~~~~~~~~~~~ 1503 1504- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1505 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1506 set to ``1`` then measurements and additional metadata collected during the 1507 measured boot process are sent to the DICE Protection Environment for storage 1508 and processing. A certificate chain, which represents the boot state of the 1509 device, can be queried from the DPE. 1510 1511- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1512 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1513 the measurements and recording them as per `PSA DRTM specification`_. For 1514 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1515 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1516 should have mechanism to authenticate BL31. This option defaults to 0. 1517 1518- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1519 Management Extension. This flag can take the values 0 to 2, to align with 1520 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1521 1522- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1523 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1524 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1525 contexts for Realm security state and only one encryption context for the 1526 rest of the security states. Default value is 0. 1527 1528- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1529 realm attestation token signing requests in EL3. This flag can take the 1530 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1531 enables additional RMMD SMCs to push and pop requests for signing to 1532 EL3 along with platform hooks that must be implemented to service those 1533 requests and responses. 1534 1535- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1536 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1537 registers so are enabled together. Using this option without 1538 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1539 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1540 superset of SVE. SME is an optional architectural feature for AArch64. 1541 At this time, this build option cannot be used on systems that have 1542 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1543 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1544 mechanism. Default is 0. 1545 1546- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1547 version 2 (SME2) for the non-secure world only. SME2 is an optional 1548 architectural feature for AArch64. 1549 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1550 accesses will still be trapped. This flag can take the values 0 to 2, to 1551 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1552 1553- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1554 Extension for secure world. Used along with SVE and FPU/SIMD. 1555 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1556 Default is 0. 1557 1558- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1559 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1560 for logical partitions in EL3, managed by the SPMD as defined in the 1561 FF-A v1.2 specification. This flag is disabled by default. This flag 1562 must not be used if ``SPMC_AT_EL3`` is enabled. 1563 1564- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1565 verification mechanism. This is a debug feature that compares the 1566 architectural features enabled through the feature specific build flags 1567 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1568 and reports any discrepancies. 1569 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1570 1571 It is expected that this feature is only used for flexible platforms like 1572 software emulators, or for hardware platforms at bringup time, to verify 1573 that the configured feature set matches the CPU. 1574 The ``FEATURE_DETECTION`` macro is disabled by default. 1575 1576- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1577 The platform will use PSA compliant Crypto APIs during authentication and 1578 image measurement process by enabling this option. It uses APIs defined as 1579 per the `PSA Crypto API specification`_. This feature is only supported if 1580 using MbedTLS 3.x version. It is disabled (``0``) by default. 1581 1582- ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware 1583 activation as per the specification. This option defaults to 0. 1584 1585- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1586 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1587 This defaults to ``0``. Current implementation follows the Firmware Handoff 1588 specification v0.9. 1589 1590- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1591 interface through BL31 as a SiP SMC function. 1592 Default is disabled (0). 1593 1594- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1595 information using HOB defined in `Platform Initialization specification`_. 1596 This defaults to ``0``. 1597 1598- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1599 handler code to handle SMC calls from the Architecture Compliance Suite. The 1600 handler is intentionally empty to reserve the SMC section and allow 1601 project-specific implementations in future ACS use cases. 1602 1603Firmware update options 1604~~~~~~~~~~~~~~~~~~~~~~~ 1605 1606- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1607 `PSA FW update specification`_. The default value is 0. 1608 PSA firmware update implementation has few limitations, such as: 1609 1610 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1611 be updated, then it should be done through another platform-defined 1612 mechanism. 1613 1614 - It assumes the platform's hardware supports CRC32 instructions. 1615 1616- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1617 in defining the firmware update metadata structure. This flag is by default 1618 set to '2'. 1619 1620- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1621 firmware bank. Each firmware bank must have the same number of images as per 1622 the `PSA FW update specification`_. 1623 This flag is used in defining the firmware update metadata structure. This 1624 flag is by default set to '1'. 1625 1626- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1627 metadata contains image description. The default value is 1. 1628 1629 The version 2 of the FWU metadata allows for an opaque metadata 1630 structure where a platform can choose to not include the firmware 1631 store description in the metadata structure. This option indicates 1632 if the firmware store description, which provides information on 1633 the updatable images is part of the structure. 1634 1635-------------- 1636 1637*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 1638 1639.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1640.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1641.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1642.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1643.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1644.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1645.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1646.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1647.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ 1648