1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/fpmr.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 } 153 154 #if ENABLE_RME && IMAGE_BL31 155 /****************************************************************************** 156 * This function performs initializations that are specific to REALM state 157 * and updates the cpu context specified by 'ctx'. 158 * 159 * NOTE: any changes to this function must be verified by an RMMD maintainer. 160 *****************************************************************************/ 161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 162 { 163 u_register_t scr_el3; 164 el3_state_t *state; 165 el2_sysregs_t *el2_ctx; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 el2_ctx = get_el2_sysregs_ctx(ctx); 170 171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 172 173 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 174 175 /* CSV2 version 2 and above */ 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 if (is_feat_sctlr2_supported()) { 182 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 183 * SCTLR2_ELx registers. 184 */ 185 scr_el3 |= SCR_SCTLR2En_BIT; 186 } 187 188 if (is_feat_d128_supported()) { 189 /* 190 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 191 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 192 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 193 */ 194 scr_el3 |= SCR_D128En_BIT; 195 } 196 197 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 198 199 if (is_feat_fgt2_supported()) { 200 fgt2_enable(ctx); 201 } 202 203 if (is_feat_debugv8p9_supported()) { 204 debugv8p9_extended_bp_wp_enable(ctx); 205 } 206 207 if (is_feat_brbe_supported()) { 208 brbe_enable(ctx); 209 } 210 211 /* 212 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 213 */ 214 if (is_feat_sme_supported()) { 215 sme_enable(ctx); 216 } 217 218 if (is_feat_spe_supported()) { 219 spe_disable_realm(ctx); 220 } 221 222 if (is_feat_trbe_supported()) { 223 trbe_disable_realm(ctx); 224 } 225 } 226 #endif /* ENABLE_RME && IMAGE_BL31 */ 227 228 /****************************************************************************** 229 * This function performs initializations that are specific to NON-SECURE state 230 * and updates the cpu context specified by 'ctx'. 231 *****************************************************************************/ 232 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 233 { 234 u_register_t scr_el3; 235 el3_state_t *state; 236 237 state = get_el3state_ctx(ctx); 238 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 239 240 /* SCR_NS: Set the NS bit */ 241 scr_el3 |= SCR_NS_BIT; 242 243 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 244 if (is_feat_mte2_supported()) { 245 scr_el3 |= SCR_ATA_BIT; 246 } 247 248 /* 249 * Pointer Authentication feature, if present, is always enabled by 250 * default for Non secure lower exception levels. We do not have an 251 * explicit flag to set it. To prevent the leakage between the worlds 252 * during world switch, we enable it only for the non-secure world. 253 * 254 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 255 * exception levels of secure and realm worlds. 256 * 257 * If the Secure/realm world wants to use pointer authentication, 258 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 259 * it will be enabled globally for all the contexts. 260 * 261 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 262 * other than EL3 263 * 264 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 265 * than EL3 266 */ 267 if (!is_ctx_pauth_supported()) { 268 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 269 } 270 271 #if HANDLE_EA_EL3_FIRST_NS 272 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 273 scr_el3 |= SCR_EA_BIT; 274 #endif 275 276 #if RAS_TRAP_NS_ERR_REC_ACCESS 277 /* 278 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 279 * and RAS ERX registers from EL1 and EL2(from any security state) 280 * are trapped to EL3. 281 * Set here to trap only for NS EL1/EL2 282 */ 283 scr_el3 |= SCR_TERR_BIT; 284 #endif 285 286 /* CSV2 version 2 and above */ 287 if (is_feat_csv2_2_supported()) { 288 /* Enable access to the SCXTNUM_ELx registers. */ 289 scr_el3 |= SCR_EnSCXT_BIT; 290 } 291 292 #ifdef IMAGE_BL31 293 /* 294 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 295 * indicated by the interrupt routing model for BL31. 296 */ 297 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 298 #endif 299 300 if (is_feat_the_supported()) { 301 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 302 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 303 */ 304 scr_el3 |= SCR_RCWMASKEn_BIT; 305 } 306 307 if (is_feat_sctlr2_supported()) { 308 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 309 * SCTLR2_ELx registers. 310 */ 311 scr_el3 |= SCR_SCTLR2En_BIT; 312 } 313 314 if (is_feat_d128_supported()) { 315 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 316 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 317 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 318 */ 319 scr_el3 |= SCR_D128En_BIT; 320 } 321 322 if (is_feat_fpmr_supported()) { 323 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 324 * register. 325 */ 326 scr_el3 |= SCR_EnFPM_BIT; 327 } 328 329 if (is_feat_aie_supported()) { 330 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 331 * system registers from NS world. 332 */ 333 scr_el3 |= SCR_AIEn_BIT; 334 } 335 336 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 337 338 /* Initialize EL2 context registers */ 339 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 340 if (is_feat_hcx_supported()) { 341 /* 342 * Initialize register HCRX_EL2 with its init value. 343 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 344 * chance that this can lead to unexpected behavior in lower 345 * ELs that have not been updated since the introduction of 346 * this feature if not properly initialized, especially when 347 * it comes to those bits that enable/disable traps. 348 */ 349 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 350 HCRX_EL2_INIT_VAL); 351 } 352 353 if (is_feat_fgt_supported()) { 354 /* 355 * Initialize HFG*_EL2 registers with a default value so legacy 356 * systems unaware of FEAT_FGT do not get trapped due to their lack 357 * of initialization for this feature. 358 */ 359 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 360 HFGITR_EL2_INIT_VAL); 361 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 362 HFGRTR_EL2_INIT_VAL); 363 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 364 HFGWTR_EL2_INIT_VAL); 365 } 366 #else 367 /* Initialize EL1 context registers */ 368 setup_el1_context(ctx, ep); 369 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 370 371 manage_extensions_nonsecure(ctx); 372 } 373 374 /******************************************************************************* 375 * The following function performs initialization of the cpu_context 'ctx' 376 * for first use that is common to all security states, and sets the 377 * initial entrypoint state as specified by the entry_point_info structure. 378 * 379 * The EE and ST attributes are used to configure the endianness and secure 380 * timer availability for the new execution context. 381 ******************************************************************************/ 382 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 383 { 384 u_register_t scr_el3; 385 u_register_t mdcr_el3; 386 el3_state_t *state; 387 gp_regs_t *gp_regs; 388 389 state = get_el3state_ctx(ctx); 390 391 /* Clear any residual register values from the context */ 392 zeromem(ctx, sizeof(*ctx)); 393 394 /* 395 * The lower-EL context is zeroed so that no stale values leak to a world. 396 * It is assumed that an all-zero lower-EL context is good enough for it 397 * to boot correctly. However, there are very few registers where this 398 * is not true and some values need to be recreated. 399 */ 400 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 401 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 402 403 /* 404 * These bits are set in the gicv3 driver. Losing them (especially the 405 * SRE bit) is problematic for all worlds. Henceforth recreate them. 406 */ 407 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 408 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 409 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 410 411 /* 412 * The actlr_el2 register can be initialized in platform's reset handler 413 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 414 */ 415 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 416 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 417 418 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 419 scr_el3 = SCR_RESET_VAL; 420 421 /* 422 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 423 * EL2, EL1 and EL0 are not trapped to EL3. 424 * 425 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 426 * EL2, EL1 and EL0 are not trapped to EL3. 427 * 428 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 429 * both Security states and both Execution states. 430 * 431 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 432 * Non-secure memory. 433 */ 434 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 435 436 scr_el3 |= SCR_SIF_BIT; 437 438 /* 439 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 440 * Exception level as specified by SPSR. 441 */ 442 if (GET_RW(ep->spsr) == MODE_RW_64) { 443 scr_el3 |= SCR_RW_BIT; 444 } 445 446 /* 447 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 448 * Secure timer registers to EL3, from AArch64 state only, if specified 449 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 450 * bit always behaves as 1 (i.e. secure physical timer register access 451 * is not trapped) 452 */ 453 if (EP_GET_ST(ep->h.attr) != 0U) { 454 scr_el3 |= SCR_ST_BIT; 455 } 456 457 /* 458 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 459 * SCR_EL3.HXEn. 460 */ 461 if (is_feat_hcx_supported()) { 462 scr_el3 |= SCR_HXEn_BIT; 463 } 464 465 /* 466 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 467 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 468 * SCR_EL3.EnAS0. 469 */ 470 if (is_feat_ls64_accdata_supported()) { 471 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 472 } 473 474 /* 475 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 476 * registers are trapped to EL3. 477 */ 478 if (is_feat_rng_trap_supported()) { 479 scr_el3 |= SCR_TRNDR_BIT; 480 } 481 482 #if FAULT_INJECTION_SUPPORT 483 /* Enable fault injection from lower ELs */ 484 scr_el3 |= SCR_FIEN_BIT; 485 #endif 486 487 /* 488 * Enable Pointer Authentication globally for all the worlds. 489 * 490 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 491 * other than EL3 492 * 493 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 494 * than EL3 495 */ 496 if (is_ctx_pauth_supported()) { 497 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 498 } 499 500 /* 501 * SCR_EL3.PIEN: Enable permission indirection and overlay 502 * registers for AArch64 if present. 503 */ 504 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 505 scr_el3 |= SCR_PIEN_BIT; 506 } 507 508 /* 509 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 510 */ 511 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 512 scr_el3 |= SCR_GCSEn_BIT; 513 } 514 515 /* 516 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 517 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 518 * next mode is Hyp. 519 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 520 * same conditions as HVC instructions and when the processor supports 521 * ARMv8.6-FGT. 522 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 523 * CNTPOFF_EL2 register under the same conditions as HVC instructions 524 * and when the processor supports ECV. 525 */ 526 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 527 || ((GET_RW(ep->spsr) != MODE_RW_64) 528 && (GET_M32(ep->spsr) == MODE32_hyp))) { 529 scr_el3 |= SCR_HCE_BIT; 530 531 if (is_feat_fgt_supported()) { 532 scr_el3 |= SCR_FGTEN_BIT; 533 } 534 535 if (is_feat_ecv_supported()) { 536 scr_el3 |= SCR_ECVEN_BIT; 537 } 538 } 539 540 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 541 if (is_feat_twed_supported()) { 542 /* Set delay in SCR_EL3 */ 543 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 544 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 545 << SCR_TWEDEL_SHIFT); 546 547 /* Enable WFE delay */ 548 scr_el3 |= SCR_TWEDEn_BIT; 549 } 550 551 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 552 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 553 if (is_feat_sel2_supported()) { 554 scr_el3 |= SCR_EEL2_BIT; 555 } 556 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 557 558 if (is_feat_mec_supported()) { 559 scr_el3 |= SCR_MECEn_BIT; 560 } 561 562 /* 563 * Populate EL3 state so that we've the right context 564 * before doing ERET 565 */ 566 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 567 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 568 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 569 570 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 571 mdcr_el3 = MDCR_EL3_RESET_VAL; 572 573 /* --------------------------------------------------------------------- 574 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 575 * Some fields are architecturally UNKNOWN on reset. 576 * 577 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 578 * Debug exceptions, other than Breakpoint Instruction exceptions, are 579 * disabled from all ELs in Secure state. 580 * 581 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 582 * privileged debug from S-EL1. 583 * 584 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 585 * access to the powerdown debug registers do not trap to EL3. 586 * 587 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 588 * debug registers, other than those registers that are controlled by 589 * MDCR_EL3.TDOSA. 590 */ 591 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 592 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 593 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 594 595 #if IMAGE_BL31 596 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 597 if (is_feat_trf_supported()) { 598 trf_enable(ctx); 599 } 600 601 if (is_feat_tcr2_supported()) { 602 tcr2_enable(ctx); 603 } 604 605 pmuv3_enable(ctx); 606 607 #if CTX_INCLUDE_EL2_REGS 608 /* 609 * Initialize SCTLR_EL2 context register with reset value. 610 */ 611 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 612 #endif /* CTX_INCLUDE_EL2_REGS */ 613 #endif /* IMAGE_BL31 */ 614 615 /* 616 * Store the X0-X7 value from the entrypoint into the context 617 * Use memcpy as we are in control of the layout of the structures 618 */ 619 gp_regs = get_gpregs_ctx(ctx); 620 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 621 } 622 623 /******************************************************************************* 624 * Context management library initialization routine. This library is used by 625 * runtime services to share pointers to 'cpu_context' structures for secure 626 * non-secure and realm states. Management of the structures and their associated 627 * memory is not done by the context management library e.g. the PSCI service 628 * manages the cpu context used for entry from and exit to the non-secure state. 629 * The Secure payload dispatcher service manages the context(s) corresponding to 630 * the secure state. It also uses this library to get access to the non-secure 631 * state cpu context pointers. 632 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 633 * which will be used for programming an entry into a lower EL. The same context 634 * will be used to save state upon exception entry from that EL. 635 ******************************************************************************/ 636 void __init cm_init(void) 637 { 638 /* 639 * The context management library has only global data to initialize, but 640 * that will be done when the BSS is zeroed out. 641 */ 642 } 643 644 /******************************************************************************* 645 * This is the high-level function used to initialize the cpu_context 'ctx' for 646 * first use. It performs initializations that are common to all security states 647 * and initializations specific to the security state specified in 'ep' 648 ******************************************************************************/ 649 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 650 { 651 size_t security_state; 652 653 assert(ctx != NULL); 654 655 /* 656 * Perform initializations that are common 657 * to all security states 658 */ 659 setup_context_common(ctx, ep); 660 661 security_state = GET_SECURITY_STATE(ep->h.attr); 662 663 /* Perform security state specific initializations */ 664 switch (security_state) { 665 case SECURE: 666 setup_secure_context(ctx, ep); 667 break; 668 #if ENABLE_RME && IMAGE_BL31 669 case REALM: 670 setup_realm_context(ctx, ep); 671 break; 672 #endif 673 case NON_SECURE: 674 setup_ns_context(ctx, ep); 675 break; 676 default: 677 ERROR("Invalid security state\n"); 678 panic(); 679 break; 680 } 681 } 682 683 /******************************************************************************* 684 * Enable architecture extensions for EL3 execution. This function only updates 685 * registers in-place which are expected to either never change or be 686 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 687 ******************************************************************************/ 688 #if IMAGE_BL31 689 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 690 { 691 if (is_feat_pauth_supported()) { 692 pauth_init_enable_el3(); 693 } 694 695 if (is_feat_sve_supported()) { 696 sve_init_el3(); 697 } 698 699 if (is_feat_amu_supported()) { 700 amu_init_el3(my_idx); 701 } 702 703 if (is_feat_sme_supported()) { 704 sme_init_el3(); 705 } 706 707 if (is_feat_fgwte3_supported()) { 708 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 709 } 710 711 if (is_feat_mpam_supported()) { 712 mpam_init_el3(); 713 } 714 715 if (is_feat_cpa2_supported()) { 716 cpa2_enable_el3(); 717 } 718 719 pmuv3_init_el3(); 720 } 721 722 /****************************************************************************** 723 * Function to initialise the registers with the RESET values in the context 724 * memory, which are maintained per world. 725 ******************************************************************************/ 726 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 727 { 728 /* 729 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 730 * 731 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 732 * by Advanced SIMD, floating-point or SVE instructions (if 733 * implemented) do not trap to EL3. 734 * 735 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 736 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 737 */ 738 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 739 740 per_world_ctx->ctx_cptr_el3 = cptr_el3; 741 742 /* 743 * Initialize MPAM3_EL3 to its default reset value 744 * 745 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 746 * all lower ELn MPAM3_EL3 register access to, trap to EL3 747 */ 748 749 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 750 } 751 752 /******************************************************************************* 753 * Initialise per_world_context for Non-Secure world. 754 * This function enables the architecture extensions, which have same value 755 * across the cores for the non-secure world. 756 ******************************************************************************/ 757 static void manage_extensions_nonsecure_per_world(void) 758 { 759 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 760 761 if (is_feat_sme_supported()) { 762 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 763 } 764 765 if (is_feat_sve_supported()) { 766 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 767 } 768 769 if (is_feat_amu_supported()) { 770 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 771 } 772 773 if (is_feat_sys_reg_trace_supported()) { 774 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 775 } 776 777 if (is_feat_mpam_supported()) { 778 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 779 } 780 781 if (is_feat_fpmr_supported()) { 782 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 783 } 784 } 785 786 /******************************************************************************* 787 * Initialise per_world_context for Secure world. 788 * This function enables the architecture extensions, which have same value 789 * across the cores for the secure world. 790 ******************************************************************************/ 791 static void manage_extensions_secure_per_world(void) 792 { 793 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 794 795 if (is_feat_sme_supported()) { 796 797 if (ENABLE_SME_FOR_SWD) { 798 /* 799 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 800 * SME, SVE, and FPU/SIMD context properly managed. 801 */ 802 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 803 } else { 804 /* 805 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 806 * world can safely use the associated registers. 807 */ 808 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 809 } 810 } 811 if (is_feat_sve_supported()) { 812 if (ENABLE_SVE_FOR_SWD) { 813 /* 814 * Enable SVE and FPU in secure context, SPM must ensure 815 * that the SVE and FPU register contexts are properly managed. 816 */ 817 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 818 } else { 819 /* 820 * Disable SVE and FPU in secure context so non-secure world 821 * can safely use them. 822 */ 823 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 824 } 825 } 826 827 /* NS can access this but Secure shouldn't */ 828 if (is_feat_sys_reg_trace_supported()) { 829 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 830 } 831 } 832 833 static void manage_extensions_realm_per_world(void) 834 { 835 #if ENABLE_RME 836 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 837 838 if (is_feat_sve_supported()) { 839 /* 840 * Enable SVE and FPU in realm context when it is enabled for NS. 841 * Realm manager must ensure that the SVE and FPU register 842 * contexts are properly managed. 843 */ 844 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 845 } 846 847 /* NS can access this but Realm shouldn't */ 848 if (is_feat_sys_reg_trace_supported()) { 849 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 850 } 851 852 /* 853 * If SME/SME2 is supported and enabled for NS world, then disable trapping 854 * of SME instructions for Realm world. RMM will save/restore required 855 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 856 */ 857 if (is_feat_sme_supported()) { 858 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 859 } 860 861 /* 862 * If FEAT_MPAM is supported and enabled, then disable trapping access 863 * to the MPAM registers for Realm world. Instead, RMM will configure 864 * the access to be trapped by itself so it can inject undefined aborts 865 * back to the Realm. 866 */ 867 if (is_feat_mpam_supported()) { 868 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 869 } 870 #endif /* ENABLE_RME */ 871 } 872 873 void cm_manage_extensions_per_world(void) 874 { 875 manage_extensions_nonsecure_per_world(); 876 manage_extensions_secure_per_world(); 877 manage_extensions_realm_per_world(); 878 } 879 #endif /* IMAGE_BL31 */ 880 881 /******************************************************************************* 882 * Enable architecture extensions on first entry to Non-secure world. 883 ******************************************************************************/ 884 static void manage_extensions_nonsecure(cpu_context_t *ctx) 885 { 886 #if IMAGE_BL31 887 /* NOTE: registers are not context switched */ 888 if (is_feat_amu_supported()) { 889 amu_enable(ctx); 890 } 891 892 if (is_feat_sme_supported()) { 893 sme_enable(ctx); 894 } 895 896 if (is_feat_fgt2_supported()) { 897 fgt2_enable(ctx); 898 } 899 900 if (is_feat_debugv8p9_supported()) { 901 debugv8p9_extended_bp_wp_enable(ctx); 902 } 903 904 if (is_feat_spe_supported()) { 905 spe_enable_ns(ctx); 906 } 907 908 if (is_feat_trbe_supported()) { 909 if (check_if_trbe_disable_affected_core()) { 910 trbe_disable_ns(ctx); 911 } else { 912 trbe_enable_ns(ctx); 913 } 914 } 915 916 if (is_feat_brbe_supported()) { 917 brbe_enable(ctx); 918 } 919 #endif /* IMAGE_BL31 */ 920 } 921 922 #if INIT_UNUSED_NS_EL2 923 /******************************************************************************* 924 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 925 * world when EL2 is empty and unused. 926 ******************************************************************************/ 927 static void manage_extensions_nonsecure_el2_unused(void) 928 { 929 #if IMAGE_BL31 930 if (is_feat_spe_supported()) { 931 spe_init_el2_unused(); 932 } 933 934 if (is_feat_amu_supported()) { 935 amu_init_el2_unused(); 936 } 937 938 if (is_feat_mpam_supported()) { 939 mpam_init_el2_unused(); 940 } 941 942 if (is_feat_trbe_supported()) { 943 trbe_init_el2_unused(); 944 } 945 946 if (is_feat_sys_reg_trace_supported()) { 947 sys_reg_trace_init_el2_unused(); 948 } 949 950 if (is_feat_trf_supported()) { 951 trf_init_el2_unused(); 952 } 953 954 pmuv3_init_el2_unused(); 955 956 if (is_feat_sve_supported()) { 957 sve_init_el2_unused(); 958 } 959 960 if (is_feat_sme_supported()) { 961 sme_init_el2_unused(); 962 } 963 964 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 965 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 966 } 967 968 if (is_feat_pauth_supported()) { 969 pauth_enable_el2(); 970 } 971 #endif /* IMAGE_BL31 */ 972 } 973 #endif /* INIT_UNUSED_NS_EL2 */ 974 975 /******************************************************************************* 976 * Enable architecture extensions on first entry to Secure world. 977 ******************************************************************************/ 978 static void manage_extensions_secure(cpu_context_t *ctx) 979 { 980 #if IMAGE_BL31 981 if (is_feat_sme_supported()) { 982 if (ENABLE_SME_FOR_SWD) { 983 /* 984 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 985 * must ensure SME, SVE, and FPU/SIMD context properly managed. 986 */ 987 sme_init_el3(); 988 sme_enable(ctx); 989 } else { 990 /* 991 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 992 * world can safely use the associated registers. 993 */ 994 sme_disable(ctx); 995 } 996 } 997 998 if (is_feat_spe_supported()) { 999 spe_disable_secure(ctx); 1000 } 1001 1002 if (is_feat_trbe_supported()) { 1003 trbe_disable_secure(ctx); 1004 } 1005 #endif /* IMAGE_BL31 */ 1006 } 1007 1008 /******************************************************************************* 1009 * The following function initializes the cpu_context for the current CPU 1010 * for first use, and sets the initial entrypoint state as specified by the 1011 * entry_point_info structure. 1012 ******************************************************************************/ 1013 void cm_init_my_context(const entry_point_info_t *ep) 1014 { 1015 cpu_context_t *ctx; 1016 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1017 cm_setup_context(ctx, ep); 1018 } 1019 1020 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1021 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1022 { 1023 #if INIT_UNUSED_NS_EL2 1024 u_register_t hcr_el2 = HCR_RESET_VAL; 1025 u_register_t mdcr_el2; 1026 u_register_t scr_el3; 1027 1028 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1029 1030 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1031 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1032 hcr_el2 |= HCR_RW_BIT; 1033 } 1034 1035 write_hcr_el2(hcr_el2); 1036 1037 /* 1038 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1039 * All fields have architecturally UNKNOWN reset values. 1040 */ 1041 write_cptr_el2(CPTR_EL2_RESET_VAL); 1042 1043 /* 1044 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1045 * reset and are set to zero except for field(s) listed below. 1046 * 1047 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1048 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1049 * 1050 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1051 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1052 */ 1053 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1054 1055 /* 1056 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1057 * UNKNOWN value. 1058 */ 1059 write_cntvoff_el2(0); 1060 1061 /* 1062 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1063 * respectively. 1064 */ 1065 write_vpidr_el2(read_midr_el1()); 1066 write_vmpidr_el2(read_mpidr_el1()); 1067 1068 /* 1069 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1070 * 1071 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1072 * translation is disabled, cache maintenance operations depend on the 1073 * VMID. 1074 * 1075 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1076 * disabled. 1077 */ 1078 write_vttbr_el2(VTTBR_RESET_VAL & 1079 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1080 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1081 1082 /* 1083 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1084 * Some fields are architecturally UNKNOWN on reset. 1085 * 1086 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1087 * register accesses to the Debug ROM registers are not trapped to EL2. 1088 * 1089 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1090 * accesses to the powerdown debug registers are not trapped to EL2. 1091 * 1092 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1093 * debug registers do not trap to EL2. 1094 * 1095 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1096 * EL2. 1097 */ 1098 mdcr_el2 = MDCR_EL2_RESET_VAL & 1099 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1100 MDCR_EL2_TDE_BIT); 1101 1102 write_mdcr_el2(mdcr_el2); 1103 1104 /* 1105 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1106 * 1107 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1108 * EL1 accesses to System registers do not trap to EL2. 1109 */ 1110 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1111 1112 /* 1113 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1114 * reset. 1115 * 1116 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1117 * and prevent timer interrupts. 1118 */ 1119 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1120 1121 manage_extensions_nonsecure_el2_unused(); 1122 #endif /* INIT_UNUSED_NS_EL2 */ 1123 } 1124 1125 /******************************************************************************* 1126 * Prepare the CPU system registers for first entry into realm, secure, or 1127 * normal world. 1128 * 1129 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1130 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1131 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1132 * For all entries, the EL1 registers are initialized from the cpu_context 1133 ******************************************************************************/ 1134 void cm_prepare_el3_exit(size_t security_state) 1135 { 1136 u_register_t sctlr_el2, scr_el3; 1137 cpu_context_t *ctx = cm_get_context(security_state); 1138 1139 assert(ctx != NULL); 1140 1141 if (security_state == NON_SECURE) { 1142 uint64_t el2_implemented = el_implemented(2); 1143 1144 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1145 CTX_SCR_EL3); 1146 1147 if (el2_implemented != EL_IMPL_NONE) { 1148 1149 /* 1150 * If context is not being used for EL2, initialize 1151 * HCRX_EL2 with its init value here. 1152 */ 1153 if (is_feat_hcx_supported()) { 1154 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1155 } 1156 1157 /* 1158 * Initialize Fine-grained trap registers introduced 1159 * by FEAT_FGT so all traps are initially disabled when 1160 * switching to EL2 or a lower EL, preventing undesired 1161 * behavior. 1162 */ 1163 if (is_feat_fgt_supported()) { 1164 /* 1165 * Initialize HFG*_EL2 registers with a default 1166 * value so legacy systems unaware of FEAT_FGT 1167 * do not get trapped due to their lack of 1168 * initialization for this feature. 1169 */ 1170 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1171 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1172 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1173 } 1174 1175 /* Condition to ensure EL2 is being used. */ 1176 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1177 /* Initialize SCTLR_EL2 register with reset value. */ 1178 sctlr_el2 = SCTLR_EL2_RES1; 1179 1180 /* 1181 * If workaround of errata 764081 for Cortex-A75 1182 * is used then set SCTLR_EL2.IESB to enable 1183 * Implicit Error Synchronization Barrier. 1184 */ 1185 if (errata_a75_764081_applies()) { 1186 sctlr_el2 |= SCTLR_IESB_BIT; 1187 } 1188 1189 write_sctlr_el2(sctlr_el2); 1190 } else { 1191 /* 1192 * (scr_el3 & SCR_HCE_BIT==0) 1193 * EL2 implemented but unused. 1194 */ 1195 init_nonsecure_el2_unused(ctx); 1196 } 1197 } 1198 1199 if (is_feat_fgwte3_supported()) { 1200 /* 1201 * TCR_EL3 and ACTLR_EL3 could be overwritten 1202 * by platforms and hence is locked a bit late. 1203 */ 1204 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1205 } 1206 } 1207 #if (!CTX_INCLUDE_EL2_REGS) 1208 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1209 cm_el1_sysregs_context_restore(security_state); 1210 #endif 1211 cm_set_next_eret_context(security_state); 1212 } 1213 1214 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1215 1216 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1217 { 1218 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1219 if (is_feat_amu_supported()) { 1220 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1221 } 1222 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1223 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1224 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1225 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1226 } 1227 1228 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1229 { 1230 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1231 if (is_feat_amu_supported()) { 1232 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1233 } 1234 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1235 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1236 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1237 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1238 } 1239 1240 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1241 { 1242 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1243 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1244 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1245 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1246 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1247 } 1248 1249 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1250 { 1251 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1252 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1253 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1254 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1255 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1256 } 1257 1258 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1259 { 1260 u_register_t mpam_idr = read_mpamidr_el1(); 1261 1262 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1263 1264 /* 1265 * The context registers that we intend to save would be part of the 1266 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1267 */ 1268 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1269 return; 1270 } 1271 1272 /* 1273 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1274 * MPAMIDR_HAS_HCR_BIT == 1. 1275 */ 1276 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1277 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1278 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1279 1280 /* 1281 * The number of MPAMVPM registers is implementation defined, their 1282 * number is stored in the MPAMIDR_EL1 register. 1283 */ 1284 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1285 case 7: 1286 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1287 __fallthrough; 1288 case 6: 1289 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1290 __fallthrough; 1291 case 5: 1292 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1293 __fallthrough; 1294 case 4: 1295 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1296 __fallthrough; 1297 case 3: 1298 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1299 __fallthrough; 1300 case 2: 1301 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1302 __fallthrough; 1303 case 1: 1304 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1305 break; 1306 } 1307 } 1308 1309 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1310 { 1311 u_register_t mpam_idr = read_mpamidr_el1(); 1312 1313 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1314 1315 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1316 return; 1317 } 1318 1319 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1320 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1321 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1322 1323 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1324 case 7: 1325 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1326 __fallthrough; 1327 case 6: 1328 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1329 __fallthrough; 1330 case 5: 1331 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1332 __fallthrough; 1333 case 4: 1334 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1335 __fallthrough; 1336 case 3: 1337 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1338 __fallthrough; 1339 case 2: 1340 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1341 __fallthrough; 1342 case 1: 1343 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1344 break; 1345 } 1346 } 1347 1348 /* --------------------------------------------------------------------------- 1349 * The following registers are not added: 1350 * ICH_AP0R<n>_EL2 1351 * ICH_AP1R<n>_EL2 1352 * ICH_LR<n>_EL2 1353 * 1354 * NOTE: For a system with S-EL2 present but not enabled, accessing 1355 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1356 * SCR_EL3.NS = 1 before accessing this register. 1357 * --------------------------------------------------------------------------- 1358 */ 1359 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1360 { 1361 u_register_t scr_el3 = read_scr_el3(); 1362 1363 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1364 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1365 #else 1366 write_scr_el3(scr_el3 | SCR_NS_BIT); 1367 isb(); 1368 1369 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1370 1371 write_scr_el3(scr_el3); 1372 isb(); 1373 #endif 1374 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1375 1376 if (errata_ich_vmcr_el2_applies()) { 1377 if (security_state == SECURE) { 1378 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1379 } else { 1380 write_scr_el3(scr_el3 | SCR_NS_BIT); 1381 } 1382 isb(); 1383 } 1384 1385 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1386 1387 if (errata_ich_vmcr_el2_applies()) { 1388 write_scr_el3(scr_el3); 1389 isb(); 1390 } 1391 } 1392 1393 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1394 { 1395 u_register_t scr_el3 = read_scr_el3(); 1396 1397 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1398 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1399 #else 1400 write_scr_el3(scr_el3 | SCR_NS_BIT); 1401 isb(); 1402 1403 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1404 1405 write_scr_el3(scr_el3); 1406 isb(); 1407 #endif 1408 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1409 1410 if (errata_ich_vmcr_el2_applies()) { 1411 if (security_state == SECURE) { 1412 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1413 } else { 1414 write_scr_el3(scr_el3 | SCR_NS_BIT); 1415 } 1416 isb(); 1417 } 1418 1419 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1420 1421 if (errata_ich_vmcr_el2_applies()) { 1422 write_scr_el3(scr_el3); 1423 isb(); 1424 } 1425 } 1426 1427 /* ----------------------------------------------------- 1428 * The following registers are not added: 1429 * AMEVCNTVOFF0<n>_EL2 1430 * AMEVCNTVOFF1<n>_EL2 1431 * ----------------------------------------------------- 1432 */ 1433 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1434 { 1435 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1436 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1437 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1438 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1439 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1440 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1441 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1442 if (CTX_INCLUDE_AARCH32_REGS) { 1443 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1444 } 1445 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1446 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1447 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1448 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1449 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1450 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1451 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1452 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1453 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1454 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1455 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1456 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1457 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1458 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1459 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1460 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1461 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1462 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1463 1464 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1465 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1466 } 1467 1468 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1469 { 1470 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1471 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1472 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1473 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1474 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1475 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1476 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1477 if (CTX_INCLUDE_AARCH32_REGS) { 1478 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1479 } 1480 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1481 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1482 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1483 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1484 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1485 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1486 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1487 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1488 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1489 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1490 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1491 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1492 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1493 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1494 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1495 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1496 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1497 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1498 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1499 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1500 } 1501 1502 /******************************************************************************* 1503 * Save EL2 sysreg context 1504 ******************************************************************************/ 1505 void cm_el2_sysregs_context_save(uint32_t security_state) 1506 { 1507 cpu_context_t *ctx; 1508 el2_sysregs_t *el2_sysregs_ctx; 1509 1510 ctx = cm_get_context(security_state); 1511 assert(ctx != NULL); 1512 1513 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1514 1515 el2_sysregs_context_save_common(el2_sysregs_ctx); 1516 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1517 1518 if (is_feat_mte2_supported()) { 1519 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1520 } 1521 1522 if (is_feat_mpam_supported()) { 1523 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1524 } 1525 1526 if (is_feat_fgt_supported()) { 1527 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1528 } 1529 1530 if (is_feat_fgt2_supported()) { 1531 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1532 } 1533 1534 if (is_feat_ecv_v2_supported()) { 1535 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1536 } 1537 1538 if (is_feat_vhe_supported()) { 1539 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1540 read_contextidr_el2()); 1541 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1542 } 1543 1544 if (is_feat_ras_supported()) { 1545 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1546 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1547 } 1548 1549 if (is_feat_nv2_supported()) { 1550 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1551 } 1552 1553 if (is_feat_trf_supported()) { 1554 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1555 } 1556 1557 if (is_feat_csv2_2_supported()) { 1558 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1559 read_scxtnum_el2()); 1560 } 1561 1562 if (is_feat_hcx_supported()) { 1563 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1564 } 1565 1566 if (is_feat_tcr2_supported()) { 1567 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1568 } 1569 1570 if (is_feat_sxpie_supported()) { 1571 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1572 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1573 } 1574 1575 if (is_feat_sxpoe_supported()) { 1576 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1577 } 1578 1579 if (is_feat_brbe_supported()) { 1580 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1581 } 1582 1583 if (is_feat_s2pie_supported()) { 1584 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1585 } 1586 1587 if (is_feat_gcs_supported()) { 1588 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1589 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1590 } 1591 1592 if (is_feat_sctlr2_supported()) { 1593 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1594 } 1595 } 1596 1597 /******************************************************************************* 1598 * Restore EL2 sysreg context 1599 ******************************************************************************/ 1600 void cm_el2_sysregs_context_restore(uint32_t security_state) 1601 { 1602 cpu_context_t *ctx; 1603 el2_sysregs_t *el2_sysregs_ctx; 1604 1605 ctx = cm_get_context(security_state); 1606 assert(ctx != NULL); 1607 1608 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1609 1610 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1611 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1612 1613 if (is_feat_mte2_supported()) { 1614 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1615 } 1616 1617 if (is_feat_mpam_supported()) { 1618 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1619 } 1620 1621 if (is_feat_fgt_supported()) { 1622 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1623 } 1624 1625 if (is_feat_fgt2_supported()) { 1626 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1627 } 1628 1629 if (is_feat_ecv_v2_supported()) { 1630 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1631 } 1632 1633 if (is_feat_vhe_supported()) { 1634 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1635 contextidr_el2)); 1636 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1637 } 1638 1639 if (is_feat_ras_supported()) { 1640 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1641 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1642 } 1643 1644 if (is_feat_nv2_supported()) { 1645 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1646 } 1647 1648 if (is_feat_trf_supported()) { 1649 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1650 } 1651 1652 if (is_feat_csv2_2_supported()) { 1653 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1654 scxtnum_el2)); 1655 } 1656 1657 if (is_feat_hcx_supported()) { 1658 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1659 } 1660 1661 if (is_feat_tcr2_supported()) { 1662 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1663 } 1664 1665 if (is_feat_sxpie_supported()) { 1666 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1667 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1668 } 1669 1670 if (is_feat_sxpoe_supported()) { 1671 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1672 } 1673 1674 if (is_feat_s2pie_supported()) { 1675 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1676 } 1677 1678 if (is_feat_gcs_supported()) { 1679 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1680 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1681 } 1682 1683 if (is_feat_sctlr2_supported()) { 1684 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1685 } 1686 1687 if (is_feat_brbe_supported()) { 1688 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1689 } 1690 } 1691 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1692 1693 /******************************************************************************* 1694 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1695 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1696 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1697 * cm_prepare_el3_exit function. 1698 ******************************************************************************/ 1699 void cm_prepare_el3_exit_ns(void) 1700 { 1701 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1702 #if ENABLE_ASSERTIONS 1703 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1704 assert(ctx != NULL); 1705 1706 /* Assert that EL2 is used. */ 1707 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1708 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1709 (el_implemented(2U) != EL_IMPL_NONE)); 1710 #endif /* ENABLE_ASSERTIONS */ 1711 1712 /* Restore EL2 sysreg contexts */ 1713 cm_el2_sysregs_context_restore(NON_SECURE); 1714 cm_set_next_eret_context(NON_SECURE); 1715 #else 1716 cm_prepare_el3_exit(NON_SECURE); 1717 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1718 } 1719 1720 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1721 /******************************************************************************* 1722 * The next set of six functions are used by runtime services to save and restore 1723 * EL1 context on the 'cpu_context' structure for the specified security state. 1724 ******************************************************************************/ 1725 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1726 { 1727 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1728 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1729 1730 #if (!ERRATA_SPECULATIVE_AT) 1731 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1732 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1733 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1734 1735 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1736 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1737 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1738 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1739 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1740 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1741 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1742 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1743 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1744 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1745 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1746 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1747 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1748 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1749 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1750 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1751 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1752 1753 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1754 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1755 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1756 1757 if (CTX_INCLUDE_AARCH32_REGS) { 1758 /* Save Aarch32 registers */ 1759 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1760 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1761 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1762 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1763 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1764 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1765 } 1766 1767 /* Save counter-timer kernel control register */ 1768 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1769 #if NS_TIMER_SWITCH 1770 /* Save NS Timer registers */ 1771 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1772 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1773 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1774 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1775 #endif 1776 1777 if (is_feat_mte2_supported()) { 1778 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1779 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1780 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1781 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1782 } 1783 1784 if (is_feat_ras_supported()) { 1785 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1786 } 1787 1788 if (is_feat_s1pie_supported()) { 1789 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1790 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1791 } 1792 1793 if (is_feat_s1poe_supported()) { 1794 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1795 } 1796 1797 if (is_feat_s2poe_supported()) { 1798 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1799 } 1800 1801 if (is_feat_tcr2_supported()) { 1802 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1803 } 1804 1805 if (is_feat_trf_supported()) { 1806 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1807 } 1808 1809 if (is_feat_csv2_2_supported()) { 1810 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1811 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1812 } 1813 1814 if (is_feat_gcs_supported()) { 1815 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1816 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1817 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1818 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1819 } 1820 1821 if (is_feat_the_supported()) { 1822 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1823 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1824 } 1825 1826 if (is_feat_sctlr2_supported()) { 1827 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1828 } 1829 1830 if (is_feat_ls64_accdata_supported()) { 1831 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1832 } 1833 } 1834 1835 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1836 { 1837 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1838 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1839 1840 #if (!ERRATA_SPECULATIVE_AT) 1841 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1842 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1843 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1844 1845 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1846 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1847 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1848 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1849 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1850 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1851 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1852 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1853 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1854 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1855 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1856 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1857 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1858 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1859 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1860 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1861 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1862 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1863 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1864 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1865 1866 if (CTX_INCLUDE_AARCH32_REGS) { 1867 /* Restore Aarch32 registers */ 1868 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1869 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1870 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1871 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1872 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1873 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1874 } 1875 1876 /* Restore counter-timer kernel control register */ 1877 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1878 #if NS_TIMER_SWITCH 1879 /* Restore NS Timer registers */ 1880 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1881 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1882 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1883 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1884 #endif 1885 1886 if (is_feat_mte2_supported()) { 1887 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1888 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1889 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1890 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1891 } 1892 1893 if (is_feat_ras_supported()) { 1894 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1895 } 1896 1897 if (is_feat_s1pie_supported()) { 1898 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1899 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1900 } 1901 1902 if (is_feat_s1poe_supported()) { 1903 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1904 } 1905 1906 if (is_feat_s2poe_supported()) { 1907 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1908 } 1909 1910 if (is_feat_tcr2_supported()) { 1911 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1912 } 1913 1914 if (is_feat_trf_supported()) { 1915 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1916 } 1917 1918 if (is_feat_csv2_2_supported()) { 1919 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1920 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1921 } 1922 1923 if (is_feat_gcs_supported()) { 1924 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1925 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1926 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1927 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1928 } 1929 1930 if (is_feat_the_supported()) { 1931 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1932 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1933 } 1934 1935 if (is_feat_sctlr2_supported()) { 1936 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1937 } 1938 1939 if (is_feat_ls64_accdata_supported()) { 1940 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1941 } 1942 } 1943 1944 /******************************************************************************* 1945 * The next couple of functions are used by runtime services to save and restore 1946 * EL1 context on the 'cpu_context' structure for the specified security state. 1947 ******************************************************************************/ 1948 void cm_el1_sysregs_context_save(uint32_t security_state) 1949 { 1950 cpu_context_t *ctx; 1951 1952 ctx = cm_get_context(security_state); 1953 assert(ctx != NULL); 1954 1955 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1956 1957 #if IMAGE_BL31 1958 if (security_state == SECURE) { 1959 PUBLISH_EVENT(cm_exited_secure_world); 1960 } else { 1961 PUBLISH_EVENT(cm_exited_normal_world); 1962 } 1963 #endif 1964 } 1965 1966 void cm_el1_sysregs_context_restore(uint32_t security_state) 1967 { 1968 cpu_context_t *ctx; 1969 1970 ctx = cm_get_context(security_state); 1971 assert(ctx != NULL); 1972 1973 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1974 1975 #if IMAGE_BL31 1976 if (security_state == SECURE) { 1977 PUBLISH_EVENT(cm_entering_secure_world); 1978 } else { 1979 PUBLISH_EVENT(cm_entering_normal_world); 1980 } 1981 #endif 1982 } 1983 1984 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1985 1986 /******************************************************************************* 1987 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1988 * given security state with the given entrypoint 1989 ******************************************************************************/ 1990 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1991 { 1992 cpu_context_t *ctx; 1993 el3_state_t *state; 1994 1995 ctx = cm_get_context(security_state); 1996 assert(ctx != NULL); 1997 1998 /* Populate EL3 state so that ERET jumps to the correct entry */ 1999 state = get_el3state_ctx(ctx); 2000 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2001 } 2002 2003 /******************************************************************************* 2004 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2005 * pertaining to the given security state 2006 ******************************************************************************/ 2007 void cm_set_elr_spsr_el3(uint32_t security_state, 2008 uintptr_t entrypoint, uint32_t spsr) 2009 { 2010 cpu_context_t *ctx; 2011 el3_state_t *state; 2012 2013 ctx = cm_get_context(security_state); 2014 assert(ctx != NULL); 2015 2016 /* Populate EL3 state so that ERET jumps to the correct entry */ 2017 state = get_el3state_ctx(ctx); 2018 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2019 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2020 } 2021 2022 /******************************************************************************* 2023 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2024 * pertaining to the given security state using the value and bit position 2025 * specified in the parameters. It preserves all other bits. 2026 ******************************************************************************/ 2027 void cm_write_scr_el3_bit(uint32_t security_state, 2028 uint32_t bit_pos, 2029 uint32_t value) 2030 { 2031 cpu_context_t *ctx; 2032 el3_state_t *state; 2033 u_register_t scr_el3; 2034 2035 ctx = cm_get_context(security_state); 2036 assert(ctx != NULL); 2037 2038 /* Ensure that the bit position is a valid one */ 2039 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2040 2041 /* Ensure that the 'value' is only a bit wide */ 2042 assert(value <= 1U); 2043 2044 /* 2045 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2046 * and set it to its new value. 2047 */ 2048 state = get_el3state_ctx(ctx); 2049 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2050 scr_el3 &= ~(1UL << bit_pos); 2051 scr_el3 |= (u_register_t)value << bit_pos; 2052 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2053 } 2054 2055 /******************************************************************************* 2056 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2057 * given security state. 2058 ******************************************************************************/ 2059 u_register_t cm_get_scr_el3(uint32_t security_state) 2060 { 2061 const cpu_context_t *ctx; 2062 const el3_state_t *state; 2063 2064 ctx = cm_get_context(security_state); 2065 assert(ctx != NULL); 2066 2067 /* Populate EL3 state so that ERET jumps to the correct entry */ 2068 state = get_el3state_ctx(ctx); 2069 return read_ctx_reg(state, CTX_SCR_EL3); 2070 } 2071 2072 /******************************************************************************* 2073 * This function is used to program the context that's used for exception 2074 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2075 * the required security state 2076 ******************************************************************************/ 2077 void cm_set_next_eret_context(uint32_t security_state) 2078 { 2079 cpu_context_t *ctx; 2080 2081 ctx = cm_get_context(security_state); 2082 assert(ctx != NULL); 2083 2084 cm_set_next_context(ctx); 2085 } 2086