1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/fpmr.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 } 153 154 #if ENABLE_RME && IMAGE_BL31 155 /****************************************************************************** 156 * This function performs initializations that are specific to REALM state 157 * and updates the cpu context specified by 'ctx'. 158 * 159 * NOTE: any changes to this function must be verified by an RMMD maintainer. 160 *****************************************************************************/ 161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 162 { 163 u_register_t scr_el3; 164 el3_state_t *state; 165 el2_sysregs_t *el2_ctx; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 el2_ctx = get_el2_sysregs_ctx(ctx); 170 171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 172 173 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 174 175 /* CSV2 version 2 and above */ 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 if (is_feat_sctlr2_supported()) { 182 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 183 * SCTLR2_ELx registers. 184 */ 185 scr_el3 |= SCR_SCTLR2En_BIT; 186 } 187 188 if (is_feat_d128_supported()) { 189 /* 190 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 191 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 192 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 193 */ 194 scr_el3 |= SCR_D128En_BIT; 195 } 196 197 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 198 199 if (is_feat_fgt2_supported()) { 200 fgt2_enable(ctx); 201 } 202 203 if (is_feat_debugv8p9_supported()) { 204 debugv8p9_extended_bp_wp_enable(ctx); 205 } 206 207 if (is_feat_brbe_supported()) { 208 brbe_enable(ctx); 209 } 210 211 /* 212 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 213 */ 214 if (is_feat_sme_supported()) { 215 sme_enable(ctx); 216 } 217 218 if (is_feat_spe_supported()) { 219 spe_disable_realm(ctx); 220 } 221 222 if (is_feat_trbe_supported()) { 223 trbe_disable_realm(ctx); 224 } 225 } 226 #endif /* ENABLE_RME && IMAGE_BL31 */ 227 228 /****************************************************************************** 229 * This function performs initializations that are specific to NON-SECURE state 230 * and updates the cpu context specified by 'ctx'. 231 *****************************************************************************/ 232 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 233 { 234 u_register_t scr_el3; 235 el3_state_t *state; 236 237 state = get_el3state_ctx(ctx); 238 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 239 240 /* SCR_NS: Set the NS bit */ 241 scr_el3 |= SCR_NS_BIT; 242 243 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 244 if (is_feat_mte2_supported()) { 245 scr_el3 |= SCR_ATA_BIT; 246 } 247 248 /* 249 * Pointer Authentication feature, if present, is always enabled by 250 * default for Non secure lower exception levels. We do not have an 251 * explicit flag to set it. To prevent the leakage between the worlds 252 * during world switch, we enable it only for the non-secure world. 253 * 254 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 255 * exception levels of secure and realm worlds. 256 * 257 * If the Secure/realm world wants to use pointer authentication, 258 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 259 * it will be enabled globally for all the contexts. 260 * 261 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 262 * other than EL3 263 * 264 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 265 * than EL3 266 */ 267 if (!is_ctx_pauth_supported()) { 268 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 269 } 270 271 #if HANDLE_EA_EL3_FIRST_NS 272 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 273 scr_el3 |= SCR_EA_BIT; 274 #endif 275 276 #if RAS_TRAP_NS_ERR_REC_ACCESS 277 /* 278 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 279 * and RAS ERX registers from EL1 and EL2(from any security state) 280 * are trapped to EL3. 281 * Set here to trap only for NS EL1/EL2 282 */ 283 scr_el3 |= SCR_TERR_BIT; 284 #endif 285 286 /* CSV2 version 2 and above */ 287 if (is_feat_csv2_2_supported()) { 288 /* Enable access to the SCXTNUM_ELx registers. */ 289 scr_el3 |= SCR_EnSCXT_BIT; 290 } 291 292 #ifdef IMAGE_BL31 293 /* 294 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 295 * indicated by the interrupt routing model for BL31. 296 */ 297 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 298 #endif 299 300 if (is_feat_the_supported()) { 301 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 302 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 303 */ 304 scr_el3 |= SCR_RCWMASKEn_BIT; 305 } 306 307 if (is_feat_sctlr2_supported()) { 308 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 309 * SCTLR2_ELx registers. 310 */ 311 scr_el3 |= SCR_SCTLR2En_BIT; 312 } 313 314 if (is_feat_d128_supported()) { 315 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 316 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 317 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 318 */ 319 scr_el3 |= SCR_D128En_BIT; 320 } 321 322 if (is_feat_fpmr_supported()) { 323 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 324 * register. 325 */ 326 scr_el3 |= SCR_EnFPM_BIT; 327 } 328 329 if (is_feat_aie_supported()) { 330 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 331 * system registers from NS world. 332 */ 333 scr_el3 |= SCR_AIEn_BIT; 334 } 335 336 if (is_feat_pfar_supported()) { 337 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR 338 * system registers from NS world. 339 */ 340 scr_el3 |= SCR_PFAREn_BIT; 341 } 342 343 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 344 345 /* Initialize EL2 context registers */ 346 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 347 if (is_feat_hcx_supported()) { 348 /* 349 * Initialize register HCRX_EL2 with its init value. 350 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 351 * chance that this can lead to unexpected behavior in lower 352 * ELs that have not been updated since the introduction of 353 * this feature if not properly initialized, especially when 354 * it comes to those bits that enable/disable traps. 355 */ 356 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 357 HCRX_EL2_INIT_VAL); 358 } 359 360 if (is_feat_fgt_supported()) { 361 /* 362 * Initialize HFG*_EL2 registers with a default value so legacy 363 * systems unaware of FEAT_FGT do not get trapped due to their lack 364 * of initialization for this feature. 365 */ 366 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 367 HFGITR_EL2_INIT_VAL); 368 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 369 HFGRTR_EL2_INIT_VAL); 370 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 371 HFGWTR_EL2_INIT_VAL); 372 } 373 #else 374 /* Initialize EL1 context registers */ 375 setup_el1_context(ctx, ep); 376 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 377 378 manage_extensions_nonsecure(ctx); 379 } 380 381 /******************************************************************************* 382 * The following function performs initialization of the cpu_context 'ctx' 383 * for first use that is common to all security states, and sets the 384 * initial entrypoint state as specified by the entry_point_info structure. 385 * 386 * The EE and ST attributes are used to configure the endianness and secure 387 * timer availability for the new execution context. 388 ******************************************************************************/ 389 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 390 { 391 u_register_t scr_el3; 392 u_register_t mdcr_el3; 393 el3_state_t *state; 394 gp_regs_t *gp_regs; 395 396 state = get_el3state_ctx(ctx); 397 398 /* Clear any residual register values from the context */ 399 zeromem(ctx, sizeof(*ctx)); 400 401 /* 402 * The lower-EL context is zeroed so that no stale values leak to a world. 403 * It is assumed that an all-zero lower-EL context is good enough for it 404 * to boot correctly. However, there are very few registers where this 405 * is not true and some values need to be recreated. 406 */ 407 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 408 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 409 410 /* 411 * These bits are set in the gicv3 driver. Losing them (especially the 412 * SRE bit) is problematic for all worlds. Henceforth recreate them. 413 */ 414 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 415 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 416 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 417 418 /* 419 * The actlr_el2 register can be initialized in platform's reset handler 420 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 421 */ 422 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 423 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 424 425 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 426 scr_el3 = SCR_RESET_VAL; 427 428 /* 429 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 430 * EL2, EL1 and EL0 are not trapped to EL3. 431 * 432 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 433 * EL2, EL1 and EL0 are not trapped to EL3. 434 * 435 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 436 * both Security states and both Execution states. 437 * 438 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 439 * Non-secure memory. 440 */ 441 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 442 443 scr_el3 |= SCR_SIF_BIT; 444 445 /* 446 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 447 * Exception level as specified by SPSR. 448 */ 449 if (GET_RW(ep->spsr) == MODE_RW_64) { 450 scr_el3 |= SCR_RW_BIT; 451 } 452 453 /* 454 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 455 * Secure timer registers to EL3, from AArch64 state only, if specified 456 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 457 * bit always behaves as 1 (i.e. secure physical timer register access 458 * is not trapped) 459 */ 460 if (EP_GET_ST(ep->h.attr) != 0U) { 461 scr_el3 |= SCR_ST_BIT; 462 } 463 464 /* 465 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 466 * SCR_EL3.HXEn. 467 */ 468 if (is_feat_hcx_supported()) { 469 scr_el3 |= SCR_HXEn_BIT; 470 } 471 472 /* 473 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 474 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 475 * SCR_EL3.EnAS0. 476 */ 477 if (is_feat_ls64_accdata_supported()) { 478 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 479 } 480 481 /* 482 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 483 * registers are trapped to EL3. 484 */ 485 if (is_feat_rng_trap_supported()) { 486 scr_el3 |= SCR_TRNDR_BIT; 487 } 488 489 #if FAULT_INJECTION_SUPPORT 490 /* Enable fault injection from lower ELs */ 491 scr_el3 |= SCR_FIEN_BIT; 492 #endif 493 494 /* 495 * Enable Pointer Authentication globally for all the worlds. 496 * 497 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 498 * other than EL3 499 * 500 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 501 * than EL3 502 */ 503 if (is_ctx_pauth_supported()) { 504 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 505 } 506 507 /* 508 * SCR_EL3.PIEN: Enable permission indirection and overlay 509 * registers for AArch64 if present. 510 */ 511 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 512 scr_el3 |= SCR_PIEN_BIT; 513 } 514 515 /* 516 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 517 */ 518 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 519 scr_el3 |= SCR_GCSEn_BIT; 520 } 521 522 /* 523 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 524 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 525 * next mode is Hyp. 526 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 527 * same conditions as HVC instructions and when the processor supports 528 * ARMv8.6-FGT. 529 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 530 * CNTPOFF_EL2 register under the same conditions as HVC instructions 531 * and when the processor supports ECV. 532 */ 533 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 534 || ((GET_RW(ep->spsr) != MODE_RW_64) 535 && (GET_M32(ep->spsr) == MODE32_hyp))) { 536 scr_el3 |= SCR_HCE_BIT; 537 538 if (is_feat_fgt_supported()) { 539 scr_el3 |= SCR_FGTEN_BIT; 540 } 541 542 if (is_feat_ecv_supported()) { 543 scr_el3 |= SCR_ECVEN_BIT; 544 } 545 } 546 547 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 548 if (is_feat_twed_supported()) { 549 /* Set delay in SCR_EL3 */ 550 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 551 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 552 << SCR_TWEDEL_SHIFT); 553 554 /* Enable WFE delay */ 555 scr_el3 |= SCR_TWEDEn_BIT; 556 } 557 558 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 559 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 560 if (is_feat_sel2_supported()) { 561 scr_el3 |= SCR_EEL2_BIT; 562 } 563 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 564 565 if (is_feat_mec_supported()) { 566 scr_el3 |= SCR_MECEn_BIT; 567 } 568 569 /* 570 * Populate EL3 state so that we've the right context 571 * before doing ERET 572 */ 573 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 574 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 575 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 576 577 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 578 mdcr_el3 = MDCR_EL3_RESET_VAL; 579 580 /* --------------------------------------------------------------------- 581 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 582 * Some fields are architecturally UNKNOWN on reset. 583 * 584 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 585 * Debug exceptions, other than Breakpoint Instruction exceptions, are 586 * disabled from all ELs in Secure state. 587 * 588 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 589 * privileged debug from S-EL1. 590 * 591 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 592 * access to the powerdown debug registers do not trap to EL3. 593 * 594 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 595 * debug registers, other than those registers that are controlled by 596 * MDCR_EL3.TDOSA. 597 */ 598 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 599 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 600 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 601 602 #if IMAGE_BL31 603 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 604 if (is_feat_trf_supported()) { 605 trf_enable(ctx); 606 } 607 608 if (is_feat_tcr2_supported()) { 609 tcr2_enable(ctx); 610 } 611 612 pmuv3_enable(ctx); 613 614 #if CTX_INCLUDE_EL2_REGS 615 /* 616 * Initialize SCTLR_EL2 context register with reset value. 617 */ 618 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 619 #endif /* CTX_INCLUDE_EL2_REGS */ 620 #endif /* IMAGE_BL31 */ 621 622 /* 623 * Store the X0-X7 value from the entrypoint into the context 624 * Use memcpy as we are in control of the layout of the structures 625 */ 626 gp_regs = get_gpregs_ctx(ctx); 627 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 628 } 629 630 /******************************************************************************* 631 * Context management library initialization routine. This library is used by 632 * runtime services to share pointers to 'cpu_context' structures for secure 633 * non-secure and realm states. Management of the structures and their associated 634 * memory is not done by the context management library e.g. the PSCI service 635 * manages the cpu context used for entry from and exit to the non-secure state. 636 * The Secure payload dispatcher service manages the context(s) corresponding to 637 * the secure state. It also uses this library to get access to the non-secure 638 * state cpu context pointers. 639 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 640 * which will be used for programming an entry into a lower EL. The same context 641 * will be used to save state upon exception entry from that EL. 642 ******************************************************************************/ 643 void __init cm_init(void) 644 { 645 /* 646 * The context management library has only global data to initialize, but 647 * that will be done when the BSS is zeroed out. 648 */ 649 } 650 651 /******************************************************************************* 652 * This is the high-level function used to initialize the cpu_context 'ctx' for 653 * first use. It performs initializations that are common to all security states 654 * and initializations specific to the security state specified in 'ep' 655 ******************************************************************************/ 656 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 657 { 658 size_t security_state; 659 660 assert(ctx != NULL); 661 662 /* 663 * Perform initializations that are common 664 * to all security states 665 */ 666 setup_context_common(ctx, ep); 667 668 security_state = GET_SECURITY_STATE(ep->h.attr); 669 670 /* Perform security state specific initializations */ 671 switch (security_state) { 672 case SECURE: 673 setup_secure_context(ctx, ep); 674 break; 675 #if ENABLE_RME && IMAGE_BL31 676 case REALM: 677 setup_realm_context(ctx, ep); 678 break; 679 #endif 680 case NON_SECURE: 681 setup_ns_context(ctx, ep); 682 break; 683 default: 684 ERROR("Invalid security state\n"); 685 panic(); 686 break; 687 } 688 } 689 690 /******************************************************************************* 691 * Enable architecture extensions for EL3 execution. This function only updates 692 * registers in-place which are expected to either never change or be 693 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 694 ******************************************************************************/ 695 #if IMAGE_BL31 696 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 697 { 698 if (is_feat_pauth_supported()) { 699 pauth_init_enable_el3(); 700 } 701 702 if (is_feat_sve_supported()) { 703 sve_init_el3(); 704 } 705 706 if (is_feat_amu_supported()) { 707 amu_init_el3(my_idx); 708 } 709 710 if (is_feat_sme_supported()) { 711 sme_init_el3(); 712 } 713 714 if (is_feat_fgwte3_supported()) { 715 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 716 } 717 718 if (is_feat_mpam_supported()) { 719 mpam_init_el3(); 720 } 721 722 if (is_feat_cpa2_supported()) { 723 cpa2_enable_el3(); 724 } 725 726 pmuv3_init_el3(); 727 } 728 729 /****************************************************************************** 730 * Function to initialise the registers with the RESET values in the context 731 * memory, which are maintained per world. 732 ******************************************************************************/ 733 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 734 { 735 /* 736 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 737 * 738 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 739 * by Advanced SIMD, floating-point or SVE instructions (if 740 * implemented) do not trap to EL3. 741 * 742 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 743 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 744 */ 745 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 746 747 per_world_ctx->ctx_cptr_el3 = cptr_el3; 748 749 /* 750 * Initialize MPAM3_EL3 to its default reset value 751 * 752 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 753 * all lower ELn MPAM3_EL3 register access to, trap to EL3 754 */ 755 756 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 757 } 758 759 /******************************************************************************* 760 * Initialise per_world_context for Non-Secure world. 761 * This function enables the architecture extensions, which have same value 762 * across the cores for the non-secure world. 763 ******************************************************************************/ 764 static void manage_extensions_nonsecure_per_world(void) 765 { 766 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 767 768 if (is_feat_sme_supported()) { 769 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 770 } 771 772 if (is_feat_sve_supported()) { 773 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 774 } 775 776 if (is_feat_amu_supported()) { 777 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 778 } 779 780 if (is_feat_sys_reg_trace_supported()) { 781 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 782 } 783 784 if (is_feat_mpam_supported()) { 785 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 786 } 787 788 if (is_feat_fpmr_supported()) { 789 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 790 } 791 } 792 793 /******************************************************************************* 794 * Initialise per_world_context for Secure world. 795 * This function enables the architecture extensions, which have same value 796 * across the cores for the secure world. 797 ******************************************************************************/ 798 static void manage_extensions_secure_per_world(void) 799 { 800 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 801 802 if (is_feat_sme_supported()) { 803 804 if (ENABLE_SME_FOR_SWD) { 805 /* 806 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 807 * SME, SVE, and FPU/SIMD context properly managed. 808 */ 809 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 810 } else { 811 /* 812 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 813 * world can safely use the associated registers. 814 */ 815 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 816 } 817 } 818 if (is_feat_sve_supported()) { 819 if (ENABLE_SVE_FOR_SWD) { 820 /* 821 * Enable SVE and FPU in secure context, SPM must ensure 822 * that the SVE and FPU register contexts are properly managed. 823 */ 824 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 825 } else { 826 /* 827 * Disable SVE and FPU in secure context so non-secure world 828 * can safely use them. 829 */ 830 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 831 } 832 } 833 834 /* NS can access this but Secure shouldn't */ 835 if (is_feat_sys_reg_trace_supported()) { 836 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 837 } 838 } 839 840 static void manage_extensions_realm_per_world(void) 841 { 842 #if ENABLE_RME 843 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 844 845 if (is_feat_sve_supported()) { 846 /* 847 * Enable SVE and FPU in realm context when it is enabled for NS. 848 * Realm manager must ensure that the SVE and FPU register 849 * contexts are properly managed. 850 */ 851 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 852 } 853 854 /* NS can access this but Realm shouldn't */ 855 if (is_feat_sys_reg_trace_supported()) { 856 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 857 } 858 859 /* 860 * If SME/SME2 is supported and enabled for NS world, then disable trapping 861 * of SME instructions for Realm world. RMM will save/restore required 862 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 863 */ 864 if (is_feat_sme_supported()) { 865 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 866 } 867 868 /* 869 * If FEAT_MPAM is supported and enabled, then disable trapping access 870 * to the MPAM registers for Realm world. Instead, RMM will configure 871 * the access to be trapped by itself so it can inject undefined aborts 872 * back to the Realm. 873 */ 874 if (is_feat_mpam_supported()) { 875 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 876 } 877 #endif /* ENABLE_RME */ 878 } 879 880 void cm_manage_extensions_per_world(void) 881 { 882 manage_extensions_nonsecure_per_world(); 883 manage_extensions_secure_per_world(); 884 manage_extensions_realm_per_world(); 885 } 886 #endif /* IMAGE_BL31 */ 887 888 /******************************************************************************* 889 * Enable architecture extensions on first entry to Non-secure world. 890 ******************************************************************************/ 891 static void manage_extensions_nonsecure(cpu_context_t *ctx) 892 { 893 #if IMAGE_BL31 894 /* NOTE: registers are not context switched */ 895 if (is_feat_amu_supported()) { 896 amu_enable(ctx); 897 } 898 899 if (is_feat_sme_supported()) { 900 sme_enable(ctx); 901 } 902 903 if (is_feat_fgt2_supported()) { 904 fgt2_enable(ctx); 905 } 906 907 if (is_feat_debugv8p9_supported()) { 908 debugv8p9_extended_bp_wp_enable(ctx); 909 } 910 911 if (is_feat_spe_supported()) { 912 spe_enable_ns(ctx); 913 } 914 915 if (is_feat_trbe_supported()) { 916 if (check_if_trbe_disable_affected_core()) { 917 trbe_disable_ns(ctx); 918 } else { 919 trbe_enable_ns(ctx); 920 } 921 } 922 923 if (is_feat_brbe_supported()) { 924 brbe_enable(ctx); 925 } 926 #endif /* IMAGE_BL31 */ 927 } 928 929 #if INIT_UNUSED_NS_EL2 930 /******************************************************************************* 931 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 932 * world when EL2 is empty and unused. 933 ******************************************************************************/ 934 static void manage_extensions_nonsecure_el2_unused(void) 935 { 936 #if IMAGE_BL31 937 if (is_feat_spe_supported()) { 938 spe_init_el2_unused(); 939 } 940 941 if (is_feat_amu_supported()) { 942 amu_init_el2_unused(); 943 } 944 945 if (is_feat_mpam_supported()) { 946 mpam_init_el2_unused(); 947 } 948 949 if (is_feat_trbe_supported()) { 950 trbe_init_el2_unused(); 951 } 952 953 if (is_feat_sys_reg_trace_supported()) { 954 sys_reg_trace_init_el2_unused(); 955 } 956 957 if (is_feat_trf_supported()) { 958 trf_init_el2_unused(); 959 } 960 961 pmuv3_init_el2_unused(); 962 963 if (is_feat_sve_supported()) { 964 sve_init_el2_unused(); 965 } 966 967 if (is_feat_sme_supported()) { 968 sme_init_el2_unused(); 969 } 970 971 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 972 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 973 } 974 975 if (is_feat_pauth_supported()) { 976 pauth_enable_el2(); 977 } 978 #endif /* IMAGE_BL31 */ 979 } 980 #endif /* INIT_UNUSED_NS_EL2 */ 981 982 /******************************************************************************* 983 * Enable architecture extensions on first entry to Secure world. 984 ******************************************************************************/ 985 static void manage_extensions_secure(cpu_context_t *ctx) 986 { 987 #if IMAGE_BL31 988 if (is_feat_sme_supported()) { 989 if (ENABLE_SME_FOR_SWD) { 990 /* 991 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 992 * must ensure SME, SVE, and FPU/SIMD context properly managed. 993 */ 994 sme_init_el3(); 995 sme_enable(ctx); 996 } else { 997 /* 998 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 999 * world can safely use the associated registers. 1000 */ 1001 sme_disable(ctx); 1002 } 1003 } 1004 1005 if (is_feat_spe_supported()) { 1006 spe_disable_secure(ctx); 1007 } 1008 1009 if (is_feat_trbe_supported()) { 1010 trbe_disable_secure(ctx); 1011 } 1012 #endif /* IMAGE_BL31 */ 1013 } 1014 1015 /******************************************************************************* 1016 * The following function initializes the cpu_context for the current CPU 1017 * for first use, and sets the initial entrypoint state as specified by the 1018 * entry_point_info structure. 1019 ******************************************************************************/ 1020 void cm_init_my_context(const entry_point_info_t *ep) 1021 { 1022 cpu_context_t *ctx; 1023 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1024 cm_setup_context(ctx, ep); 1025 } 1026 1027 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1028 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1029 { 1030 #if INIT_UNUSED_NS_EL2 1031 u_register_t hcr_el2 = HCR_RESET_VAL; 1032 u_register_t mdcr_el2; 1033 u_register_t scr_el3; 1034 1035 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1036 1037 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1038 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1039 hcr_el2 |= HCR_RW_BIT; 1040 } 1041 1042 write_hcr_el2(hcr_el2); 1043 1044 /* 1045 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1046 * All fields have architecturally UNKNOWN reset values. 1047 */ 1048 write_cptr_el2(CPTR_EL2_RESET_VAL); 1049 1050 /* 1051 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1052 * reset and are set to zero except for field(s) listed below. 1053 * 1054 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1055 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1056 * 1057 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1058 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1059 */ 1060 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1061 1062 /* 1063 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1064 * UNKNOWN value. 1065 */ 1066 write_cntvoff_el2(0); 1067 1068 /* 1069 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1070 * respectively. 1071 */ 1072 write_vpidr_el2(read_midr_el1()); 1073 write_vmpidr_el2(read_mpidr_el1()); 1074 1075 /* 1076 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1077 * 1078 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1079 * translation is disabled, cache maintenance operations depend on the 1080 * VMID. 1081 * 1082 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1083 * disabled. 1084 */ 1085 write_vttbr_el2(VTTBR_RESET_VAL & 1086 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1087 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1088 1089 /* 1090 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1091 * Some fields are architecturally UNKNOWN on reset. 1092 * 1093 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1094 * register accesses to the Debug ROM registers are not trapped to EL2. 1095 * 1096 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1097 * accesses to the powerdown debug registers are not trapped to EL2. 1098 * 1099 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1100 * debug registers do not trap to EL2. 1101 * 1102 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1103 * EL2. 1104 */ 1105 mdcr_el2 = MDCR_EL2_RESET_VAL & 1106 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1107 MDCR_EL2_TDE_BIT); 1108 1109 write_mdcr_el2(mdcr_el2); 1110 1111 /* 1112 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1113 * 1114 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1115 * EL1 accesses to System registers do not trap to EL2. 1116 */ 1117 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1118 1119 /* 1120 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1121 * reset. 1122 * 1123 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1124 * and prevent timer interrupts. 1125 */ 1126 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1127 1128 manage_extensions_nonsecure_el2_unused(); 1129 #endif /* INIT_UNUSED_NS_EL2 */ 1130 } 1131 1132 /******************************************************************************* 1133 * Prepare the CPU system registers for first entry into realm, secure, or 1134 * normal world. 1135 * 1136 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1137 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1138 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1139 * For all entries, the EL1 registers are initialized from the cpu_context 1140 ******************************************************************************/ 1141 void cm_prepare_el3_exit(size_t security_state) 1142 { 1143 u_register_t sctlr_el2, scr_el3; 1144 cpu_context_t *ctx = cm_get_context(security_state); 1145 1146 assert(ctx != NULL); 1147 1148 if (security_state == NON_SECURE) { 1149 uint64_t el2_implemented = el_implemented(2); 1150 1151 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1152 CTX_SCR_EL3); 1153 1154 if (el2_implemented != EL_IMPL_NONE) { 1155 1156 /* 1157 * If context is not being used for EL2, initialize 1158 * HCRX_EL2 with its init value here. 1159 */ 1160 if (is_feat_hcx_supported()) { 1161 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1162 } 1163 1164 /* 1165 * Initialize Fine-grained trap registers introduced 1166 * by FEAT_FGT so all traps are initially disabled when 1167 * switching to EL2 or a lower EL, preventing undesired 1168 * behavior. 1169 */ 1170 if (is_feat_fgt_supported()) { 1171 /* 1172 * Initialize HFG*_EL2 registers with a default 1173 * value so legacy systems unaware of FEAT_FGT 1174 * do not get trapped due to their lack of 1175 * initialization for this feature. 1176 */ 1177 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1178 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1179 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1180 } 1181 1182 /* Condition to ensure EL2 is being used. */ 1183 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1184 /* Initialize SCTLR_EL2 register with reset value. */ 1185 sctlr_el2 = SCTLR_EL2_RES1; 1186 1187 /* 1188 * If workaround of errata 764081 for Cortex-A75 1189 * is used then set SCTLR_EL2.IESB to enable 1190 * Implicit Error Synchronization Barrier. 1191 */ 1192 if (errata_a75_764081_applies()) { 1193 sctlr_el2 |= SCTLR_IESB_BIT; 1194 } 1195 1196 write_sctlr_el2(sctlr_el2); 1197 } else { 1198 /* 1199 * (scr_el3 & SCR_HCE_BIT==0) 1200 * EL2 implemented but unused. 1201 */ 1202 init_nonsecure_el2_unused(ctx); 1203 } 1204 } 1205 1206 if (is_feat_fgwte3_supported()) { 1207 /* 1208 * TCR_EL3 and ACTLR_EL3 could be overwritten 1209 * by platforms and hence is locked a bit late. 1210 */ 1211 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1212 } 1213 } 1214 #if (!CTX_INCLUDE_EL2_REGS) 1215 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1216 cm_el1_sysregs_context_restore(security_state); 1217 #endif 1218 cm_set_next_eret_context(security_state); 1219 } 1220 1221 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1222 1223 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1224 { 1225 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1226 if (is_feat_amu_supported()) { 1227 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1228 } 1229 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1230 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1231 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1232 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1233 } 1234 1235 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1236 { 1237 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1238 if (is_feat_amu_supported()) { 1239 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1240 } 1241 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1242 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1243 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1244 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1245 } 1246 1247 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1248 { 1249 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1250 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1251 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1252 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1253 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1254 } 1255 1256 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1257 { 1258 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1259 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1260 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1261 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1262 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1263 } 1264 1265 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1266 { 1267 u_register_t mpam_idr = read_mpamidr_el1(); 1268 1269 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1270 1271 /* 1272 * The context registers that we intend to save would be part of the 1273 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1274 */ 1275 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1276 return; 1277 } 1278 1279 /* 1280 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1281 * MPAMIDR_HAS_HCR_BIT == 1. 1282 */ 1283 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1284 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1285 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1286 1287 /* 1288 * The number of MPAMVPM registers is implementation defined, their 1289 * number is stored in the MPAMIDR_EL1 register. 1290 */ 1291 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1292 case 7: 1293 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1294 __fallthrough; 1295 case 6: 1296 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1297 __fallthrough; 1298 case 5: 1299 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1300 __fallthrough; 1301 case 4: 1302 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1303 __fallthrough; 1304 case 3: 1305 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1306 __fallthrough; 1307 case 2: 1308 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1309 __fallthrough; 1310 case 1: 1311 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1312 break; 1313 } 1314 } 1315 1316 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1317 { 1318 u_register_t mpam_idr = read_mpamidr_el1(); 1319 1320 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1321 1322 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1323 return; 1324 } 1325 1326 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1327 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1328 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1329 1330 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1331 case 7: 1332 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1333 __fallthrough; 1334 case 6: 1335 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1336 __fallthrough; 1337 case 5: 1338 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1339 __fallthrough; 1340 case 4: 1341 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1342 __fallthrough; 1343 case 3: 1344 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1345 __fallthrough; 1346 case 2: 1347 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1348 __fallthrough; 1349 case 1: 1350 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1351 break; 1352 } 1353 } 1354 1355 /* --------------------------------------------------------------------------- 1356 * The following registers are not added: 1357 * ICH_AP0R<n>_EL2 1358 * ICH_AP1R<n>_EL2 1359 * ICH_LR<n>_EL2 1360 * 1361 * NOTE: For a system with S-EL2 present but not enabled, accessing 1362 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1363 * SCR_EL3.NS = 1 before accessing this register. 1364 * --------------------------------------------------------------------------- 1365 */ 1366 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1367 { 1368 u_register_t scr_el3 = read_scr_el3(); 1369 1370 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1371 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1372 #else 1373 write_scr_el3(scr_el3 | SCR_NS_BIT); 1374 isb(); 1375 1376 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1377 1378 write_scr_el3(scr_el3); 1379 isb(); 1380 #endif 1381 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1382 1383 if (errata_ich_vmcr_el2_applies()) { 1384 if (security_state == SECURE) { 1385 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1386 } else { 1387 write_scr_el3(scr_el3 | SCR_NS_BIT); 1388 } 1389 isb(); 1390 } 1391 1392 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1393 1394 if (errata_ich_vmcr_el2_applies()) { 1395 write_scr_el3(scr_el3); 1396 isb(); 1397 } 1398 } 1399 1400 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1401 { 1402 u_register_t scr_el3 = read_scr_el3(); 1403 1404 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1405 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1406 #else 1407 write_scr_el3(scr_el3 | SCR_NS_BIT); 1408 isb(); 1409 1410 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1411 1412 write_scr_el3(scr_el3); 1413 isb(); 1414 #endif 1415 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1416 1417 if (errata_ich_vmcr_el2_applies()) { 1418 if (security_state == SECURE) { 1419 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1420 } else { 1421 write_scr_el3(scr_el3 | SCR_NS_BIT); 1422 } 1423 isb(); 1424 } 1425 1426 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1427 1428 if (errata_ich_vmcr_el2_applies()) { 1429 write_scr_el3(scr_el3); 1430 isb(); 1431 } 1432 } 1433 1434 /* ----------------------------------------------------- 1435 * The following registers are not added: 1436 * AMEVCNTVOFF0<n>_EL2 1437 * AMEVCNTVOFF1<n>_EL2 1438 * ----------------------------------------------------- 1439 */ 1440 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1441 { 1442 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1443 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1444 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1445 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1446 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1447 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1448 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1449 if (CTX_INCLUDE_AARCH32_REGS) { 1450 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1451 } 1452 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1453 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1454 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1455 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1456 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1457 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1458 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1459 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1460 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1461 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1462 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1463 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1464 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1465 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1466 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1467 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1468 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1469 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1470 1471 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1472 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1473 } 1474 1475 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1476 { 1477 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1478 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1479 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1480 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1481 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1482 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1483 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1484 if (CTX_INCLUDE_AARCH32_REGS) { 1485 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1486 } 1487 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1488 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1489 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1490 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1491 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1492 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1493 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1494 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1495 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1496 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1497 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1498 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1499 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1500 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1501 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1502 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1503 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1504 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1505 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1506 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1507 } 1508 1509 /******************************************************************************* 1510 * Save EL2 sysreg context 1511 ******************************************************************************/ 1512 void cm_el2_sysregs_context_save(uint32_t security_state) 1513 { 1514 cpu_context_t *ctx; 1515 el2_sysregs_t *el2_sysregs_ctx; 1516 1517 ctx = cm_get_context(security_state); 1518 assert(ctx != NULL); 1519 1520 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1521 1522 el2_sysregs_context_save_common(el2_sysregs_ctx); 1523 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1524 1525 if (is_feat_mte2_supported()) { 1526 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1527 } 1528 1529 if (is_feat_mpam_supported()) { 1530 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1531 } 1532 1533 if (is_feat_fgt_supported()) { 1534 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1535 } 1536 1537 if (is_feat_fgt2_supported()) { 1538 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1539 } 1540 1541 if (is_feat_ecv_v2_supported()) { 1542 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1543 } 1544 1545 if (is_feat_vhe_supported()) { 1546 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1547 read_contextidr_el2()); 1548 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1549 } 1550 1551 if (is_feat_ras_supported()) { 1552 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1553 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1554 } 1555 1556 if (is_feat_nv2_supported()) { 1557 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1558 } 1559 1560 if (is_feat_trf_supported()) { 1561 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1562 } 1563 1564 if (is_feat_csv2_2_supported()) { 1565 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1566 read_scxtnum_el2()); 1567 } 1568 1569 if (is_feat_hcx_supported()) { 1570 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1571 } 1572 1573 if (is_feat_tcr2_supported()) { 1574 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1575 } 1576 1577 if (is_feat_sxpie_supported()) { 1578 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1579 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1580 } 1581 1582 if (is_feat_sxpoe_supported()) { 1583 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1584 } 1585 1586 if (is_feat_brbe_supported()) { 1587 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1588 } 1589 1590 if (is_feat_s2pie_supported()) { 1591 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1592 } 1593 1594 if (is_feat_gcs_supported()) { 1595 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1596 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1597 } 1598 1599 if (is_feat_sctlr2_supported()) { 1600 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1601 } 1602 } 1603 1604 /******************************************************************************* 1605 * Restore EL2 sysreg context 1606 ******************************************************************************/ 1607 void cm_el2_sysregs_context_restore(uint32_t security_state) 1608 { 1609 cpu_context_t *ctx; 1610 el2_sysregs_t *el2_sysregs_ctx; 1611 1612 ctx = cm_get_context(security_state); 1613 assert(ctx != NULL); 1614 1615 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1616 1617 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1618 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1619 1620 if (is_feat_mte2_supported()) { 1621 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1622 } 1623 1624 if (is_feat_mpam_supported()) { 1625 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1626 } 1627 1628 if (is_feat_fgt_supported()) { 1629 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1630 } 1631 1632 if (is_feat_fgt2_supported()) { 1633 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1634 } 1635 1636 if (is_feat_ecv_v2_supported()) { 1637 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1638 } 1639 1640 if (is_feat_vhe_supported()) { 1641 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1642 contextidr_el2)); 1643 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1644 } 1645 1646 if (is_feat_ras_supported()) { 1647 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1648 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1649 } 1650 1651 if (is_feat_nv2_supported()) { 1652 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1653 } 1654 1655 if (is_feat_trf_supported()) { 1656 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1657 } 1658 1659 if (is_feat_csv2_2_supported()) { 1660 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1661 scxtnum_el2)); 1662 } 1663 1664 if (is_feat_hcx_supported()) { 1665 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1666 } 1667 1668 if (is_feat_tcr2_supported()) { 1669 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1670 } 1671 1672 if (is_feat_sxpie_supported()) { 1673 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1674 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1675 } 1676 1677 if (is_feat_sxpoe_supported()) { 1678 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1679 } 1680 1681 if (is_feat_s2pie_supported()) { 1682 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1683 } 1684 1685 if (is_feat_gcs_supported()) { 1686 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1687 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1688 } 1689 1690 if (is_feat_sctlr2_supported()) { 1691 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1692 } 1693 1694 if (is_feat_brbe_supported()) { 1695 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1696 } 1697 } 1698 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1699 1700 /******************************************************************************* 1701 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1702 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1703 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1704 * cm_prepare_el3_exit function. 1705 ******************************************************************************/ 1706 void cm_prepare_el3_exit_ns(void) 1707 { 1708 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1709 #if ENABLE_ASSERTIONS 1710 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1711 assert(ctx != NULL); 1712 1713 /* Assert that EL2 is used. */ 1714 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1715 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1716 (el_implemented(2U) != EL_IMPL_NONE)); 1717 #endif /* ENABLE_ASSERTIONS */ 1718 1719 /* Restore EL2 sysreg contexts */ 1720 cm_el2_sysregs_context_restore(NON_SECURE); 1721 cm_set_next_eret_context(NON_SECURE); 1722 #else 1723 cm_prepare_el3_exit(NON_SECURE); 1724 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1725 } 1726 1727 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1728 /******************************************************************************* 1729 * The next set of six functions are used by runtime services to save and restore 1730 * EL1 context on the 'cpu_context' structure for the specified security state. 1731 ******************************************************************************/ 1732 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1733 { 1734 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1735 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1736 1737 #if (!ERRATA_SPECULATIVE_AT) 1738 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1739 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1740 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1741 1742 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1743 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1744 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1745 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1746 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1747 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1748 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1749 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1750 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1751 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1752 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1753 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1754 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1755 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1756 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1757 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1758 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1759 1760 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1761 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1762 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1763 1764 if (CTX_INCLUDE_AARCH32_REGS) { 1765 /* Save Aarch32 registers */ 1766 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1767 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1768 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1769 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1770 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1771 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1772 } 1773 1774 /* Save counter-timer kernel control register */ 1775 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1776 #if NS_TIMER_SWITCH 1777 /* Save NS Timer registers */ 1778 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1779 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1780 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1781 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1782 #endif 1783 1784 if (is_feat_mte2_supported()) { 1785 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1786 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1787 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1788 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1789 } 1790 1791 if (is_feat_ras_supported()) { 1792 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1793 } 1794 1795 if (is_feat_s1pie_supported()) { 1796 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1797 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1798 } 1799 1800 if (is_feat_s1poe_supported()) { 1801 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1802 } 1803 1804 if (is_feat_s2poe_supported()) { 1805 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1806 } 1807 1808 if (is_feat_tcr2_supported()) { 1809 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1810 } 1811 1812 if (is_feat_trf_supported()) { 1813 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1814 } 1815 1816 if (is_feat_csv2_2_supported()) { 1817 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1818 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1819 } 1820 1821 if (is_feat_gcs_supported()) { 1822 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1823 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1824 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1825 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1826 } 1827 1828 if (is_feat_the_supported()) { 1829 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1830 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1831 } 1832 1833 if (is_feat_sctlr2_supported()) { 1834 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1835 } 1836 1837 if (is_feat_ls64_accdata_supported()) { 1838 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1839 } 1840 } 1841 1842 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1843 { 1844 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1845 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1846 1847 #if (!ERRATA_SPECULATIVE_AT) 1848 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1849 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1850 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1851 1852 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1853 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1854 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1855 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1856 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1857 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1858 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1859 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1860 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1861 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1862 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1863 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1864 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1865 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1866 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1867 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1868 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1869 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1870 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1871 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1872 1873 if (CTX_INCLUDE_AARCH32_REGS) { 1874 /* Restore Aarch32 registers */ 1875 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1876 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1877 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1878 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1879 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1880 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1881 } 1882 1883 /* Restore counter-timer kernel control register */ 1884 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1885 #if NS_TIMER_SWITCH 1886 /* Restore NS Timer registers */ 1887 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1888 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1889 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1890 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1891 #endif 1892 1893 if (is_feat_mte2_supported()) { 1894 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1895 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1896 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1897 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1898 } 1899 1900 if (is_feat_ras_supported()) { 1901 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1902 } 1903 1904 if (is_feat_s1pie_supported()) { 1905 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1906 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1907 } 1908 1909 if (is_feat_s1poe_supported()) { 1910 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1911 } 1912 1913 if (is_feat_s2poe_supported()) { 1914 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1915 } 1916 1917 if (is_feat_tcr2_supported()) { 1918 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1919 } 1920 1921 if (is_feat_trf_supported()) { 1922 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1923 } 1924 1925 if (is_feat_csv2_2_supported()) { 1926 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1927 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1928 } 1929 1930 if (is_feat_gcs_supported()) { 1931 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1932 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1933 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1934 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1935 } 1936 1937 if (is_feat_the_supported()) { 1938 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1939 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1940 } 1941 1942 if (is_feat_sctlr2_supported()) { 1943 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1944 } 1945 1946 if (is_feat_ls64_accdata_supported()) { 1947 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1948 } 1949 } 1950 1951 /******************************************************************************* 1952 * The next couple of functions are used by runtime services to save and restore 1953 * EL1 context on the 'cpu_context' structure for the specified security state. 1954 ******************************************************************************/ 1955 void cm_el1_sysregs_context_save(uint32_t security_state) 1956 { 1957 cpu_context_t *ctx; 1958 1959 ctx = cm_get_context(security_state); 1960 assert(ctx != NULL); 1961 1962 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1963 1964 #if IMAGE_BL31 1965 if (security_state == SECURE) { 1966 PUBLISH_EVENT(cm_exited_secure_world); 1967 } else { 1968 PUBLISH_EVENT(cm_exited_normal_world); 1969 } 1970 #endif 1971 } 1972 1973 void cm_el1_sysregs_context_restore(uint32_t security_state) 1974 { 1975 cpu_context_t *ctx; 1976 1977 ctx = cm_get_context(security_state); 1978 assert(ctx != NULL); 1979 1980 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1981 1982 #if IMAGE_BL31 1983 if (security_state == SECURE) { 1984 PUBLISH_EVENT(cm_entering_secure_world); 1985 } else { 1986 PUBLISH_EVENT(cm_entering_normal_world); 1987 } 1988 #endif 1989 } 1990 1991 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1992 1993 /******************************************************************************* 1994 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1995 * given security state with the given entrypoint 1996 ******************************************************************************/ 1997 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1998 { 1999 cpu_context_t *ctx; 2000 el3_state_t *state; 2001 2002 ctx = cm_get_context(security_state); 2003 assert(ctx != NULL); 2004 2005 /* Populate EL3 state so that ERET jumps to the correct entry */ 2006 state = get_el3state_ctx(ctx); 2007 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2008 } 2009 2010 /******************************************************************************* 2011 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2012 * pertaining to the given security state 2013 ******************************************************************************/ 2014 void cm_set_elr_spsr_el3(uint32_t security_state, 2015 uintptr_t entrypoint, uint32_t spsr) 2016 { 2017 cpu_context_t *ctx; 2018 el3_state_t *state; 2019 2020 ctx = cm_get_context(security_state); 2021 assert(ctx != NULL); 2022 2023 /* Populate EL3 state so that ERET jumps to the correct entry */ 2024 state = get_el3state_ctx(ctx); 2025 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2026 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2027 } 2028 2029 /******************************************************************************* 2030 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2031 * pertaining to the given security state using the value and bit position 2032 * specified in the parameters. It preserves all other bits. 2033 ******************************************************************************/ 2034 void cm_write_scr_el3_bit(uint32_t security_state, 2035 uint32_t bit_pos, 2036 uint32_t value) 2037 { 2038 cpu_context_t *ctx; 2039 el3_state_t *state; 2040 u_register_t scr_el3; 2041 2042 ctx = cm_get_context(security_state); 2043 assert(ctx != NULL); 2044 2045 /* Ensure that the bit position is a valid one */ 2046 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2047 2048 /* Ensure that the 'value' is only a bit wide */ 2049 assert(value <= 1U); 2050 2051 /* 2052 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2053 * and set it to its new value. 2054 */ 2055 state = get_el3state_ctx(ctx); 2056 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2057 scr_el3 &= ~(1UL << bit_pos); 2058 scr_el3 |= (u_register_t)value << bit_pos; 2059 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2060 } 2061 2062 /******************************************************************************* 2063 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2064 * given security state. 2065 ******************************************************************************/ 2066 u_register_t cm_get_scr_el3(uint32_t security_state) 2067 { 2068 const cpu_context_t *ctx; 2069 const el3_state_t *state; 2070 2071 ctx = cm_get_context(security_state); 2072 assert(ctx != NULL); 2073 2074 /* Populate EL3 state so that ERET jumps to the correct entry */ 2075 state = get_el3state_ctx(ctx); 2076 return read_ctx_reg(state, CTX_SCR_EL3); 2077 } 2078 2079 /******************************************************************************* 2080 * This function is used to program the context that's used for exception 2081 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2082 * the required security state 2083 ******************************************************************************/ 2084 void cm_set_next_eret_context(uint32_t security_state) 2085 { 2086 cpu_context_t *ctx; 2087 2088 ctx = cm_get_context(security_state); 2089 assert(ctx != NULL); 2090 2091 cm_set_next_context(ctx); 2092 } 2093