feat(rmmd): extend RMI function ID range validation

Add support for the extended RMI function number range (RMI_FNUM1)in
the is_rmi_fid() macro. The macro now validates FIDs in both:
- Original rang

feat(rmmd): extend RMI function ID range validation

Add support for the extended RMI function number range (RMI_FNUM1)in
the is_rmi_fid() macro. The macro now validates FIDs in both:
- Original range: 0x150 - 0x18F (RMI_FNUM_MIN_VALUE to RMI_FNUM_MAX_VALUE)
- Extended range: 0x1D0 - 0x2CF (RMI_FNUM1_MIN_VALUE to RMI_FNUM1_MAX_VALUE)

This change ensures proper identification and handling of RMI calls
across the full function ID space as defined by the RMM specification.

Change-Id: Ie65999ffeacc94057389e056761e57586f804b63
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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fix(smccc): ignore SCR_EEL2_BIT

Commit cbba59c41a99 ("enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM")
enables ARCH_FEATURE_AVAILABILITY by default when RME is enabled which
results into below asser

fix(smccc): ignore SCR_EEL2_BIT

Commit cbba59c41a99 ("enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM")
enables ARCH_FEATURE_AVAILABILITY by default when RME is enabled which
results into below assertion when RMM queries the features.

ERROR: Unexpected bits 0x40000 were set in register 1e1100!
ASSERT: services/arm_arch_svc/arm_arch_svc_setup.c:251

This happpens because SCR_EEL2_BIT is neither part of SCR_EL3_FEATS nor
part of SCR_EL3_IGNORED, as the SMCCC spec doesn't list SCR_EEL2_BIT as
reported, add it to SCR_EL3_IGNORED.

Change-Id: I0465744dc7f0ae589d6a8345c1cca63ac6f7f357
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from diffe

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime the
same component.

This patch checks if the plat_lfa_load_auth_image return -EAGAIN
indicating that the platform expects the LFA_PRIME call to be
issued again. This is done by returning LFA_SUCCESS and setting
flags[0] to 1, indicating that LFA_PRIME is incomplete and must
be called again.

Change-Id: Ia3046b5467c50c4c51392bac3fb9e9533f2438db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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fix(cpufeat): use of additional breakpoints

Extended Breakpoints access through mdcr_el3.ebwe is available
only when there are greater than 16 breakpoints implemented.
Otherwise the EBWE Bit is RES0

fix(cpufeat): use of additional breakpoints

Extended Breakpoints access through mdcr_el3.ebwe is available
only when there are greater than 16 breakpoints implemented.
Otherwise the EBWE Bit is RES0 and we could skip enabling Extended
Breakpoint access.

Ref: https://developer.arm.com/documentation/111107/2025-09/AArch64-Registers/MDCR-EL3--Monitor-Debug-Configuration-Register--EL3-?lang=en

Change-Id: I2b2147e83d65ee9b0492d3cf3adafd5c8cbe17f5
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa)

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa): rename component_id to lfa_component_id

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chore(lfa): rename component_id to lfa_component_id

Refactor the function lfa_is_prime_complete to use a more specific
parameter name, lfa_component_id, enhancing code clarity. This change
improves

chore(lfa): rename component_id to lfa_component_id

Refactor the function lfa_is_prime_complete to use a more specific
parameter name, lfa_component_id, enhancing code clarity. This change
improves readability and reduces potential confusion with other
component identifiers in the codebase.

Change-Id: I00285fce4b7149bd97d6386ef471e9d1598a3fed
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(smccc): fixed define when ENABLE_FEAT_FPMR is disabled

Define SCR_FEAT_FPMR as 0 when ENABLE_FEAT_FPMR is disabled to avoid
conditional build inconsistencies.

Signed-off-by: Arvind Ram Prakash

fix(smccc): fixed define when ENABLE_FEAT_FPMR is disabled

Define SCR_FEAT_FPMR as 0 when ENABLE_FEAT_FPMR is disabled to avoid
conditional build inconsistencies.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ibe71fa20fa4ffa98d8fff41517ccbf29755a58c3

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feat(cpufeat): enable FEAT_PFAR support

Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system register

feat(cpufeat): enable FEAT_PFAR support

Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system registers are trapped by the SCR_EL3.PFARen bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_PFAR build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: I5c9ae750417e75792f693732df3869e02b6e4319
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(cpufeat): enable FEAT_AIE support" into integration

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those system registers are trapped by the SCR_EL3.AIEn bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_AIE build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: Iba2011719013a89f9cb3a4317bde18254f45cd25
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(lfa): add helper to check LFA prime completion status

Introduce `is_lfa_prime_finished()` to allow callers to query whether the
prime operation for a given component has completed. This enables

feat(lfa): add helper to check LFA prime completion status

Introduce `is_lfa_prime_finished()` to allow callers to query whether the
prime operation for a given component has completed. This enables external
logic to safely determine if activation is ready to proceed.

The helper checks for:
- Matching `component_id` in the current activation
- Prime status being `PRIME_COMPLETE`
- `activation_pending` being true

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I55dadba639571faacc27de245cf0a9f2493956a5

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chore(lfa): use standard int return type for prime/activate callbacks

Replace `int32_t` with `int` for `component_prime_fn` and
`component_activate_fn` typedefs, along with their implementations
in

chore(lfa): use standard int return type for prime/activate callbacks

Replace `int32_t` with `int` for `component_prime_fn` and
`component_activate_fn` typedefs, along with their implementations
in BL31 and RMM LFA services. This aligns with common convention
for function return types and avoids unnecessary use of fixed-width
types where a native int is sufficient

Change-Id: Id22e93a554260b22e36b59baeac2cbb1b4646727
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(rmmd): add warm reset helpers for primary and secondary CPUs

Introduce two helpers to support RMM warm reset, primarily for use
during Live Firmware Activation:

- rmmd_primary_warm_reset(): r

feat(rmmd): add warm reset helpers for primary and secondary CPUs

Introduce two helpers to support RMM warm reset, primarily for use
during Live Firmware Activation:

- rmmd_primary_warm_reset(): re-runs rmmd_setup() and rmm_init()
for the primary CPU.
- rmmd_secondary_warm_reset(): reinitializes secondary CPUs using
rmmd_cpu_on_finish_handler(), with a spinlock to serialize
access.

Change-Id: I885536aa85e395ed69069802112dcdb5063a9c19
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "ja/ffa_v1_3" into integration

* changes:
feat(tc): bump SPMC version to FF-A v1.3 TC platform
feat(fvp): bump the SPMC version
feat(ff-a): bump SPMD FF-A version

feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR mac

feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR macros.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I0494738b9978ad72b3316a24d7811096c53f952b

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Merge changes I32c5be5d,I15a652a0 into integration

* changes:
fix(qemu): add reason parameter to MEC update
refactor(rmmd): modify MEC update call to meet FIRME

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[1] https://developer.arm.com/documentation/den0149/1-0alp0/

Change-Id: I15a652a021561edca16e79d127e6f08975cf1361
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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feat(spmd): support for FFA_ABORT invocation from SWd

SPMC can propagate abort handling to SPMD when an SP specifies suitable
abort action in its manifest. SPMD panics upon receiving FFA_ABORT from

feat(spmd): support for FFA_ABORT invocation from SWd

SPMC can propagate abort handling to SPMD when an SP specifies suitable
abort action in its manifest. SPMD panics upon receiving FFA_ABORT from
SPMC.

Change-Id: I3b573fdfc203c3446b1d629f579e333162d5ff72
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "feat(spmd): add FFA_NS_RES_INFO_GET ABI" into integration

Merge "feat(el3-spmc): parse and report VM availability messages" into integration

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505

feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505aab1ba9e8c
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7

feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7924
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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