1 /*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/arm/cci.h>
14 #include <drivers/arm/ccn.h>
15 #include <drivers/arm/gicv2.h>
16 #include <drivers/arm/sp804_delay_timer.h>
17 #include <drivers/arm/smmu_v3.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <fconf_hw_config_getter.h>
20 #include <lib/mmio.h>
21 #include <lib/smccc.h>
22 #include <lib/xlat_tables/xlat_tables_compat.h>
23 #include <platform_def.h>
24 #include <services/arm_arch_svc.h>
25 #include <services/rmm_core_manifest.h>
26 #if SPM_MM
27 #include <services/spm_mm_partition.h>
28 #endif
29
30 #include <plat/arm/common/arm_config.h>
31 #include <plat/arm/common/plat_arm.h>
32 #include <plat/common/platform.h>
33
34 #include "fvp_private.h"
35
36 /* Defines for GIC Driver build time selection */
37 #define FVP_GICV2 1
38 #define FVP_GICV3 2
39
40 /* Defines for RMM Console */
41 #define FVP_RMM_CONSOLE_BASE UL(0x1c0c0000)
42 #define FVP_RMM_CONSOLE_BAUD UL(115200)
43 #define FVP_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
44 #define FVP_RMM_CONSOLE_NAME "pl011"
45 #define FVP_RMM_CONSOLE_COUNT UL(1)
46
47 /* Defines for RMM PCIe ECAM */
48 #define FVP_RMM_ECAM_BASE PCIE_EXP_BASE
49 #define FVP_RMM_ECAM_SEGMENT UL(0x0)
50 #define FVP_RMM_ECAM_BDF UL(0x0)
51
52 /* Defines for RMM SMMUv3 */
53 #define FVP_RMM_SMMU_BASE PLAT_FVP_SMMUV3_BASE
54 #define FVP_RMM_SMMU_COUNT UL(1)
55
56 /*******************************************************************************
57 * arm_config holds the characteristics of the differences between the three FVP
58 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
59 * at each boot stage by the primary before enabling the MMU (to allow
60 * interconnect configuration) & used thereafter. Each BL will have its own copy
61 * to allow independent operation.
62 ******************************************************************************/
63 arm_config_t arm_config;
64
65 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
66 DEVICE0_SIZE, \
67 MT_DEVICE | MT_RW | EL3_PAS)
68
69 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
70 DEVICE1_SIZE, \
71 MT_DEVICE | MT_RW | EL3_PAS)
72
73 #define MAP_CCN MAP_REGION_FLAT(CCN_BASE, \
74 CCN_SIZE, \
75 MT_DEVICE | MT_RW | MT_SECURE)
76
77 #if FVP_GICR_REGION_PROTECTION
78 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
79 BASE_GICD_SIZE, \
80 MT_DEVICE | MT_RW | MT_SECURE)
81
82 /* Map all core's redistributor memory as read-only. After boots up,
83 * per-core map its redistributor memory as read-write */
84 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
85 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
86 MT_DEVICE | MT_RO | MT_SECURE)
87 #endif /* FVP_GICR_REGION_PROTECTION */
88
89 /*
90 * Need to be mapped with write permissions in order to set a new non-volatile
91 * counter value.
92 */
93 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
94 DEVICE2_SIZE, \
95 MT_DEVICE | MT_RW | MT_SECURE)
96
97 #if TRANSFER_LIST
98 #ifdef FW_NS_HANDOFF_BASE
99 #define MAP_FW_NS_HANDOFF \
100 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
101 MT_MEMORY | MT_RW | MT_NS)
102 #endif
103 #ifdef PLAT_ARM_EL3_FW_HANDOFF_BASE
104 #define MAP_EL3_FW_HANDOFF \
105 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
106 PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
107 #endif
108 #endif
109
110 /*
111 * Table of memory regions for various BL stages to map using the MMU.
112 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
113 * of mapping it.
114 */
115 #ifdef IMAGE_BL1
116 const mmap_region_t plat_arm_mmap[] = {
117 ARM_MAP_SHARED_RAM,
118 V2M_MAP_FLASH0_RO,
119 V2M_MAP_IOFPGA,
120 MAP_DEVICE0,
121 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
122 MAP_CCN,
123 #endif
124 #if TRUSTED_BOARD_BOOT
125 /* To access the Root of Trust Public Key registers. */
126 MAP_DEVICE2,
127 /* Map DRAM to authenticate NS_BL2U image. */
128 ARM_MAP_NS_DRAM1,
129 #endif
130 {0}
131 };
132 #endif
133 #ifdef IMAGE_BL2
134 const mmap_region_t plat_arm_mmap[] = {
135 ARM_MAP_SHARED_RAM,
136 V2M_MAP_FLASH0_RW,
137 V2M_MAP_IOFPGA,
138 MAP_DEVICE0,
139 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
140 MAP_CCN,
141 #endif
142 ARM_MAP_NS_DRAM1,
143 #ifdef __aarch64__
144 ARM_MAP_DRAM2,
145 #endif
146 /*
147 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM.
148 */
149 ARM_MAP_TRUSTED_DRAM,
150
151 /*
152 * Required to load Event Log in TZC secured memory
153 */
154 #if MEASURED_BOOT && (defined(SPD_tspd) || defined(SPD_opteed) || \
155 defined(SPD_spmd))
156 ARM_MAP_EVENT_LOG_DRAM1,
157 #endif /* MEASURED_BOOT && (SPD_tspd || SPD_opteed || SPD_spmd) */
158
159 #if ENABLE_RME
160 ARM_MAP_RMM_DRAM,
161 ARM_MAP_GPT_L1_DRAM,
162 #endif /* ENABLE_RME */
163 #ifdef SPD_tspd
164 ARM_MAP_TSP_SEC_MEM,
165 #endif
166 #if TRUSTED_BOARD_BOOT
167 /* To access the Root of Trust Public Key registers. */
168 MAP_DEVICE2,
169 #endif /* TRUSTED_BOARD_BOOT */
170
171 #if CRYPTO_SUPPORT && !RESET_TO_BL2
172 /*
173 * To access shared the Mbed TLS heap while booting the
174 * system with Crypto support
175 */
176 ARM_MAP_BL1_RW,
177 #endif /* CRYPTO_SUPPORT && !RESET_TO_BL2 */
178 #if SPM_MM || SPMC_AT_EL3
179 ARM_SP_IMAGE_MMAP,
180 #endif
181 #if ARM_BL31_IN_DRAM
182 ARM_MAP_BL31_SEC_DRAM,
183 #endif
184 #ifdef SPD_opteed
185 ARM_MAP_OPTEE_CORE_MEM,
186 ARM_OPTEE_PAGEABLE_LOAD_MEM,
187 #endif
188 #ifdef MAP_EL3_FW_HANDOFF
189 MAP_EL3_FW_HANDOFF,
190 #endif
191 { 0 }
192 };
193 #endif
194 #ifdef IMAGE_BL2U
195 const mmap_region_t plat_arm_mmap[] = {
196 MAP_DEVICE0,
197 V2M_MAP_IOFPGA,
198 {0}
199 };
200 #endif
201 #ifdef IMAGE_BL31
202 const mmap_region_t plat_arm_mmap[] = {
203 ARM_MAP_SHARED_RAM,
204 #if USE_DEBUGFS
205 /* Required by devfip, can be removed if devfip is not used */
206 V2M_MAP_FLASH0_RW,
207 #endif /* USE_DEBUGFS */
208 ARM_MAP_EL3_TZC_DRAM,
209 V2M_MAP_IOFPGA,
210 MAP_DEVICE0,
211 #if FVP_GICR_REGION_PROTECTION
212 MAP_GICD_MEM,
213 MAP_GICR_MEM,
214 #else
215 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
216 MAP_CCN,
217 #endif
218 MAP_DEVICE1,
219 #endif /* FVP_GICR_REGION_PROTECTION */
220 ARM_V2M_MAP_MEM_PROTECT,
221 #if SPM_MM
222 ARM_SPM_BUF_EL3_MMAP,
223 #endif
224 #if ENABLE_RME
225 ARM_MAP_GPT_L1_DRAM,
226 ARM_MAP_EL3_RMM_SHARED_MEM,
227 #endif
228 #ifdef MAP_FW_NS_HANDOFF
229 MAP_FW_NS_HANDOFF,
230 #endif
231 #if defined(MAP_EL3_FW_HANDOFF) && !RESET_TO_BL31
232 MAP_EL3_FW_HANDOFF,
233 #endif
234 { 0 }
235 };
236
237 #if defined(IMAGE_BL31) && SPM_MM
238 const mmap_region_t plat_arm_secure_partition_mmap[] = {
239 V2M_MAP_IOFPGA_EL0, /* for the UART */
240 V2M_MAP_SECURE_SYSTEMREG_EL0, /* for initializing flash */
241 #if PSA_FWU_SUPPORT
242 V2M_MAP_FLASH0_RW_EL0, /* for firmware update service in standalone mm */
243 #endif
244 V2M_MAP_FLASH1_RW_EL0, /* for secure variable service in standalone mm */
245 MAP_REGION_FLAT(DEVICE0_BASE,
246 DEVICE0_SIZE,
247 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
248 ARM_SP_IMAGE_MMAP,
249 ARM_SP_IMAGE_NS_BUF_MMAP,
250 ARM_SP_IMAGE_RW_MMAP,
251 ARM_SPM_BUF_EL0_MMAP,
252 ARM_SP_PSEUDO_NS_CRB_MMAP,
253 ARM_SP_PSEUDO_S_CRB_MMAP,
254 {0}
255 };
256 #endif
257 #endif
258 #ifdef IMAGE_BL32
259 const mmap_region_t plat_arm_mmap[] = {
260 #ifndef __aarch64__
261 ARM_MAP_SHARED_RAM,
262 ARM_V2M_MAP_MEM_PROTECT,
263 #endif
264 V2M_MAP_IOFPGA,
265 MAP_DEVICE0,
266 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
267 MAP_CCN,
268 #endif
269 MAP_DEVICE1,
270 {0}
271 };
272 #endif
273
274 #ifdef IMAGE_RMM
275 const mmap_region_t plat_arm_mmap[] = {
276 V2M_MAP_IOFPGA,
277 MAP_DEVICE0,
278 MAP_DEVICE1,
279 {0}
280 };
281 #endif
282
283 ARM_CASSERT_MMAP
284
285 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
286 static const int fvp_cci400_map[] = {
287 PLAT_FVP_CCI400_CLUS0_SL_PORT,
288 PLAT_FVP_CCI400_CLUS1_SL_PORT,
289 };
290
291 static const int fvp_cci5xx_map[] = {
292 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
293 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
294 };
295
get_interconnect_master(void)296 static unsigned int get_interconnect_master(void)
297 {
298 unsigned int master;
299 u_register_t mpidr;
300
301 mpidr = read_mpidr_el1();
302 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
303 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
304
305 assert(master < FVP_CLUSTER_COUNT);
306 return master;
307 }
308 #endif
309
310 #if defined(IMAGE_BL31) && SPM_MM
311 /*
312 * Boot information passed to a secure partition during initialisation. Linear
313 * indices in MP information will be filled at runtime.
314 */
315 static spm_mm_mp_info_t sp_mp_info[] = {
316 [0] = {0x80000000, 0},
317 [1] = {0x80000001, 0},
318 [2] = {0x80000002, 0},
319 [3] = {0x80000003, 0},
320 [4] = {0x80000100, 0},
321 [5] = {0x80000101, 0},
322 [6] = {0x80000102, 0},
323 [7] = {0x80000103, 0},
324 };
325
326 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
327 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
328 .h.version = VERSION_1,
329 .h.size = sizeof(spm_mm_boot_info_t),
330 .h.attr = 0,
331 .sp_mem_base = ARM_SP_IMAGE_BASE,
332 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
333 .sp_image_base = ARM_SP_IMAGE_BASE,
334 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
335 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
336 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
337 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
338 .sp_image_size = ARM_SP_IMAGE_SIZE,
339 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
340 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
341 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
342 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
343 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
344 .num_cpus = PLATFORM_CORE_COUNT,
345 .mp_info = &sp_mp_info[0],
346 };
347
plat_get_secure_partition_mmap(void * cookie)348 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
349 {
350 return plat_arm_secure_partition_mmap;
351 }
352
plat_get_secure_partition_boot_info(void * cookie)353 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
354 void *cookie)
355 {
356 return &plat_arm_secure_partition_boot_info;
357 }
358 #endif
359
360 /*******************************************************************************
361 * A single boot loader stack is expected to work on both the Foundation FVP
362 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
363 * SYS_ID register provides a mechanism for detecting the differences between
364 * these platforms. This information is stored in a per-BL array to allow the
365 * code to take the correct path.Per BL platform configuration.
366 ******************************************************************************/
fvp_config_setup(void)367 void __init fvp_config_setup(void)
368 {
369 unsigned int rev, hbi, bld, arch, sys_id;
370
371 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
372 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
373 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
374 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
375 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
376
377 if (arch != ARCH_MODEL) {
378 ERROR("This firmware is for FVP models\n");
379 panic();
380 }
381
382 /*
383 * The build field in the SYS_ID tells which variant of the GIC
384 * memory is implemented by the model.
385 */
386 switch (bld) {
387 case BLD_GIC_VE_MMAP:
388 ERROR("Legacy Versatile Express memory map for GIC peripheral"
389 " is not supported\n");
390 panic();
391 break;
392 case BLD_GIC_A53A57_MMAP:
393 break;
394 default:
395 ERROR("Unsupported board build %x\n", bld);
396 panic();
397 }
398
399 /*
400 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
401 * for the Foundation FVP.
402 */
403 switch (hbi) {
404 case HBI_FOUNDATION_FVP:
405 arm_config.flags = 0;
406
407 /*
408 * Check for supported revisions of Foundation FVP
409 * Allow future revisions to run but emit warning diagnostic
410 */
411 switch (rev) {
412 case REV_FOUNDATION_FVP_V2_0:
413 case REV_FOUNDATION_FVP_V2_1:
414 case REV_FOUNDATION_FVP_v9_1:
415 case REV_FOUNDATION_FVP_v9_6:
416 break;
417 default:
418 WARN("Unrecognized Foundation FVP revision %x\n", rev);
419 break;
420 }
421 break;
422 case HBI_BASE_FVP:
423 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
424
425 /*
426 * Check for supported revisions
427 * Allow future revisions to run but emit warning diagnostic
428 */
429 switch (rev) {
430 case REV_BASE_FVP_V0:
431 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
432 break;
433 case REV_BASE_FVP_REVC:
434 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
435 ARM_CONFIG_FVP_HAS_CCI5XX);
436 break;
437 default:
438 WARN("Unrecognized Base FVP revision %x\n", rev);
439 break;
440 }
441 break;
442 default:
443 ERROR("Unsupported board HBI number 0x%x\n", hbi);
444 panic();
445 }
446
447 /*
448 * We assume that the presence of MT bit, and therefore shifted
449 * affinities, is uniform across the platform: either all CPUs, or no
450 * CPUs implement it.
451 */
452 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
453 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
454 }
455
456
fvp_interconnect_init(void)457 void __init fvp_interconnect_init(void)
458 {
459 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
460 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
461 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
462 panic();
463 }
464
465 plat_arm_interconnect_init();
466 #else
467 uintptr_t cci_base = 0U;
468 const int *cci_map = NULL;
469 unsigned int map_size = 0U;
470
471 /* Initialize the right interconnect */
472 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
473 cci_base = PLAT_FVP_CCI5XX_BASE;
474 cci_map = fvp_cci5xx_map;
475 map_size = ARRAY_SIZE(fvp_cci5xx_map);
476 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
477 cci_base = PLAT_FVP_CCI400_BASE;
478 cci_map = fvp_cci400_map;
479 map_size = ARRAY_SIZE(fvp_cci400_map);
480 } else {
481 return;
482 }
483
484 assert(cci_base != 0U);
485 assert(cci_map != NULL);
486 cci_init(cci_base, cci_map, map_size);
487 #endif
488 }
489
fvp_interconnect_enable(void)490 void fvp_interconnect_enable(void)
491 {
492 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
493 plat_arm_interconnect_enter_coherency();
494 #else
495 unsigned int master;
496
497 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
498 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
499 master = get_interconnect_master();
500 cci_enable_snoop_dvm_reqs(master);
501 }
502 #endif
503 }
504
fvp_interconnect_disable(void)505 void fvp_interconnect_disable(void)
506 {
507 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
508 plat_arm_interconnect_exit_coherency();
509 #else
510 unsigned int master;
511
512 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
513 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
514 master = get_interconnect_master();
515 cci_disable_snoop_dvm_reqs(master);
516 }
517 #endif
518 }
519
520 #if CRYPTO_SUPPORT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)521 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
522 {
523 assert(heap_addr != NULL);
524 assert(heap_size != NULL);
525
526 return arm_get_mbedtls_heap(heap_addr, heap_size);
527 }
528 #endif /* CRYPTO_SUPPORT */
529
fvp_timer_init(void)530 void fvp_timer_init(void)
531 {
532 #if USE_SP804_TIMER
533 /* Enable the clock override for SP804 timer 0, which means that no
534 * clock dividers are applied and the raw (35MHz) clock will be used.
535 */
536 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
537
538 /* Initialize delay timer driver using SP804 dual timer 0 */
539 sp804_timer_init(V2M_SP804_TIMER0_BASE,
540 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
541 #else
542 generic_delay_timer_init();
543
544 /* Enable System level generic timer */
545 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
546 CNTCR_FCREQ(0U) | CNTCR_EN);
547 #endif /* USE_SP804_TIMER */
548 }
549
550 /*****************************************************************************
551 * plat_is_smccc_feature_available() - This function checks whether SMCCC
552 * feature is availabile for platform.
553 * @fid: SMCCC function id
554 *
555 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
556 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
557 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)558 int32_t plat_is_smccc_feature_available(u_register_t fid)
559 {
560 switch (fid) {
561 case SMCCC_ARCH_SOC_ID:
562 return SMC_ARCH_CALL_SUCCESS;
563 default:
564 return SMC_ARCH_CALL_NOT_SUPPORTED;
565 }
566 }
567
568 /* Get SOC version */
plat_get_soc_version(void)569 int32_t plat_get_soc_version(void)
570 {
571 return (int32_t)
572 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
573 ARM_SOC_IDENTIFICATION_CODE) |
574 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
575 }
576
577 /* Get SOC revision */
plat_get_soc_revision(void)578 int32_t plat_get_soc_revision(void)
579 {
580 unsigned int sys_id;
581
582 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
583 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
584 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
585 }
586
587 /* Get SoC name */
plat_get_soc_name(char * soc_name)588 int32_t plat_get_soc_name(char *soc_name)
589 {
590 snprintf(soc_name, SMCCC_SOC_NAME_LEN, "Arm Platform Revision %d",
591 plat_get_soc_revision());
592 return SMC_ARCH_CALL_SUCCESS;
593 }
594 #if ENABLE_RME
595
596 /* BDF mappings for RP0 RC0 */
597 const struct bdf_mapping_info rc0rp0_bdf_data[] = {
598 /* BDF0 */
599 {0U, /* mapping_base */
600 0x8000U, /* mapping_top */
601 0U, /* mapping_off */
602 0U /* smmu_idx */
603 }
604 };
605
606 /* Root ports for RC0 */
607 const struct root_port_info rc0rp_data[] = {
608 /* RP0 */
609 {0U, /* root_port_id */
610 0U, /* padding */
611 ARRAY_SIZE(rc0rp0_bdf_data), /* num_bdf_mappings */
612 (struct bdf_mapping_info *)rc0rp0_bdf_data /* bdf_mappings */
613 }
614 };
615
616 /* Root complexes */
617 const struct root_complex_info rc_data[] = {
618 /* RC0 */
619 {PCIE_EXP_BASE, /* ecam_base */
620 0U, /* segment */
621 {0U, 0U, 0U}, /* padding */
622 ARRAY_SIZE(rc0rp_data), /* num_root_ports */
623 (struct root_port_info *)rc0rp_data /* root_ports */
624 }
625 };
626
627 /* Number of PCIe Root Complexes */
628 #define FVP_RMM_RC_COUNT ARRAY_SIZE(rc_data)
629
630 /*
631 * Get a pointer to the RMM-EL3 Shared buffer and return it
632 * through the pointer passed as parameter.
633 *
634 * This function returns the size of the shared buffer.
635 */
plat_rmmd_get_el3_rmm_shared_mem(uintptr_t * shared)636 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
637 {
638 *shared = (uintptr_t)RMM_SHARED_BASE;
639
640 return (size_t)RMM_SHARED_SIZE;
641 }
642
643 /*
644 * Calculate checksum of 64-bit words @buffer with @size length
645 */
checksum_calc(uint64_t * buffer,size_t size)646 static uint64_t checksum_calc(uint64_t *buffer, size_t size)
647 {
648 uint64_t sum = 0UL;
649
650 assert(((uintptr_t)buffer & (sizeof(uint64_t) - 1UL)) == 0UL);
651 assert((size & (sizeof(uint64_t) - 1UL)) == 0UL);
652
653 for (unsigned long i = 0UL; i < (size / sizeof(uint64_t)); i++) {
654 sum += buffer[i];
655 }
656
657 return sum;
658 }
659 /*
660 * Boot Manifest v0.5 structure illustration, with two DRAM banks,
661 * a single console and one device memory with two PCIe device
662 * non-coherent address ranges.
663 *
664 * +--------------------------------------------------+
665 * | offset | field | comment |
666 * +--------+--------------------+--------------------+
667 * | 0 | version | 0x00000005 |
668 * +--------+--------------------+--------------------+
669 * | 4 | padding | 0x00000000 |
670 * +--------+--------------------+--------------------+
671 * | 8 | plat_data | NULL |
672 * +--------+--------------------+--------------------+
673 * | 16 | num_banks | |
674 * +--------+--------------------+ |
675 * | 24 | banks | plat_dram +--+
676 * +--------+--------------------+ | |
677 * | 32 | checksum | | |
678 * +--------+--------------------+--------------------+ |
679 * | 40 | num_consoles | | |
680 * +--------+--------------------+ | |
681 * | 48 | consoles | plat_console +--|--+
682 * +--------+--------------------+ | | |
683 * | 56 | checksum | | | |
684 * +--------+--------------------+--------------------+ | |
685 * | 64 | num_banks | | | |
686 * +--------+--------------------+ | | |
687 * | 72 | banks | plat_ncoh_region +--|--|--+
688 * +--------+--------------------+ | | | |
689 * | 80 | checksum | | | | |
690 * +--------+--------------------+--------------------+ | | |
691 * | 88 | num_banks | | | | |
692 * +--------+--------------------+ | | | |
693 * | 96 | banks | plat_coh_region | | | |
694 * +--------+--------------------+ | | | |
695 * | 104 | checksum | | | | |
696 * +--------+--------------------+--------------------+ | | |
697 * | 112 | num_smmus | | | | |
698 * +--------+--------------------+ | | | |
699 * | 120 | smmus | plat_smmu +--|--|--|--+
700 * +--------+--------------------+ | | | | |
701 * | 128 | checksum | | | | | |
702 * +--------+--------------------+--------------------+ | | | |
703 * | 136 | num_root_complex | | | | | |
704 * +--------+--------------------+ | | | | |
705 * | 144 | rc_info_version | | | | | |
706 * +--------+--------------------+ | | | | |
707 * | 148 | padding | plat_root_complex +--|--|--|--|--+
708 * +--------+--------------------+ | | | | | |
709 * | 152 | root_complex | | | | | | |
710 * +--------+--------------------+ | | | | | |
711 * | 160 | checksum | | | | | | |
712 * +--------+--------------------+--------------------+<-+ | | | |
713 * | 168 | base 0 | | | | | |
714 * +--------+--------------------+ mem_bank[0] | | | | |
715 * | 176 | size 0 | | | | | |
716 * +--------+--------------------+--------------------+ | | | |
717 * | 184 | base 1 | | | | | |
718 * +--------+--------------------+ mem_bank[1] | | | | |
719 * | 192 | size 1 | | | | | |
720 * +--------+--------------------+--------------------+<----+ | | |
721 * | 200 | base | | | | |
722 * +--------+--------------------+ | | | |
723 * | 208 | map_pages | | | | |
724 * +--------+--------------------+ | | | |
725 * | 216 | name | | | | |
726 * +--------+--------------------+ consoles[0] | | | |
727 * | 224 | clk_in_hz | | | | |
728 * +--------+--------------------+ | | | |
729 * | 232 | baud_rate | | | | |
730 * +--------+--------------------+ | | | |
731 * | 240 | flags | | | | |
732 * +--------+--------------------+--------------------+<-------+ | |
733 * | 248 | base 0 | | | |
734 * +--------+--------------------+ ncoh_region[0] | | |
735 * | 256 | size 0 | | | |
736 * +--------+--------------------+--------------------+ | |
737 * | 264 | base 1 | | | |
738 * +--------+--------------------+ ncoh_region[1] | | |
739 * | 272 | size 1 | | | |
740 * +--------+--------------------+--------------------+<----------+ |
741 * | 280 | smmu_base | | |
742 * +--------+--------------------+ smmus[0] | |
743 * | 288 | smmu_r_base | | |
744 * +--------+--------------------+--------------------+<-------------+
745 * | 296 | ecam_base | |
746 * +--------+--------------------+ |
747 * | 304 | segment | |
748 * +--------+--------------------+ |
749 * | 305 | padding | root_complex[0] +--+
750 * +--------+--------------------+ | |
751 * | 308 | num_root_ports | | |
752 * +--------+--------------------+ | |
753 * | 312 | root_ports | | |
754 * +--------+--------------------+--------------------+<-+
755 * | 320 | root_port_id | |
756 * +--------+--------------------+ |
757 * | 322 | padding | |
758 * +--------+--------------------+ root_ports[0] +--+
759 * | 324 | num_bdf_mappings | | |
760 * +--------+--------------------+ | |
761 * | 328 | bdf_mappings | | |
762 * +--------+--------------------+--------------------+<-+
763 * | 336 | mapping_base | |
764 * +--------+--------------------+ |
765 * | 338 | mapping_top | |
766 * +--------+--------------------+ bdf_mappings[0] |
767 * | 340 | mapping_off | |
768 * +--------+--------------------+ |
769 * | 342 | smmu_idx | |
770 * +--------+--------------------+--------------------+
771 */
plat_rmmd_load_manifest(struct rmm_manifest * manifest)772 int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
773 {
774 uint64_t checksum, num_banks, num_consoles;
775 uint64_t num_ncoh_regions, num_coh_regions;
776 uint64_t num_smmus, num_root_complex;
777 unsigned int num_root_ports, num_bdf_mappings;
778 uint32_t o_realm;
779 struct memory_bank *bank_ptr, *ncoh_region_ptr, *coh_region_ptr;
780 struct console_info *console_ptr;
781 struct smmu_info *smmu_ptr;
782 struct root_complex_info *root_complex_ptr, *rc_ptr;
783 struct root_port_info *root_port_ptr, *rp_ptr;
784 struct bdf_mapping_info *bdf_mapping_ptr, *bdf_ptr;
785
786 assert(manifest != NULL);
787
788 /* Get number of DRAM banks */
789 num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks);
790 assert(num_banks <= ARM_DRAM_NUM_BANKS);
791
792 /* Set number of consoles */
793 num_consoles = FVP_RMM_CONSOLE_COUNT;
794
795 /* Set number of device non-coherent address ranges for FVP RevC */
796 num_ncoh_regions = 2;
797
798 /* Set number of SMMUs */
799 num_smmus = FVP_RMM_SMMU_COUNT;
800
801 /* Set number of PCIe root complexes */
802 num_root_complex = FVP_RMM_RC_COUNT;
803
804 /* Calculate and set number of all PCIe root ports and BDF mappings */
805 num_root_ports = 0U;
806 num_bdf_mappings = 0U;
807
808 /* Scan all root complex entries */
809 for (unsigned long i = 0UL; i < num_root_complex; i++) {
810 num_root_ports += rc_data[i].num_root_ports;
811
812 /* Scan all root ports entries in root complex */
813 for (unsigned int j = 0U; j < rc_data[i].num_root_ports; j++) {
814 num_bdf_mappings += rc_data[i].root_ports[j].num_bdf_mappings;
815 }
816 }
817
818 manifest->version = RMMD_MANIFEST_VERSION;
819 manifest->padding = 0U; /* RES0 */
820 manifest->plat_data = 0UL;
821 manifest->plat_dram.num_banks = num_banks;
822 manifest->plat_console.num_consoles = num_consoles;
823 manifest->plat_ncoh_region.num_banks = num_ncoh_regions;
824 manifest->plat_smmu.num_smmus = num_smmus;
825 manifest->plat_root_complex.num_root_complex = num_root_complex;
826 manifest->plat_root_complex.rc_info_version = PCIE_RC_INFO_VERSION;
827 manifest->plat_root_complex.padding = 0U; /* RES0 */
828
829 /* FVP does not support device coherent address ranges */
830 num_coh_regions = 0UL;
831 manifest->plat_coh_region.num_banks = num_coh_regions;
832 manifest->plat_coh_region.banks = NULL;
833 manifest->plat_coh_region.checksum = 0UL;
834
835 bank_ptr = (struct memory_bank *)
836 (((uintptr_t)manifest) + sizeof(struct rmm_manifest));
837 console_ptr = (struct console_info *)
838 ((uintptr_t)bank_ptr + (num_banks *
839 sizeof(struct memory_bank)));
840 ncoh_region_ptr = (struct memory_bank *)
841 ((uintptr_t)console_ptr + (num_consoles *
842 sizeof(struct console_info)));
843 coh_region_ptr = (struct memory_bank *)
844 ((uintptr_t)ncoh_region_ptr + (num_ncoh_regions *
845 sizeof(struct memory_bank)));
846 smmu_ptr = (struct smmu_info *)
847 ((uintptr_t)coh_region_ptr + (num_coh_regions *
848 sizeof(struct memory_bank)));
849 root_complex_ptr = (struct root_complex_info *)
850 ((uintptr_t)smmu_ptr + (num_smmus *
851 sizeof(struct smmu_info)));
852 root_port_ptr = (struct root_port_info *)
853 ((uintptr_t)root_complex_ptr + (num_root_complex *
854 sizeof(struct root_complex_info)));
855 bdf_mapping_ptr = (struct bdf_mapping_info *)
856 ((uintptr_t)root_port_ptr + (num_root_ports *
857 sizeof(struct root_port_info)));
858
859 manifest->plat_dram.banks = bank_ptr;
860 manifest->plat_console.consoles = console_ptr;
861 manifest->plat_ncoh_region.banks = ncoh_region_ptr;
862 manifest->plat_smmu.smmus = smmu_ptr;
863 manifest->plat_root_complex.root_complex = root_complex_ptr;
864
865 /* Ensure the manifest is not larger than the shared buffer */
866 assert((sizeof(struct rmm_manifest) +
867 (sizeof(struct memory_bank) *
868 manifest->plat_dram.num_banks) +
869 (sizeof(struct console_info) *
870 manifest->plat_console.num_consoles) +
871 (sizeof(struct memory_bank) *
872 manifest->plat_ncoh_region.num_banks) +
873 (sizeof(struct memory_bank) *
874 manifest->plat_coh_region.num_banks) +
875 (sizeof(struct smmu_info) *
876 manifest->plat_smmu.num_smmus) +
877 (sizeof(struct root_complex_info) *
878 manifest->plat_root_complex.num_root_complex) +
879 (sizeof(struct root_port_info) * num_root_ports) +
880 (sizeof(struct bdf_mapping_info) * num_bdf_mappings))
881 <= ARM_EL3_RMM_SHARED_SIZE);
882
883 /* Calculate checksum of plat_dram structure */
884 checksum = num_banks + (uint64_t)bank_ptr;
885
886 /* Store FVP DRAM banks data in Boot Manifest */
887 for (unsigned long i = 0UL; i < num_banks; i++) {
888 bank_ptr[i].base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base);
889 bank_ptr[i].size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size);
890 }
891
892 /* Update checksum */
893 checksum += checksum_calc((uint64_t *)bank_ptr, sizeof(struct memory_bank) * num_banks);
894
895 /* Checksum must be 0 */
896 manifest->plat_dram.checksum = ~checksum + 1UL;
897
898 /* Calculate the checksum of plat_consoles structure */
899 checksum = num_consoles + (uint64_t)console_ptr;
900
901 /* Zero out the console info struct */
902 (void)memset((void *)console_ptr, '\0',
903 sizeof(struct console_info) * num_consoles);
904
905 console_ptr[0].base = FVP_RMM_CONSOLE_BASE;
906 console_ptr[0].map_pages = 1UL;
907 console_ptr[0].clk_in_hz = FVP_RMM_CONSOLE_CLK_IN_HZ;
908 console_ptr[0].baud_rate = FVP_RMM_CONSOLE_BAUD;
909
910 (void)strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME,
911 RMM_CONSOLE_MAX_NAME_LEN - 1UL);
912
913 /* Update checksum */
914 checksum += checksum_calc((uint64_t *)console_ptr,
915 sizeof(struct console_info) * num_consoles);
916 /* Checksum must be 0 */
917 manifest->plat_console.checksum = ~checksum + 1UL;
918
919 /*
920 * Calculate the checksum of device non-coherent address ranges
921 * info structure
922 */
923 checksum = num_ncoh_regions + (uint64_t)ncoh_region_ptr;
924
925 /* Zero out the PCIe region info struct */
926 (void)memset((void *)ncoh_region_ptr, 0,
927 sizeof(struct memory_bank) * num_ncoh_regions);
928
929 /* Set number of device non-coherent address ranges based on DT */
930 num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
931 /* At least 1 PCIe region need to be described in DT */
932 assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
933
934 for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
935 ncoh_region_ptr[i].base =
936 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
937 ncoh_region_ptr[i].size =
938 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
939 }
940
941 /*
942 * Workaround if the DT does not specify the 2nd PCIe region. This code can be
943 * removed when upstream DT is updated to have 2nd PCIe region.
944 */
945 if (num_ncoh_regions == 1) {
946 num_ncoh_regions++;
947 /* Add 3GB of 2nd PCIe region */
948 ncoh_region_ptr[1].base = 0x4000000000;
949 ncoh_region_ptr[1].size = 0xc0000000;
950 }
951
952 /* Update checksum */
953 checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
954 sizeof(struct memory_bank) * num_ncoh_regions);
955
956 /* Checksum must be 0 */
957 manifest->plat_ncoh_region.checksum = ~checksum + 1UL;
958
959 /* Calculate the checksum of the plat_smmu structure */
960 checksum = num_smmus + (uint64_t)smmu_ptr;
961
962 smmu_ptr[0].smmu_base = FVP_RMM_SMMU_BASE;
963
964 /* Read SMMU_ROOT_IDR0.BA_REALM[31:22] register field */
965 o_realm = mmio_read_32(FVP_RMM_SMMU_BASE + SMMU_ROOT_IDR0) &
966 SMMU_ROOT_IDR0_BA_REALM_MASK;
967 /*
968 * Calculate the base address offset of Realm Register Page 0.
969 * O_REALM = 0x20000 + (BA_REALM * 0x10000)
970 * SMMU_REALM_BASE = SMMU_PAGE_0_BASE + O_REALM
971 */
972 o_realm = 0x20000 + (o_realm >> (SMMU_ROOT_IDR0_BA_REALM_SHIFT - 16U));
973
974 smmu_ptr[0].smmu_r_base = FVP_RMM_SMMU_BASE + o_realm;
975
976 /* Update checksum */
977 checksum += checksum_calc((uint64_t *)smmu_ptr,
978 sizeof(struct smmu_info) * num_smmus);
979 /* Checksum must be 0 */
980 manifest->plat_smmu.checksum = ~checksum + 1UL;
981
982 /* Calculate the checksum of the plat_root_complex structure */
983 checksum = num_root_complex + (uint64_t)root_complex_ptr;
984
985 /* Zero out PCIe root complex info structures */
986 (void)memset((void *)root_complex_ptr, 0,
987 sizeof(struct root_complex_info) * num_root_complex);
988
989 /* Set pointers for data in manifest */
990 rc_ptr = root_complex_ptr;
991 rp_ptr = root_port_ptr;
992 bdf_ptr = bdf_mapping_ptr;
993
994 /* Fill PCIe root complex info structures */
995 for (unsigned long i = 0U; i < num_root_complex; i++) {
996 const struct root_complex_info *rc_info = &rc_data[i];
997 const struct root_port_info *rp_info = rc_info->root_ports;
998
999 /* Copy root complex data, except root_ports pointer */
1000 (void)memcpy((void *)rc_ptr, (void *)rc_info,
1001 sizeof(struct root_complex_info) - sizeof(struct root_port_info *));
1002
1003 /* Set root_ports for root complex */
1004 rc_ptr->root_ports = rp_ptr;
1005
1006 /* Scan root ports */
1007 for (unsigned int j = 0U; j < rc_ptr->num_root_ports; j++) {
1008 const struct bdf_mapping_info *bdf_info = rp_info->bdf_mappings;
1009
1010 /* Copy root port data, except bdf_mappings pointer */
1011 (void)memcpy((void *)rp_ptr, (void *)rp_info,
1012 sizeof(struct root_port_info) - sizeof(struct bdf_mapping_info *));
1013
1014 /* Set bdf_mappings for root port */
1015 rp_ptr->bdf_mappings = bdf_ptr;
1016
1017 /* Copy all BDF mappings for root port */
1018 (void)memcpy((void *)bdf_ptr, (void *)bdf_info,
1019 sizeof(struct bdf_mapping_info) * rp_ptr->num_bdf_mappings);
1020
1021 bdf_ptr += rp_ptr->num_bdf_mappings;
1022 rp_ptr++;
1023 rp_info++;
1024 }
1025 rc_ptr++;
1026 }
1027
1028 /* Check that all data are written in manifest */
1029 assert(rc_ptr == (root_complex_ptr + num_root_complex));
1030 assert(rp_ptr == (root_port_ptr + num_root_ports));
1031 assert(bdf_ptr == (bdf_mapping_ptr + num_bdf_mappings));
1032
1033 /* Update checksum for all PCIe data */
1034 checksum += checksum_calc((uint64_t *)root_complex_ptr,
1035 (uintptr_t)bdf_ptr - (uintptr_t)root_complex_ptr);
1036
1037 /* Checksum must be 0 */
1038 manifest->plat_root_complex.checksum = ~checksum + 1UL;
1039
1040 return 0;
1041 }
1042
1043 /*
1044 * Update encryption key associated with @mecid.
1045 */
plat_rmmd_mecid_key_update(uint16_t mecid,unsigned int reason)1046 int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason)
1047 {
1048 /*
1049 * FVP does not provide an interface to change the encryption key associated
1050 * with MECID. Hence always return success.
1051 */
1052 return 0;
1053 }
1054 #endif /* ENABLE_RME */
1055