fix(dcc): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(dcc): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Iba1627367d9bb8c2f5e4a9d45de96dd891356abc
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signe

feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I39e366ed1988847bfa288adc0732d9b864e58bbd

show more ...

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I7a2565ce6b8beb71dc9c711327ab72ce825111cc
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge "fix(mhu): shift by minor revision offset" into integration

Merge "feat(dsu): support power control and autonomous powerdown config" into integration

fix(arm-drivers): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o

fix(arm-drivers): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I6464ba742af81a2fffe9782d032275486d32f3a1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

show more ...

feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-

feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and trig

feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and triggers as well as to map the config frame in device
nGnRnE memory. All wires will default to the NS domain and the platform
can override this.

Change-Id: I93aec5809aec4328d1cba832c2c6e5891e398e5b
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to m

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to map the config frame in device nGnRnE
memory. All wires will default to NS and the platform may override this.

Change-Id: Icbd43503753cd76fd3d80ed47eba6926494bc323
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux t

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux to fully boot.
This is expected to be fully replaced with context management when
adding world switching support as some of these are expected to be
shared between worlds.

Change-Id: I59a7b5a63f878c9a717ef81e977be7133a402f3f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the nec

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.

Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.

Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support fo

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.

This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.

No actual functionality yet.

Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(mhu): shift by minor revision offset

Fix version check in mhu_v3_x_driver_init swapping
MHU_ARCH_MINOR_REV_MASK by MHU_ARCH_MINOR_REV_OFF as hinted by coverity:

(1) Event result_independent_of_

fix(mhu): shift by minor revision offset

Fix version check in mhu_v3_x_driver_init swapping
MHU_ARCH_MINOR_REV_MASK by MHU_ARCH_MINOR_REV_OFF as hinted by coverity:

(1) Event result_independent_of_operands:
"(aidr & (15U /* 0xfU << 0U */)) >> (15U /* 0xfU << 0U */)" is 0
regardless of the values of its operands. This occurs as the operand
of assignment.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4307ae0fdc48831dade983a040671730369377ff

show more ...

fix(gic): quote the correct flag on error

Generic GIC driver files should use the USE_GIC_DRIVER flag. When that's
not the case, the correct flag should be quotes to avoid confusion.

Change-Id: I0b

fix(gic): quote the correct flag on error

Generic GIC driver files should use the USE_GIC_DRIVER flag. When that's
not the case, the correct flag should be quotes to avoid confusion.

Change-Id: I0b0443d52c0b0e81d7b380285a278ffdeae17ca3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

chore: fix preprocessor checks

We can also drop the preprocessor check from plat_gic_init - it was
introduced because the tsp needed to call this function on gicv2 but not
gicv3 and this was the cle

chore: fix preprocessor checks

We can also drop the preprocessor check from plat_gic_init - it was
introduced because the tsp needed to call this function on gicv2 but not
gicv3 and this was the cleanest way to filter this out. Now that we have
the generic driver, the caller has all the tools to cater for this.
Callers have been converted so this is redundant.

Also, the FVP observes different behaviour on debug and release builds
in regards to the contents of plat_params_from_bl2. Make this explicit
so that release builds with ENABLE_ASSERTIONS=1 are possible.

Change-Id: I86959e67460d0c25c558f33c08e6233a8b6eeb7f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - c

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - calling
the top-level helpers from plat/arm/common/arm_gicvX.c or by using the
driver directly. Both of these methods allow for a high degree of
customisation - most functions are defined to be weak and there are no
calls to any of them in generic code.

As it turns out, requirements around those GICs are largely the same.
Platforms that use arm_gicvX.c use the helpers identically among each
other. Platforms that use the driver directly tend to end up with calls
that look a lot like the arm_gicvX.c helpers and the weakness of the
functions are never exercised.

All of this results in a lot of code duplication to do what is
essentially the same thing. Even though it's not a lot of code, when
multiplied among many platforms it becomes significant and makes
refactoring it quite difficult. It's also bug prone since the steps are
a little convoluted and things are likely to work even with subtle
errors (see 50009f61177421118f42d6a000611ba0e613d54b).

So promote as much of the GIC to be called from common code. Do the
setup in bl31_main() and have every PSCI method do the state management
directly instead of delegating it to the platform hooks. We can base
this implementation on arm_gicvX.c since they already offer logical
names and have worked quite well so far with minimal changes.

The main benefit of doing this is reduced code duplication. If we assume
that, outside of some platform setup, GIC management is identical, then
a platform can add support by telling the build system, regardless of
GIC revision. The other benefit is performance - BL31 and PSCI already
know the core_pos and they can pass it as an argument instead of having
to call plat_my_core_pos(). Now, the only platform specific GIC actions
necessary are the saving and restoring of context on entering and
exiting a power domain. The PSCI library does not keep track of this so
it is unable perform it itself. The routines themselves are also
provided.

For compatibility all of this is hidden behind a build flag. Platforms
are encouraged to adopt this driver, but it would not be practical to
convert and validate every GIC based platform.

This patch renames the functions in question to follow the
gic_<function>() convention. This allows the names to be version
agnostic.

Finally, drop the weak definitions - they are unused, likely to remain
so, and can be added back if the need arises.

Change-Id: I5b5267f4b72f633fb1096400ec8e4b208694135f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(arm-drivers): typecast expressions to match data type

This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall hav

fix(arm-drivers): typecast expressions to match data type

This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I1500e2b3628313e68f94bce701a057b80bc2f933
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(arm-drivers): align essential type categories

This corrects the MISRA violation C2012-10.7:
If a composite expression is used as one operand of an operator in
which the usual arithmetic conversi

fix(arm-drivers): align essential type categories

This corrects the MISRA violation C2012-10.7:
If a composite expression is used as one operand of an operator in
which the usual arithmetic conversions are performed then the other
operand shall not have wider essential type.
Explicitly type casted to match the data type of both the operands.

Change-Id: I89fef817ad672f310de9bc0e93646cd2ba04793b
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(arm-drivers): typecast expression to match data type

This corrects the MISRA violation C2012-10.6:
The value of a composite expression shall not be assigned to
an object with wider essential typ

fix(arm-drivers): typecast expression to match data type

This corrects the MISRA violation C2012-10.6:
The value of a composite expression shall not be assigned to
an object with wider essential type.
Explicitly type casted to match the data type of composite
expression.

Change-Id: I2ec044ff7fd7a8d0cdc8db5f71f30872fb8d9e81
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement

fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I66f957467bdee13052847f3e8c5ad6ae258c4222
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add suppo

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add support for local chip addressing

show more ...

refactor(rse)!: remove rse_comms_init

The function to use is now rse_mbx_init(), that does the same if
using MHU.

Change-Id: I712712d7d1bcd8c96d26951e176b877afb65209d
Signed-off-by: Yann Gautier <y

refactor(rse)!: remove rse_comms_init

The function to use is now rse_mbx_init(), that does the same if
using MHU.

Change-Id: I712712d7d1bcd8c96d26951e176b877afb65209d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

refactor(rse): put MHU code in a dedicated file

To be able to use RSE comms without MHU, a first step is to disentangle
the rse_comms.c file with MHU code direct calls. This is done with the
creatio

refactor(rse): put MHU code in a dedicated file

To be able to use RSE comms without MHU, a first step is to disentangle
the rse_comms.c file with MHU code direct calls. This is done with the
creation of a new file rse_comms_mhu.c. New APIs are created to
initialize the mailbox, get max message size and send and receive data.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I75dda77e1886beaa6ced6f92c311617125918cfa

show more ...