1 /* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV5_H 8 #define GICV5_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stdbool.h> 12 #include <stdint.h> 13 #endif 14 15 #include <lib/utils_def.h> 16 17 /* Interrupt Domain definitions */ 18 #define INTDMN_S 0 19 #define INTDMN_NS 1 20 #define INTDMN_EL3 2 21 #define INTDMN_RL 3 22 23 /* Trigger modes */ 24 #define TM_EDGE 0 25 #define TM_LEVEL 1 26 27 /* Architected PPI numbers */ 28 #define PPI_TRBIRQ 31 29 #define PPI_CNTP 30 30 #define PPI_CNTPS 29 31 #define PPI_CNTHV 28 32 #define PPI_CNTV 27 33 #define PPI_CNTHP 26 34 #define PPI_GICMNT 25 35 #define PPI_CTIIRQ 24 36 #define PPI_PMUIRQ 23 37 #define PPI_COMMIRQ 22 38 #define PPI_PMBIRQ 21 39 #define PPI_CNTHPS 20 40 #define PPI_CNTHVS 19 41 #define PPI_DB_NS 2 42 #define PPI_DB_RL 1 43 #define PPI_DB_S 0 44 45 #ifndef __ASSEMBLER__ 46 47 #define _PPI_FIELD_SHIFT(_REG, _ppi_id) \ 48 ((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT)) 49 50 #define write_icc_ppi_domainr(_var, _ppi_id, _value) \ 51 do { \ 52 _var |= (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\ 53 } while (false) 54 55 struct gicv5_driver_data { 56 }; 57 58 extern const struct gicv5_driver_data plat_gicv5_driver_data; 59 60 void gicv5_driver_init(); 61 uint8_t gicv5_get_pending_interrupt_type(void); 62 bool gicv5_has_interrupt_type(unsigned int type); 63 void gicv5_enable_ppis(); 64 #endif /* __ASSEMBLER__ */ 65 #endif /* GICV5_H */ 66