1 /* 2 * Copyright (c) 2019, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal PM nodes enums and defines */ 9 10 #ifndef PM_NODE_H 11 #define PM_NODE_H 12 13 /********************************************************************* 14 * Macro definitions 15 ********************************************************************/ 16 17 #define NODE_CLASS_SHIFT 26U 18 #define NODE_SUBCLASS_SHIFT 20U 19 #define NODE_TYPE_SHIFT 14U 20 #define NODE_INDEX_SHIFT 0U 21 #define NODE_CLASS_MASK_BITS GENMASK_32(5, 0) 22 #define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0) 23 #define NODE_TYPE_MASK_BITS GENMASK_32(5, 0) 24 #define NODE_INDEX_MASK_BITS GENMASK_32(13, 0) 25 #define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT) 26 27 #define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \ 28 ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \ 29 (((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \ 30 (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \ 31 (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT)) 32 33 #define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT) 34 35 /********************************************************************* 36 * Enum definitions 37 ********************************************************************/ 38 39 /* Node class types */ 40 enum pm_node_class { 41 XPM_NODECLASS_MIN, 42 43 XPM_NODECLASS_POWER, 44 XPM_NODECLASS_CLOCK, 45 XPM_NODECLASS_RESET, 46 XPM_NODECLASS_MEMIC, 47 XPM_NODECLASS_STMIC, 48 XPM_NODECLASS_DEVICE, 49 50 XPM_NODECLASS_MAX 51 }; 52 53 enum pm_device_node_subclass { 54 /* Device types */ 55 XPM_NODESUBCL_DEV_CORE = 1, 56 XPM_NODESUBCL_DEV_PERIPH, 57 XPM_NODESUBCL_DEV_MEM, 58 XPM_NODESUBCL_DEV_SOC, 59 XPM_NODESUBCL_DEV_MEM_CTRLR, 60 XPM_NODESUBCL_DEV_PHY, 61 }; 62 63 enum pm_device_node_type { 64 /* Device types */ 65 XPM_NODETYPE_DEV_CORE_PMC = 1, 66 XPM_NODETYPE_DEV_CORE_PSM, 67 XPM_NODETYPE_DEV_CORE_APU, 68 XPM_NODETYPE_DEV_CORE_RPU, 69 XPM_NODETYPE_DEV_OCM, 70 XPM_NODETYPE_DEV_TCM, 71 XPM_NODETYPE_DEV_L2CACHE, 72 XPM_NODETYPE_DEV_DDR, 73 XPM_NODETYPE_DEV_PERIPH, 74 XPM_NODETYPE_DEV_SOC, 75 XPM_NODETYPE_DEV_GT, 76 }; 77 78 /* Device node Indexes */ 79 enum pm_device_node_idx { 80 /* Device nodes */ 81 XPM_NODEIDX_DEV_MIN = 0x0, 82 83 /* Processor devices */ 84 XPM_NODEIDX_DEV_PMC_PROC = 0x1, 85 XPM_NODEIDX_DEV_PSM_PROC = 0x2, 86 XPM_NODEIDX_DEV_ACPU_0 = 0x3, 87 XPM_NODEIDX_DEV_ACPU_1 = 0x4, 88 XPM_NODEIDX_DEV_RPU0_0 = 0x5, 89 XPM_NODEIDX_DEV_RPU0_1 = 0x6, 90 91 /* Memory devices */ 92 XPM_NODEIDX_DEV_OCM_0 = 0x7, 93 XPM_NODEIDX_DEV_OCM_1 = 0x8, 94 XPM_NODEIDX_DEV_OCM_2 = 0x9, 95 XPM_NODEIDX_DEV_OCM_3 = 0xA, 96 XPM_NODEIDX_DEV_TCM_0_A = 0xB, 97 XPM_NODEIDX_DEV_TCM_0_B = 0xC, 98 XPM_NODEIDX_DEV_TCM_1_A = 0xD, 99 XPM_NODEIDX_DEV_TCM_1_B = 0xE, 100 XPM_NODEIDX_DEV_L2_BANK_0 = 0xF, 101 XPM_NODEIDX_DEV_DDR_0 = 0x10, 102 XPM_NODEIDX_DEV_DDR_1 = 0x11, 103 XPM_NODEIDX_DEV_DDR_2 = 0x12, 104 XPM_NODEIDX_DEV_DDR_3 = 0x13, 105 XPM_NODEIDX_DEV_DDR_4 = 0x14, 106 XPM_NODEIDX_DEV_DDR_5 = 0x15, 107 XPM_NODEIDX_DEV_DDR_6 = 0x16, 108 XPM_NODEIDX_DEV_DDR_7 = 0x17, 109 110 /* LPD Peripheral devices */ 111 XPM_NODEIDX_DEV_USB_0 = 0x18, 112 XPM_NODEIDX_DEV_GEM_0 = 0x19, 113 XPM_NODEIDX_DEV_GEM_1 = 0x1A, 114 XPM_NODEIDX_DEV_SPI_0 = 0x1B, 115 XPM_NODEIDX_DEV_SPI_1 = 0x1C, 116 XPM_NODEIDX_DEV_I2C_0 = 0x1D, 117 XPM_NODEIDX_DEV_I2C_1 = 0x1E, 118 XPM_NODEIDX_DEV_CAN_FD_0 = 0x1F, 119 XPM_NODEIDX_DEV_CAN_FD_1 = 0x20, 120 XPM_NODEIDX_DEV_UART_0 = 0x21, 121 XPM_NODEIDX_DEV_UART_1 = 0x22, 122 XPM_NODEIDX_DEV_GPIO = 0x23, 123 XPM_NODEIDX_DEV_TTC_0 = 0x24, 124 XPM_NODEIDX_DEV_TTC_1 = 0x25, 125 XPM_NODEIDX_DEV_TTC_2 = 0x26, 126 XPM_NODEIDX_DEV_TTC_3 = 0x27, 127 XPM_NODEIDX_DEV_SWDT_LPD = 0x28, 128 XPM_NODEIDX_DEV_I2C_2 = 0x117, 129 XPM_NODEIDX_DEV_I2C_3 = 0x118, 130 XPM_NODEIDX_DEV_I2C_4 = 0x119, 131 XPM_NODEIDX_DEV_I2C_5 = 0x11A, 132 XPM_NODEIDX_DEV_I2C_6 = 0x11B, 133 XPM_NODEIDX_DEV_I2C_7 = 0x11C, 134 XPM_NODEIDX_DEV_CAN_FD_2 = 0x11D, 135 XPM_NODEIDX_DEV_CAN_FD_3 = 0x11E, 136 XPM_NODEIDX_DEV_TTC_4 = 0x11F, 137 XPM_NODEIDX_DEV_TTC_5 = 0x120, 138 XPM_NODEIDX_DEV_TTC_6 = 0x121, 139 XPM_NODEIDX_DEV_TTC_7 = 0x122, 140 141 /* FPD Peripheral devices */ 142 XPM_NODEIDX_DEV_SWDT_FPD = 0x29, 143 144 /* PMC Peripheral devices */ 145 XPM_NODEIDX_DEV_OSPI = 0x2A, 146 XPM_NODEIDX_DEV_QSPI = 0x2B, 147 XPM_NODEIDX_DEV_GPIO_PMC = 0x2C, 148 XPM_NODEIDX_DEV_I2C_PMC = 0x2D, 149 XPM_NODEIDX_DEV_SDIO_0 = 0x2E, 150 XPM_NODEIDX_DEV_SDIO_1 = 0x2F, 151 152 XPM_NODEIDX_DEV_PL_0 = 0x30, 153 XPM_NODEIDX_DEV_PL_1 = 0x31, 154 XPM_NODEIDX_DEV_PL_2 = 0x32, 155 XPM_NODEIDX_DEV_PL_3 = 0x33, 156 XPM_NODEIDX_DEV_RTC = 0x34, 157 XPM_NODEIDX_DEV_ADMA_0 = 0x35, 158 XPM_NODEIDX_DEV_ADMA_1 = 0x36, 159 XPM_NODEIDX_DEV_ADMA_2 = 0x37, 160 XPM_NODEIDX_DEV_ADMA_3 = 0x38, 161 XPM_NODEIDX_DEV_ADMA_4 = 0x39, 162 XPM_NODEIDX_DEV_ADMA_5 = 0x3A, 163 XPM_NODEIDX_DEV_ADMA_6 = 0x3B, 164 XPM_NODEIDX_DEV_ADMA_7 = 0x3C, 165 XPM_NODEIDX_DEV_IPI_0 = 0x3D, 166 XPM_NODEIDX_DEV_IPI_1 = 0x3E, 167 XPM_NODEIDX_DEV_IPI_2 = 0x3F, 168 XPM_NODEIDX_DEV_IPI_3 = 0x40, 169 XPM_NODEIDX_DEV_IPI_4 = 0x41, 170 XPM_NODEIDX_DEV_IPI_5 = 0x42, 171 XPM_NODEIDX_DEV_IPI_6 = 0x43, 172 173 /* Entire SoC */ 174 XPM_NODEIDX_DEV_SOC = 0x44, 175 176 /* DDR memory controllers */ 177 XPM_NODEIDX_DEV_DDRMC_0 = 0x45, 178 XPM_NODEIDX_DEV_DDRMC_1 = 0x46, 179 XPM_NODEIDX_DEV_DDRMC_2 = 0x47, 180 XPM_NODEIDX_DEV_DDRMC_3 = 0x48, 181 182 /* GT devices */ 183 XPM_NODEIDX_DEV_GT_0 = 0x49, 184 XPM_NODEIDX_DEV_GT_1 = 0x4A, 185 XPM_NODEIDX_DEV_GT_2 = 0x4B, 186 XPM_NODEIDX_DEV_GT_3 = 0x4C, 187 XPM_NODEIDX_DEV_GT_4 = 0x4D, 188 XPM_NODEIDX_DEV_GT_5 = 0x4E, 189 XPM_NODEIDX_DEV_GT_6 = 0x4F, 190 XPM_NODEIDX_DEV_GT_7 = 0x50, 191 XPM_NODEIDX_DEV_GT_8 = 0x51, 192 XPM_NODEIDX_DEV_GT_9 = 0x52, 193 XPM_NODEIDX_DEV_GT_10 = 0x53, 194 195 #if defined(PLAT_versal_net) 196 XPM_NODEIDX_DEV_ACPU_0_0 = 0xAF, 197 XPM_NODEIDX_DEV_ACPU_0_1 = 0xB0, 198 XPM_NODEIDX_DEV_ACPU_0_2 = 0xB1, 199 XPM_NODEIDX_DEV_ACPU_0_3 = 0xB2, 200 XPM_NODEIDX_DEV_ACPU_1_0 = 0xB3, 201 XPM_NODEIDX_DEV_ACPU_1_1 = 0xB4, 202 XPM_NODEIDX_DEV_ACPU_1_2 = 0xB5, 203 XPM_NODEIDX_DEV_ACPU_1_3 = 0xB6, 204 XPM_NODEIDX_DEV_ACPU_2_0 = 0xB7, 205 XPM_NODEIDX_DEV_ACPU_2_1 = 0xB8, 206 XPM_NODEIDX_DEV_ACPU_2_2 = 0xB9, 207 XPM_NODEIDX_DEV_ACPU_2_3 = 0xBA, 208 XPM_NODEIDX_DEV_ACPU_3_0 = 0xBB, 209 XPM_NODEIDX_DEV_ACPU_3_1 = 0xBC, 210 XPM_NODEIDX_DEV_ACPU_3_2 = 0xBD, 211 XPM_NODEIDX_DEV_ACPU_3_3 = 0xBE, 212 XPM_NODEIDX_DEV_RPU_A_0 = 0xBF, 213 XPM_NODEIDX_DEV_RPU_A_1 = 0xC0, 214 XPM_NODEIDX_DEV_RPU_B_0 = 0xC1, 215 XPM_NODEIDX_DEV_RPU_B_1 = 0xC2, 216 XPM_NODEIDX_DEV_OCM_0_0 = 0xC3, 217 XPM_NODEIDX_DEV_OCM_0_1 = 0xC4, 218 XPM_NODEIDX_DEV_OCM_0_2 = 0xC5, 219 XPM_NODEIDX_DEV_OCM_0_3 = 0xC6, 220 XPM_NODEIDX_DEV_OCM_1_0 = 0xC7, 221 XPM_NODEIDX_DEV_OCM_1_1 = 0xC8, 222 XPM_NODEIDX_DEV_OCM_1_2 = 0xC9, 223 XPM_NODEIDX_DEV_OCM_1_3 = 0xCA, 224 XPM_NODEIDX_DEV_TCM_A_0A = 0xCB, 225 XPM_NODEIDX_DEV_TCM_A_0B = 0xCC, 226 XPM_NODEIDX_DEV_TCM_A_0C = 0xCD, 227 XPM_NODEIDX_DEV_TCM_A_1A = 0xCE, 228 XPM_NODEIDX_DEV_TCM_A_1B = 0xCF, 229 XPM_NODEIDX_DEV_TCM_A_1C = 0xD0, 230 XPM_NODEIDX_DEV_TCM_B_0A = 0xD1, 231 XPM_NODEIDX_DEV_TCM_B_0B = 0xD2, 232 XPM_NODEIDX_DEV_TCM_B_0C = 0xD3, 233 XPM_NODEIDX_DEV_TCM_B_1A = 0xD4, 234 XPM_NODEIDX_DEV_TCM_B_1B = 0xD5, 235 XPM_NODEIDX_DEV_TCM_B_1C = 0xD6, 236 XPM_NODEIDX_DEV_USB_1 = 0xD7, 237 XPM_NODEIDX_DEV_PMC_WWDT = 0xD8, 238 XPM_NODEIDX_DEV_LPD_SWDT_0 = 0xD9, 239 XPM_NODEIDX_DEV_LPD_SWDT_1 = 0xDA, 240 XPM_NODEIDX_DEV_FPD_SWDT_0 = 0xDB, 241 XPM_NODEIDX_DEV_FPD_SWDT_1 = 0xDC, 242 XPM_NODEIDX_DEV_FPD_SWDT_2 = 0xDD, 243 XPM_NODEIDX_DEV_FPD_SWDT_3 = 0xDE, 244 #endif 245 246 #if defined(PLAT_versal2) 247 XPM_NODEIDX_DEV_USB_1 = 0xD7, 248 #endif 249 250 XPM_NODEIDX_DEV_MAX, 251 }; 252 253 #endif /* PM_NODE_H */ 254