1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 /* Protected physical address size */ 59 #define PLAT_ARM_PPS (SZ_1T) 60 #endif /* ENABLE_RME */ 61 62 /* 63 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 64 * max size of BL32 image. 65 */ 66 #if defined(SPD_spmd) 67 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 68 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 69 #endif 70 71 /* Virtual address used by dynamic mem_protect for chunk_base */ 72 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 73 74 /* No SCP in FVP */ 75 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 76 77 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 78 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 79 80 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 81 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 82 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 83 84 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 85 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 86 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 87 88 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 89 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 90 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 91 92 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 93 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 94 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 95 96 /* 97 * On the FVP platform when using the EL3 SPMC implementation allocate the 98 * datastore for tracking shared memory descriptors in the TZC DRAM section 99 * to ensure sufficient storage can be allocated. 100 * Provide an implementation of the accessor method to allow the datastore 101 * details to be retrieved by the SPMC. 102 * The SPMC will take care of initializing the memory region. 103 */ 104 105 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 106 107 /* Define memory configuration for device tree files. */ 108 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 109 110 #if SPMC_AT_EL3 111 /* 112 * Number of Secure Partitions supported. 113 * SPMC at EL3, uses this count to configure the maximum number of supported 114 * secure partitions. 115 */ 116 #define SECURE_PARTITION_COUNT 1 117 118 /* 119 * Number of Normal World Partitions supported. 120 * SPMC at EL3, uses this count to configure the maximum number of supported 121 * NWd partitions. 122 */ 123 #define NS_PARTITION_COUNT 1 124 125 /* 126 * Number of Logical Partitions supported. 127 * SPMC at EL3, uses this count to configure the maximum number of supported 128 * logical partitions. 129 */ 130 #define MAX_EL3_LP_DESCS_COUNT 1 131 132 #endif /* SPMC_AT_EL3 */ 133 134 /* 135 * Load address of BL33 for this platform port 136 */ 137 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 138 139 #if TRANSFER_LIST 140 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000) 141 142 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 143 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 144 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 145 146 #if RESET_TO_BL31 147 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 148 #endif 149 150 #else 151 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 152 #endif 153 154 /* 155 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 156 * plat_arm_mmap array defined for each BL stage. 157 */ 158 #if defined(IMAGE_BL31) 159 # if SPM_MM 160 # define PLAT_ARM_MMAP_ENTRIES 10 161 # define MAX_XLAT_TABLES 9 162 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 163 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 164 # elif SPMC_AT_EL3 165 # define PLAT_ARM_MMAP_ENTRIES 13 166 # define MAX_XLAT_TABLES 11 167 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 168 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 169 # else 170 # define PLAT_ARM_MMAP_ENTRIES 9 171 # if USE_DEBUGFS 172 # if ENABLE_RME 173 # define MAX_XLAT_TABLES 9 174 # else 175 # define MAX_XLAT_TABLES 8 176 # endif 177 # else 178 # if ENABLE_RME 179 # define MAX_XLAT_TABLES 8 180 # elif DRTM_SUPPORT 181 # define MAX_XLAT_TABLES 8 182 # else 183 # define MAX_XLAT_TABLES 7 184 # endif 185 # endif 186 # endif 187 #elif defined(IMAGE_BL32) 188 # if SPMC_AT_EL3 189 # define PLAT_ARM_MMAP_ENTRIES 270 190 # define MAX_XLAT_TABLES 10 191 # else 192 # define PLAT_ARM_MMAP_ENTRIES 9 193 # define MAX_XLAT_TABLES 6 194 # endif 195 #elif !USE_ROMLIB 196 # if ENABLE_RME && defined(IMAGE_BL2) 197 # define PLAT_ARM_MMAP_ENTRIES 12 198 # define MAX_XLAT_TABLES 6 199 # else 200 # define PLAT_ARM_MMAP_ENTRIES 12 201 # define MAX_XLAT_TABLES 5 202 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 203 #else 204 # define PLAT_ARM_MMAP_ENTRIES 12 205 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 206 defined(IMAGE_BL2) && MEASURED_BOOT 207 # define MAX_XLAT_TABLES 7 208 # else 209 # define MAX_XLAT_TABLES 6 210 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 211 #endif 212 213 /* 214 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 215 * plus a little space for growth. 216 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 217 * area. 218 */ 219 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 220 FVP_TRUSTED_SRAM_SIZE == 512 221 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 222 #else 223 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 224 #endif 225 226 /* 227 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 228 */ 229 230 #if USE_ROMLIB 231 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 232 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 233 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 234 #else 235 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 236 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 237 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 238 #endif 239 240 /* 241 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 242 * Maximum size of BL2 increases as Trusted SRAM size increases. 243 */ 244 #if CRYPTO_SUPPORT 245 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 246 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 247 (2 * PAGE_SIZE) - \ 248 FVP_BL2_ROMLIB_OPTIMIZATION) 249 #else 250 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 251 (3 * PAGE_SIZE) - \ 252 FVP_BL2_ROMLIB_OPTIMIZATION) 253 #endif 254 #elif ARM_BL31_IN_DRAM 255 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 256 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 257 #else 258 /** 259 * Default to just under half of SRAM to ensure there's enough room for really 260 * large BL31 build configurations when using the default SRAM size (256 Kb). 261 */ 262 #define PLAT_ARM_MAX_BL2_SIZE \ 263 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 264 FVP_BL2_ROMLIB_OPTIMIZATION) 265 #endif 266 267 #if RESET_TO_BL31 268 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 269 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 270 ARM_SHARED_RAM_SIZE - \ 271 ARM_L0_GPT_SIZE) 272 #else 273 /* 274 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 275 * calculated using the current BL31 PROGBITS debug size plus the sizes of 276 * BL2 and BL1-RW. 277 * Size of the BL31 PROGBITS increases as the SRAM size increases. 278 */ 279 #if TRANSFER_LIST 280 #define PLAT_ARM_MAX_BL31_SIZE \ 281 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 282 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 283 #else 284 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 285 ARM_SHARED_RAM_SIZE - \ 286 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 287 #endif /* TRANSFER_LIST */ 288 #endif /* RESET_TO_BL31 */ 289 290 #ifndef __aarch64__ 291 #if RESET_TO_SP_MIN 292 /* Size of Trusted SRAM - the first 4KB of shared memory */ 293 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 294 ARM_SHARED_RAM_SIZE) 295 #else 296 /* 297 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 298 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 299 * BL2 and BL1-RW 300 */ 301 #if TRANSFER_LIST 302 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 303 ARM_SHARED_RAM_SIZE - \ 304 PLAT_ARM_FW_HANDOFF_SIZE) 305 #else 306 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 307 ARM_SHARED_RAM_SIZE - \ 308 ARM_FW_CONFIGS_SIZE) 309 #endif /* TRANSFER_LIST */ 310 #endif /* RESET_TO_SP_MIN */ 311 #endif 312 313 /* 314 * Size of cacheable stacks 315 */ 316 #if defined(IMAGE_BL1) 317 # if CRYPTO_SUPPORT 318 # define PLATFORM_STACK_SIZE UL(0x1000) 319 # else 320 # define PLATFORM_STACK_SIZE UL(0x500) 321 # endif /* CRYPTO_SUPPORT */ 322 #elif defined(IMAGE_BL2) 323 # if CRYPTO_SUPPORT 324 # define PLATFORM_STACK_SIZE UL(0x1000) 325 # else 326 # define PLATFORM_STACK_SIZE UL(0x600) 327 # endif /* CRYPTO_SUPPORT */ 328 #elif defined(IMAGE_BL2U) 329 # define PLATFORM_STACK_SIZE UL(0x400) 330 #elif defined(IMAGE_BL31) 331 # if DRTM_SUPPORT 332 # define PLATFORM_STACK_SIZE UL(0x1000) 333 # else 334 # define PLATFORM_STACK_SIZE UL(0x800) 335 # endif /* DRTM_SUPPORT */ 336 #elif defined(IMAGE_BL32) 337 # if SPMC_AT_EL3 338 # define PLATFORM_STACK_SIZE UL(0x1000) 339 # else 340 # define PLATFORM_STACK_SIZE UL(0x440) 341 # endif /* SPMC_AT_EL3 */ 342 #elif defined(IMAGE_RMM) 343 # define PLATFORM_STACK_SIZE UL(0x440) 344 #endif 345 346 #define MAX_IO_DEVICES 3 347 #define MAX_IO_HANDLES 4 348 349 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 350 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 351 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 352 353 #if ARM_GPT_SUPPORT 354 /* 355 * Offset of the FIP in the GPT image. BL1 component uses this option 356 * as it does not load the partition table to get the FIP base 357 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 358 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 359 */ 360 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 361 #endif /* ARM_GPT_SUPPORT */ 362 363 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 364 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 365 366 /* 367 * PL011 related constants 368 */ 369 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 370 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 371 372 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 373 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 374 375 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 376 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 377 378 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 379 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 380 381 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 382 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 383 384 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 385 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 386 387 /* CCI related constants */ 388 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 389 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 390 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 391 392 /* CCI-500/CCI-550 on Base platform */ 393 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 394 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 395 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 396 397 /* CCN related constants. Only CCN 502 is currently supported */ 398 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 399 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 400 401 /* System timer related constants */ 402 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 403 404 /* Mailbox base address */ 405 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 406 407 /* PCIe memory region 1 (Base Platform RevC only) */ 408 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 409 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 410 411 /* 412 * PCIe memory region 2 (Base Platform RevC only) 413 * The full size of the second PCI memory region is 256GB 414 * but for now we only allocate the L1 GPTs for the first 3GB. 415 */ 416 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 417 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 418 419 /* TrustZone controller related constants 420 * 421 * Currently only filters 0 and 2 are connected on Base FVP. 422 * Filter 0 : CPU clusters (no access to DRAM by default) 423 * Filter 1 : not connected 424 * Filter 2 : LCDs (access to VRAM allowed by default) 425 * Filter 3 : not connected 426 * Programming unconnected filters will have no effect at the 427 * moment. These filter could, however, be connected in future. 428 * So care should be taken not to configure the unused filters. 429 * 430 * Allow only non-secure access to all DRAM to supported devices. 431 * Give access to the CPUs and Virtio. Some devices 432 * would normally use the default ID so allow that too. 433 */ 434 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 435 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 436 437 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 438 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 439 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 440 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 441 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 442 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 443 444 /* 445 * GIC related constants to cater for both GICv2 and GICv3 instances of an 446 * FVP. They could be overridden at runtime in case the FVP implements the 447 * legacy VE memory map. 448 */ 449 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 450 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 451 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 452 453 /* 454 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 455 * terminology. On a GICv2 system or mode, the lists will be merged and treated 456 * as Group 0 interrupts. 457 */ 458 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 459 ARM_G1S_IRQ_PROPS(grp), \ 460 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 461 GIC_INTR_CFG_LEVEL), \ 462 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 463 GIC_INTR_CFG_LEVEL) 464 465 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 466 467 #if SDEI_IN_FCONF 468 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 469 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 470 #else 471 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 472 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 473 ARM_SDEI_PRIVATE_EVENTS, \ 474 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 475 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 476 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 477 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 478 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 479 #else 480 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 481 #endif 482 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 483 #endif 484 485 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 486 PLAT_SP_IMAGE_NS_BUF_SIZE) 487 488 #define PLAT_SP_PRI 0x20 489 490 /* 491 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 492 */ 493 #ifdef __aarch64__ 494 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 495 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 496 #else 497 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 498 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 499 #endif 500 501 /* 502 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 503 * TODO: calculate maximum EventLog size using the calculation: 504 * Maximum size of Event Log * Number of images 505 */ 506 #if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed))) 507 /* 508 * Account for additional measurements of secure partitions and SPM. 509 * Also, account for OP-TEE running with maximum number of SPs. 510 */ 511 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 512 #elif defined(IMAGE_BL1) && TRANSFER_LIST 513 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 514 #else 515 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 516 #endif 517 518 /* 519 * Maximum size of Event Log buffer used for DRTM 520 */ 521 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 522 523 /* 524 * Number of MMAP entries used by DRTM implementation 525 */ 526 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 527 528 #endif /* PLATFORM_DEF_H */ 529