1 /* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <cdefs.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 13 #include <bl31/interrupt_mgmt.h> 14 #include <common/debug.h> 15 #include <drivers/arm/gicv5.h> 16 17 void __init gicv5_driver_init(void) 18 { 19 } 20 21 /* 22 * There exists a theoretical configuration where FEAT_RME is enabled 23 * without using TrustZone (i.e., no Secure world present). Currently, 24 * there is no reliable mechanism to detect this scenario at runtime. 25 * 26 * TODO: Add support for this configuration in the future if required. 27 */ 28 bool gicv5_has_interrupt_type(unsigned int type) 29 { 30 switch (type) { 31 case INTR_TYPE_EL3: 32 case INTR_TYPE_S_EL1: 33 case INTR_TYPE_NS: 34 return true; 35 case INTR_TYPE_RL: 36 return is_feat_rme_supported(); 37 default: 38 return false; 39 } 40 } 41 42 uint8_t gicv5_get_pending_interrupt_type(void) 43 { 44 /* there is no pending interrupt expected */ 45 return INTR_TYPE_INVAL; 46 } 47 48 /* TODO: these will probably end up contexted. Make Linux work for now */ 49 void gicv5_enable_ppis(void) 50 { 51 uint64_t domainr = 0U; 52 53 /* the only ones described in the device tree at the moment */ 54 write_icc_ppi_domainr(domainr, PPI_PMUIRQ, INTDMN_NS); 55 write_icc_ppi_domainr(domainr, PPI_GICMNT, INTDMN_NS); 56 write_icc_ppi_domainr(domainr, PPI_CNTHP, INTDMN_NS); 57 write_icc_ppi_domainr(domainr, PPI_CNTV, INTDMN_NS); 58 write_icc_ppi_domainr(domainr, PPI_CNTPS, INTDMN_NS); 59 write_icc_ppi_domainr(domainr, PPI_CNTP, INTDMN_NS); 60 61 write_icc_ppi_domainr0_el3(domainr); 62 } 63