1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #include <drivers/st/stm32mp2_clk.h> 14 #endif 15 #if STM32MP21 16 #include <drivers/st/stm32mp21_pwr.h> 17 #include <drivers/st/stm32mp21_rcc.h> 18 #else /* STM32MP21 */ 19 #include <drivers/st/stm32mp2_pwr.h> 20 #include <drivers/st/stm32mp25_rcc.h> 21 #endif /* STM32MP21 */ 22 #if STM32MP21 23 #include <dt-bindings/clock/st,stm32mp21-rcc.h> 24 #include <dt-bindings/clock/stm32mp21-clksrc.h> 25 #include <dt-bindings/reset/st,stm32mp21-rcc.h> 26 #endif /* STM32MP21 */ 27 #if STM32MP23 28 #include <dt-bindings/clock/stm32mp25-clks.h> 29 #include <dt-bindings/clock/stm32mp25-clksrc.h> 30 #include <dt-bindings/reset/stm32mp25-resets.h> 31 #endif /* STM32MP23 */ 32 #if STM32MP25 33 #include <dt-bindings/clock/stm32mp25-clks.h> 34 #include <dt-bindings/clock/stm32mp25-clksrc.h> 35 #include <dt-bindings/reset/stm32mp25-resets.h> 36 #endif /* STM32MP25 */ 37 #include <dt-bindings/gpio/stm32-gpio.h> 38 39 #ifndef __ASSEMBLER__ 40 #include <boot_api.h> 41 #include <stm32mp2_private.h> 42 #include <stm32mp_common.h> 43 #include <stm32mp_dt.h> 44 #include <stm32mp_shared_resources.h> 45 #endif 46 47 /******************************************************************************* 48 * CHIP ID 49 ******************************************************************************/ 50 #define STM32MP2_CHIP_ID U(0x505) 51 52 #define STM32MP251A_PART_NB U(0x400B3E6D) 53 #define STM32MP251C_PART_NB U(0x000B306D) 54 #define STM32MP251D_PART_NB U(0xC00B3E6D) 55 #define STM32MP251F_PART_NB U(0x800B306D) 56 #define STM32MP253A_PART_NB U(0x400B3E0C) 57 #define STM32MP253C_PART_NB U(0x000B300C) 58 #define STM32MP253D_PART_NB U(0xC00B3E0C) 59 #define STM32MP253F_PART_NB U(0x800B300C) 60 #define STM32MP255A_PART_NB U(0x40082E00) 61 #define STM32MP255C_PART_NB U(0x00082000) 62 #define STM32MP255D_PART_NB U(0xC0082E00) 63 #define STM32MP255F_PART_NB U(0x80082000) 64 #define STM32MP257A_PART_NB U(0x40002E00) 65 #define STM32MP257C_PART_NB U(0x00002000) 66 #define STM32MP257D_PART_NB U(0xC0002E00) 67 #define STM32MP257F_PART_NB U(0x80002000) 68 69 #define STM32MP2_REV_A U(0x08) 70 #define STM32MP2_REV_B U(0x10) 71 #define STM32MP2_REV_X U(0x12) 72 #define STM32MP2_REV_Y U(0x11) 73 #define STM32MP2_REV_Z U(0x09) 74 75 /******************************************************************************* 76 * PACKAGE ID 77 ******************************************************************************/ 78 #define STM32MP25_PKG_CUSTOM U(0) 79 #define STM32MP25_PKG_AL_VFBGA361 U(1) 80 #define STM32MP25_PKG_AK_VFBGA424 U(3) 81 #define STM32MP25_PKG_AI_TFBGA436 U(5) 82 #define STM32MP25_PKG_UNKNOWN U(7) 83 84 /******************************************************************************* 85 * STM32MP2 memory map related constants 86 ******************************************************************************/ 87 #define STM32MP_SYSRAM_BASE U(0x0E000000) 88 #define STM32MP_SYSRAM_SIZE U(0x00040000) 89 #define SRAM1_BASE U(0x0E040000) 90 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 91 #define RETRAM_BASE U(0x0E080000) 92 #define RETRAM_SIZE U(0x00020000) 93 94 /* DDR configuration */ 95 #define STM32MP_DDR_BASE U(0x80000000) 96 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 97 98 /* DDR power initializations */ 99 #ifndef __ASSEMBLER__ 100 enum ddr_type { 101 STM32MP_DDR3, 102 STM32MP_DDR4, 103 STM32MP_LPDDR4 104 }; 105 #endif 106 107 /* Section used inside TF binaries */ 108 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 109 /* 512 Bytes reserved for header */ 110 #define STM32MP_HEADER_SIZE U(0x00000200) 111 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 112 STM32MP_PARAM_LOAD_SIZE) 113 114 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 115 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 116 117 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 118 STM32MP_PARAM_LOAD_SIZE + \ 119 STM32MP_HEADER_SIZE) 120 121 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 122 (STM32MP_PARAM_LOAD_SIZE + \ 123 STM32MP_HEADER_SIZE)) 124 125 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 126 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 127 128 /* Allocate remaining sysram to BL31 Binary only */ 129 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \ 130 STM32MP_BL2_SIZE) 131 132 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 133 STM32MP_SYSRAM_SIZE - \ 134 STM32MP_BL2_SIZE) 135 136 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 137 138 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 139 STM32MP_BL2_RO_SIZE) 140 141 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 142 STM32MP_SYSRAM_SIZE - \ 143 STM32MP_BL2_RW_BASE) 144 145 /* BL2 and BL32/sp_min require 4 tables */ 146 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 147 148 /* 149 * MAX_MMAP_REGIONS is usually: 150 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 151 */ 152 #if defined(IMAGE_BL31) 153 #define MAX_MMAP_REGIONS 7 154 #else 155 #define MAX_MMAP_REGIONS 6 156 #endif 157 158 /* DTB initialization value */ 159 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 160 161 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 162 STM32MP_BL2_DTB_SIZE) 163 164 #if defined(IMAGE_BL2) 165 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 166 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 167 #endif 168 169 #if STM32MP_DDR_FIP_IO_STORAGE 170 #define STM32MP_DDR_FW_BASE SRAM1_BASE 171 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) 172 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) 173 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 174 #endif 175 176 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 177 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 178 179 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 180 #define STM32MP_BL33_MAX_SIZE U(0x400000) 181 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 182 STM32MP_BL33_MAX_SIZE) 183 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 184 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */ 185 186 /******************************************************************************* 187 * STM32MP2 device/io map related constants (used for MMU) 188 ******************************************************************************/ 189 #define STM32MP_DEVICE_BASE U(0x40000000) 190 #define STM32MP_DEVICE_SIZE U(0x40000000) 191 192 /******************************************************************************* 193 * STM32MP2 RCC 194 ******************************************************************************/ 195 #define RCC_BASE U(0x44200000) 196 197 /******************************************************************************* 198 * STM32MP2 PWR 199 ******************************************************************************/ 200 #define PWR_BASE U(0x44210000) 201 202 /******************************************************************************* 203 * STM32MP2 GPIO 204 ******************************************************************************/ 205 #define GPIOA_BASE U(0x44240000) 206 #define GPIOB_BASE U(0x44250000) 207 #define GPIOC_BASE U(0x44260000) 208 #define GPIOD_BASE U(0x44270000) 209 #define GPIOE_BASE U(0x44280000) 210 #define GPIOF_BASE U(0x44290000) 211 #define GPIOG_BASE U(0x442A0000) 212 #define GPIOH_BASE U(0x442B0000) 213 #define GPIOI_BASE U(0x442C0000) 214 #define GPIOJ_BASE U(0x442D0000) 215 #define GPIOK_BASE U(0x442E0000) 216 #define GPIOZ_BASE U(0x46200000) 217 #define GPIO_BANK_OFFSET U(0x10000) 218 219 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 220 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 221 222 /******************************************************************************* 223 * STM32MP2 UART 224 ******************************************************************************/ 225 #define USART1_BASE U(0x40330000) 226 #define USART2_BASE U(0x400E0000) 227 #define USART3_BASE U(0x400F0000) 228 #define UART4_BASE U(0x40100000) 229 #define UART5_BASE U(0x40110000) 230 #define USART6_BASE U(0x40220000) 231 #define UART7_BASE U(0x40370000) 232 #define UART8_BASE U(0x40380000) 233 #define UART9_BASE U(0x402C0000) 234 #define STM32MP_NB_OF_UART U(9) 235 236 /* For UART crash console */ 237 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 238 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 239 #ifdef ULTRA_FLY 240 #define STM32MP_DEBUG_USART_BASE USART1_BASE 241 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 242 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 243 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 244 #define DEBUG_UART_TX_GPIO_PORT 3 245 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 246 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 247 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 248 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR 249 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 250 #define DEBUG_UART_RST_REG RCC_USART1CFGR 251 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 252 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR 253 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR 254 #else 255 #define STM32MP_DEBUG_USART_BASE USART2_BASE 256 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 257 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 258 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 259 #define DEBUG_UART_TX_GPIO_PORT 4 260 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 261 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 262 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 263 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 264 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 265 #define DEBUG_UART_RST_REG RCC_USART2CFGR 266 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 267 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 268 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 269 #endif 270 271 /******************************************************************************* 272 * STM32MP2 SDMMC 273 ******************************************************************************/ 274 #define STM32MP_SDMMC1_BASE U(0x48220000) 275 #define STM32MP_SDMMC2_BASE U(0x48230000) 276 #define STM32MP_SDMMC3_BASE U(0x48240000) 277 278 /******************************************************************************* 279 * STM32MP2 BSEC / OTP 280 ******************************************************************************/ 281 /* 282 * 367 available OTPs, the other are masked 283 * - ECIES key: 368 to 375 (only readable by bootrom) 284 * - HWKEY: 376 to 383 (never reloadable or readable) 285 */ 286 #define STM32MP2_OTP_MAX_ID U(0x16F) 287 #define STM32MP2_MID_OTP_START U(0x80) 288 #define STM32MP2_UPPER_OTP_START U(0x100) 289 290 /* OTP labels */ 291 #define PART_NUMBER_OTP "part-number-otp" 292 #define REVISION_OTP "rev_otp" 293 #define PACKAGE_OTP "package-otp" 294 #define HCONF1_OTP "otp124" 295 #define NAND_OTP "otp16" 296 #define NAND2_OTP "otp20" 297 #define BOARD_ID_OTP "board-id" 298 #define UID_OTP "uid-otp" 299 #define LIFECYCLE2_OTP "otp18" 300 #define PKH_OTP "otp144" 301 #define ENCKEY_OTP "otp260" 302 303 /* OTP mask */ 304 /* PACKAGE */ 305 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 306 #define PACKAGE_OTP_PKG_SHIFT U(0) 307 308 /* IWDG OTP */ 309 #define HCONF1_OTP_IWDG_HW_POS U(0) 310 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 311 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 312 313 /* NAND OTP */ 314 /* NAND parameter storage flag */ 315 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 316 317 /* NAND page size in bytes */ 318 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 319 #define NAND_PAGE_SIZE_SHIFT U(29) 320 #define NAND_PAGE_SIZE_2K U(0) 321 #define NAND_PAGE_SIZE_4K U(1) 322 #define NAND_PAGE_SIZE_8K U(2) 323 324 /* NAND block size in pages */ 325 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 326 #define NAND_BLOCK_SIZE_SHIFT U(27) 327 #define NAND_BLOCK_SIZE_64_PAGES U(0) 328 #define NAND_BLOCK_SIZE_128_PAGES U(1) 329 #define NAND_BLOCK_SIZE_256_PAGES U(2) 330 331 /* NAND number of block (in unit of 256 blocks) */ 332 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 333 #define NAND_BLOCK_NB_SHIFT U(19) 334 #define NAND_BLOCK_NB_UNIT U(256) 335 336 /* NAND bus width in bits */ 337 #define NAND_WIDTH_MASK BIT_32(18) 338 #define NAND_WIDTH_SHIFT U(18) 339 340 /* NAND number of ECC bits per 512 bytes */ 341 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 342 #define NAND_ECC_BIT_NB_SHIFT U(15) 343 #define NAND_ECC_BIT_NB_UNSET U(0) 344 #define NAND_ECC_BIT_NB_1_BITS U(1) 345 #define NAND_ECC_BIT_NB_4_BITS U(2) 346 #define NAND_ECC_BIT_NB_8_BITS U(3) 347 #define NAND_ECC_ON_DIE U(4) 348 349 /* NAND number of planes */ 350 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 351 352 /* NAND2 OTP */ 353 #define NAND2_PAGE_SIZE_SHIFT U(16) 354 355 /* NAND2 config distribution */ 356 #define NAND2_CONFIG_DISTRIB BIT_32(0) 357 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 358 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 359 360 /* MONOTONIC OTP */ 361 #define MAX_MONOTONIC_VALUE U(32) 362 363 /* UID OTP */ 364 #define UID_WORD_NB U(3) 365 366 /* Lifecycle OTP */ 367 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 368 369 /******************************************************************************* 370 * STM32MP2 TAMP 371 ******************************************************************************/ 372 #define PLAT_MAX_TAMP_INT U(5) 373 #define PLAT_MAX_TAMP_EXT U(3) 374 #define TAMP_BASE U(0x46010000) 375 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 376 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 377 #define TAMP_BKP_REG_CLK CK_BUS_RTC 378 #define TAMP_BKP_SEC_NUMBER U(10) 379 #define TAMP_COUNTR U(0x40) 380 381 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 382 static inline uintptr_t tamp_bkpr(uint32_t idx) 383 { 384 return TAMP_BKP_REGISTER_BASE + (idx << 2); 385 } 386 #endif 387 388 /******************************************************************************* 389 * STM32MP2 DDRCTRL 390 ******************************************************************************/ 391 #define DDRCTRL_BASE U(0x48040000) 392 393 /******************************************************************************* 394 * STM32MP2 DDRDBG 395 ******************************************************************************/ 396 #define DDRDBG_BASE U(0x48050000) 397 398 /******************************************************************************* 399 * STM32MP2 DDRPHYC 400 ******************************************************************************/ 401 #define DDRPHYC_BASE U(0x48C00000) 402 403 /******************************************************************************* 404 * Miscellaneous STM32MP2 peripherals base address 405 ******************************************************************************/ 406 #define BSEC_BASE U(0x44000000) 407 #define DBGMCU_BASE U(0x4A010000) 408 #define HASH_BASE U(0x42010000) 409 #define RTC_BASE U(0x46000000) 410 #define STGEN_BASE U(0x48080000) 411 #define SYSCFG_BASE U(0x44230000) 412 413 /******************************************************************************* 414 * STM32MP RIF 415 ******************************************************************************/ 416 #define RISAB3_BASE U(0x42110000) 417 #define RISAB5_BASE U(0x42130000) 418 419 /******************************************************************************* 420 * STM32MP CA35SSC 421 ******************************************************************************/ 422 #define A35SSC_BASE U(0x48800000) 423 424 /******************************************************************************* 425 * REGULATORS 426 ******************************************************************************/ 427 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 428 #define PLAT_NB_RDEVS U(19) 429 /* 2 FIXED */ 430 #define PLAT_NB_FIXED_REGUS U(2) 431 /* No GPIO regu */ 432 #define PLAT_NB_GPIO_REGUS U(0) 433 434 /******************************************************************************* 435 * Device Tree defines 436 ******************************************************************************/ 437 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 438 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 439 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 440 #if STM32MP21 441 #define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc" 442 #else 443 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 444 #endif 445 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 446 #define DT_UART_COMPAT "st,stm32h7-uart" 447 448 #endif /* STM32MP2_DEF_H */ 449