1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <lib/debugfs.h> 16 #include <lib/extensions/ras.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/mmio.h> 20 #if TRANSFER_LIST 21 #include <lib/transfer_list.h> 22 #endif 23 #include <lib/xlat_tables/xlat_tables_compat.h> 24 #include <plat/arm/common/plat_arm.h> 25 #include <plat/common/platform.h> 26 #include <platform_def.h> 27 28 struct transfer_list_header *secure_tl; 29 struct transfer_list_header *ns_tl __unused; 30 31 /* 32 * Placeholder variables for copying the arguments that have been passed to 33 * BL31 from BL2. 34 */ 35 static entry_point_info_t bl32_image_ep_info; 36 static entry_point_info_t bl33_image_ep_info; 37 38 #if ENABLE_RME 39 static entry_point_info_t rmm_image_ep_info; 40 #if (RME_GPT_BITLOCK_BLOCK == 0) 41 #define BITLOCK_BASE UL(0) 42 #define BITLOCK_SIZE UL(0) 43 #else 44 /* 45 * Number of bitlock_t entries in bitlocks array for PLAT_ARM_PPS 46 * with RME_GPT_BITLOCK_BLOCK * 512MB per bitlock. 47 */ 48 #if (PLAT_ARM_PPS > (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8))) 49 #define BITLOCKS_NUM (PLAT_ARM_PPS) / \ 50 (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8)) 51 #else 52 #define BITLOCKS_NUM U(1) 53 #endif 54 /* 55 * Bitlocks array 56 */ 57 static bitlock_t gpt_bitlock[BITLOCKS_NUM]; 58 #define BITLOCK_BASE (uintptr_t)gpt_bitlock 59 #define BITLOCK_SIZE sizeof(gpt_bitlock) 60 #endif /* RME_GPT_BITLOCK_BLOCK */ 61 #endif /* ENABLE_RME */ 62 63 #if !RESET_TO_BL31 64 /* 65 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 66 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 67 */ 68 #if TRANSFER_LIST 69 CASSERT(BL31_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl31_base_overflows); 70 #else 71 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 72 #endif /* TRANSFER_LIST */ 73 #endif /* RESET_TO_BL31 */ 74 75 /* Weak definitions may be overridden in specific ARM standard platform */ 76 #pragma weak bl31_early_platform_setup2 77 #pragma weak bl31_platform_setup 78 #pragma weak bl31_plat_arch_setup 79 #pragma weak bl31_plat_get_next_image_ep_info 80 #pragma weak bl31_plat_runtime_setup 81 82 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 83 BL31_START, \ 84 BL31_END - BL31_START, \ 85 MT_MEMORY | MT_RW | EL3_PAS) 86 #if RECLAIM_INIT_CODE 87 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 88 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 89 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 90 91 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 92 ~(PAGE_SIZE - 1)) 93 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 94 ~(PAGE_SIZE - 1)) 95 96 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 97 BL_INIT_CODE_BASE, \ 98 BL_INIT_CODE_END \ 99 - BL_INIT_CODE_BASE, \ 100 MT_CODE | EL3_PAS) 101 #endif 102 103 #if SEPARATE_NOBITS_REGION 104 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 105 BL31_NOBITS_BASE, \ 106 BL31_NOBITS_LIMIT \ 107 - BL31_NOBITS_BASE, \ 108 MT_MEMORY | MT_RW | EL3_PAS) 109 110 #endif 111 /******************************************************************************* 112 * Return a pointer to the 'entry_point_info' structure of the next image for the 113 * security state specified. BL33 corresponds to the non-secure image type 114 * while BL32 corresponds to the secure image type. A NULL pointer is returned 115 * if the image does not exist. 116 ******************************************************************************/ 117 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 118 { 119 entry_point_info_t *next_image_info; 120 121 assert(sec_state_is_valid(type)); 122 if (type == NON_SECURE) { 123 #if TRANSFER_LIST && !RESET_TO_BL31 124 next_image_info = transfer_list_set_handoff_args( 125 ns_tl, &bl33_image_ep_info); 126 #else 127 next_image_info = &bl33_image_ep_info; 128 #endif 129 } 130 #if ENABLE_RME 131 else if (type == REALM) { 132 next_image_info = &rmm_image_ep_info; 133 } 134 #endif 135 else { 136 next_image_info = &bl32_image_ep_info; 137 } 138 139 /* 140 * None of the images on the ARM development platforms can have 0x0 141 * as the entrypoint 142 */ 143 if (next_image_info->pc) 144 return next_image_info; 145 else 146 return NULL; 147 } 148 149 /******************************************************************************* 150 * Perform any BL31 early platform setup common to ARM standard platforms. 151 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 152 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 153 * done before the MMU is initialized so that the memory layout can be used 154 * while creating page tables. BL2 has flushed this information to memory, so 155 * we are guaranteed to pick up good data. 156 ******************************************************************************/ 157 void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 158 u_register_t arg2, u_register_t arg3) 159 { 160 #if TRANSFER_LIST 161 #if RESET_TO_BL31 162 /* Populate entry point information for BL33 */ 163 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 164 /* 165 * Tell BL31 where the non-trusted software image 166 * is located and the entry state information 167 */ 168 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 169 170 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 171 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 172 173 bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET; 174 bl33_image_ep_info.args.arg1 = 175 TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION); 176 bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE; 177 #else 178 struct transfer_list_entry *te = NULL; 179 struct entry_point_info *ep; 180 181 secure_tl = (struct transfer_list_header *)arg3; 182 183 /* 184 * Populate the global entry point structures used to execute subsequent 185 * images. 186 */ 187 while ((te = transfer_list_next(secure_tl, te)) != NULL) { 188 ep = transfer_list_entry_data(te); 189 190 if (te->tag_id == TL_TAG_EXEC_EP_INFO64) { 191 switch (GET_SECURITY_STATE(ep->h.attr)) { 192 case NON_SECURE: 193 bl33_image_ep_info = *ep; 194 break; 195 #if ENABLE_RME 196 case REALM: 197 rmm_image_ep_info = *ep; 198 break; 199 #endif 200 case SECURE: 201 bl32_image_ep_info = *ep; 202 break; 203 default: 204 ERROR("Unrecognized Image Security State %lu\n", 205 GET_SECURITY_STATE(ep->h.attr)); 206 panic(); 207 } 208 } 209 } 210 #endif /* RESET_TO_BL31 */ 211 #else /* (!TRANSFER_LIST) */ 212 #if RESET_TO_BL31 213 /* There are no parameters from BL2 if BL31 is a reset vector */ 214 assert((uintptr_t)arg0 == 0U); 215 assert((uintptr_t)arg3 == 0U); 216 217 # ifdef BL32_BASE 218 /* Populate entry point information for BL32 */ 219 SET_PARAM_HEAD(&bl32_image_ep_info, 220 PARAM_EP, 221 VERSION_1, 222 0); 223 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 224 bl32_image_ep_info.pc = BL32_BASE; 225 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 226 227 #if defined(SPD_spmd) 228 bl32_image_ep_info.args.arg0 = ARM_SPMC_MANIFEST_BASE; 229 #endif 230 231 # endif /* BL32_BASE */ 232 233 /* Populate entry point information for BL33 */ 234 SET_PARAM_HEAD(&bl33_image_ep_info, 235 PARAM_EP, 236 VERSION_1, 237 0); 238 /* 239 * Tell BL31 where the non-trusted software image 240 * is located and the entry state information 241 */ 242 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 243 244 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 245 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 246 247 #if ENABLE_RME 248 /* 249 * Populate entry point information for RMM. 250 * Only PC needs to be set as other fields are determined by RMMD. 251 */ 252 rmm_image_ep_info.pc = RMM_BASE; 253 #endif /* ENABLE_RME */ 254 #else /* RESET_TO_BL31 */ 255 /* 256 * In debug builds, we pass a special value in 'arg3' 257 * to verify platform parameters from BL2 to BL31. 258 * In release builds, it's not used. 259 */ 260 #if DEBUG 261 assert(((uintptr_t)arg3) == ARM_BL31_PLAT_PARAM_VAL); 262 #endif 263 264 /* 265 * Check params passed from BL2 should not be NULL, 266 */ 267 bl_params_t *params_from_bl2 = (bl_params_t *)(uintptr_t)arg0; 268 assert(params_from_bl2 != NULL); 269 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 270 assert(params_from_bl2->h.version >= VERSION_2); 271 272 bl_params_node_t *bl_params = params_from_bl2->head; 273 274 /* 275 * Copy BL33, BL32 and RMM (if present), entry point information. 276 * They are stored in Secure RAM, in BL2's address space. 277 */ 278 while (bl_params != NULL) { 279 if (bl_params->image_id == BL32_IMAGE_ID) { 280 bl32_image_ep_info = *bl_params->ep_info; 281 #if SPMC_AT_EL3 282 /* 283 * Populate the BL32 image base, size and max limit in 284 * the entry point information, since there is no 285 * platform function to retrieve them in generic 286 * code. We choose arg2, arg3 and arg4 since the generic 287 * code uses arg1 for stashing the SP manifest size. The 288 * SPMC setup uses these arguments to update SP manifest 289 * with actual SP's base address and it size. 290 */ 291 bl32_image_ep_info.args.arg2 = 292 bl_params->image_info->image_base; 293 bl32_image_ep_info.args.arg3 = 294 bl_params->image_info->image_size; 295 bl32_image_ep_info.args.arg4 = 296 bl_params->image_info->image_base + 297 bl_params->image_info->image_max_size; 298 #endif 299 } 300 #if ENABLE_RME 301 else if (bl_params->image_id == RMM_IMAGE_ID) { 302 rmm_image_ep_info = *bl_params->ep_info; 303 } 304 #endif 305 else if (bl_params->image_id == BL33_IMAGE_ID) { 306 bl33_image_ep_info = *bl_params->ep_info; 307 } 308 309 bl_params = bl_params->next_params_info; 310 } 311 312 if (bl33_image_ep_info.pc == 0U) 313 panic(); 314 #if ENABLE_RME 315 if (rmm_image_ep_info.pc == 0U) 316 panic(); 317 #endif 318 #endif /* RESET_TO_BL31 */ 319 320 #if ARM_LINUX_KERNEL_AS_BL33 321 /* 322 * According to the file ``Documentation/arm64/booting.txt`` of the 323 * Linux kernel tree, Linux expects the physical address of the device 324 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 325 * must be 0. 326 * Repurpose the option to load Hafnium hypervisor in the normal world. 327 * It expects its manifest address in x0. This is essentially the linux 328 * dts (passed to the primary VM) by adding 'hypervisor' and chosen 329 * nodes specifying the Hypervisor configuration. 330 */ 331 #if RESET_TO_BL31 332 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 333 #else 334 bl33_image_ep_info.args.arg0 = arg2; 335 #endif /* RESET_TO_BL31 */ 336 bl33_image_ep_info.args.arg1 = 0U; 337 bl33_image_ep_info.args.arg2 = 0U; 338 bl33_image_ep_info.args.arg3 = 0U; 339 #endif /* ARM_LINUX_KERNEL_AS_BL33 */ 340 #endif /* TRANSFER_LIST */ 341 } 342 343 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 344 u_register_t arg2, u_register_t arg3) 345 { 346 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 347 348 /* 349 * Initialize Interconnect for this cluster during cold boot. 350 * No need for locks as no other CPU is active. 351 */ 352 plat_arm_interconnect_init(); 353 354 /* 355 * Enable Interconnect coherency for the primary CPU's cluster. 356 * Earlier bootloader stages might already do this (e.g. Trusted 357 * Firmware's BL1 does it) but we can't assume so. There is no harm in 358 * executing this code twice anyway. 359 * Platform specific PSCI code will enable coherency for other 360 * clusters. 361 */ 362 plat_arm_interconnect_enter_coherency(); 363 } 364 365 /******************************************************************************* 366 * Perform any BL31 platform setup common to ARM standard platforms 367 ******************************************************************************/ 368 void arm_bl31_platform_setup(void) 369 { 370 struct transfer_list_entry *te __unused; 371 372 #if TRANSFER_LIST && !RESET_TO_BL31 373 ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, 374 PLAT_ARM_FW_HANDOFF_SIZE); 375 if (ns_tl == NULL) { 376 ERROR("Non-secure transfer list initialisation failed!\n"); 377 panic(); 378 } 379 /* BL31 may modify the HW_CONFIG so defer copying it until later. */ 380 te = transfer_list_find(secure_tl, TL_TAG_FDT); 381 assert(te != NULL); 382 383 /* 384 * A pre-existing assumption is that FCONF is unsupported w/ RESET_TO_BL2 and 385 * RESET_TO_BL31. In the case of RESET_TO_BL31 this makes sense because there 386 * isn't a prior stage to load the device tree, but the reasoning for RESET_TO_BL2 is 387 * less clear. For the moment hardware properties that would normally be 388 * derived from the DT are statically defined. 389 */ 390 #if !RESET_TO_BL2 391 fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te)); 392 #endif 393 394 te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size, 395 transfer_list_entry_data(te)); 396 assert(te != NULL); 397 #endif /* TRANSFER_LIST && !RESET_TO_BL31 */ 398 399 #if RESET_TO_BL31 400 /* 401 * Do initial security configuration to allow DRAM/device access 402 * (if earlier BL has not already done so). 403 */ 404 plat_arm_security_setup(); 405 406 #if defined(PLAT_ARM_MEM_PROT_ADDR) 407 arm_nor_psci_do_dyn_mem_protect(); 408 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 409 410 #endif /* RESET_TO_BL31 */ 411 412 /* Enable and initialize the System level generic timer */ 413 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 414 CNTCR_FCREQ(0U) | CNTCR_EN); 415 416 /* Allow access to the System counter timer module */ 417 arm_configure_sys_timer(); 418 419 /* Initialize power controller before setting up topology */ 420 plat_arm_pwrc_setup(); 421 422 #if ENABLE_FEAT_RAS && FFH_SUPPORT 423 ras_init(); 424 #endif 425 426 #if USE_DEBUGFS 427 debugfs_init(); 428 #endif /* USE_DEBUGFS */ 429 } 430 431 /******************************************************************************* 432 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 433 * standard platforms 434 ******************************************************************************/ 435 void arm_bl31_plat_runtime_setup(void) 436 { 437 struct transfer_list_entry *te __unused; 438 /* Initialize the runtime console */ 439 arm_console_runtime_init(); 440 441 #if TRANSFER_LIST && !RESET_TO_BL31 442 /* 443 * We assume BL31 has added all TE's required by BL33 at this stage, ensure 444 * that data is visible to all observers by performing a flush operation, so 445 * they can access the updated data even if caching is not enabled. 446 */ 447 flush_dcache_range((uintptr_t)ns_tl, ns_tl->size); 448 #endif /* TRANSFER_LIST && !RESET_TO_BL31 */ 449 450 #if RECLAIM_INIT_CODE 451 arm_free_init_memory(); 452 #endif 453 454 #if PLAT_RO_XLAT_TABLES 455 arm_xlat_make_tables_readonly(); 456 #endif 457 } 458 459 #if RECLAIM_INIT_CODE 460 /* 461 * Make memory for image boot time code RW to reclaim it as stack for the 462 * secondary cores, or RO where it cannot be reclaimed: 463 * 464 * |-------- INIT SECTION --------| 465 * ----------------------------------------- 466 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 467 * | STACK | STACK | STACK | SPACE | 468 * ----------------------------------------- 469 * <-------------------> <------> 470 * MAKE RW AND XN MAKE 471 * FOR STACKS RO AND XN 472 */ 473 void arm_free_init_memory(void) 474 { 475 int ret = 0; 476 477 if (BL_STACKS_END < BL_INIT_CODE_END) { 478 /* Reclaim some of the init section as stack if possible. */ 479 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 480 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 481 BL_STACKS_END - BL_INIT_CODE_BASE, 482 MT_RW_DATA); 483 } 484 /* Make the rest of the init section read-only. */ 485 ret |= xlat_change_mem_attributes(BL_STACKS_END, 486 BL_INIT_CODE_END - BL_STACKS_END, 487 MT_RO_DATA); 488 } else { 489 /* The stacks cover the init section, so reclaim it all. */ 490 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 491 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 492 MT_RW_DATA); 493 } 494 495 if (ret != 0) { 496 ERROR("Could not reclaim initialization code"); 497 panic(); 498 } 499 } 500 #endif 501 502 void __init bl31_platform_setup(void) 503 { 504 arm_bl31_platform_setup(); 505 } 506 507 void bl31_plat_runtime_setup(void) 508 { 509 arm_bl31_plat_runtime_setup(); 510 } 511 512 /******************************************************************************* 513 * Perform the very early platform specific architectural setup shared between 514 * ARM standard platforms. This only does basic initialization. Later 515 * architectural setup (bl31_arch_setup()) does not do anything platform 516 * specific. 517 ******************************************************************************/ 518 void __init arm_bl31_plat_arch_setup(void) 519 { 520 const mmap_region_t bl_regions[] = { 521 MAP_BL31_TOTAL, 522 #if ENABLE_RME 523 ARM_MAP_L0_GPT_REGION, 524 #endif 525 #if RECLAIM_INIT_CODE 526 MAP_BL_INIT_CODE, 527 #endif 528 #if SEPARATE_NOBITS_REGION 529 MAP_BL31_NOBITS, 530 #endif 531 ARM_MAP_BL_RO, 532 #if USE_ROMLIB 533 ARM_MAP_ROMLIB_CODE, 534 ARM_MAP_ROMLIB_DATA, 535 #endif 536 #if USE_COHERENT_MEM 537 ARM_MAP_BL_COHERENT_RAM, 538 #endif 539 {0} 540 }; 541 542 setup_page_tables(bl_regions, plat_arm_get_mmap()); 543 544 enable_mmu_el3(0); 545 546 #if ENABLE_RME 547 #if RESET_TO_BL31 548 /* initialize GPT only when RME is enabled. */ 549 assert(is_feat_rme_present()); 550 551 /* Initialise and enable granule protection after MMU. */ 552 arm_gpt_setup(); 553 #endif /* RESET_TO_BL31 */ 554 /* 555 * Initialise Granule Protection library and enable GPC for the primary 556 * processor. The tables have already been initialized by a previous BL 557 * stage, so there is no need to provide any PAS here. This function 558 * sets up pointers to those tables. 559 */ 560 if (gpt_runtime_init(BITLOCK_BASE, BITLOCK_SIZE) < 0) { 561 ERROR("gpt_runtime_init() failed!\n"); 562 panic(); 563 } 564 #endif /* ENABLE_RME */ 565 566 arm_setup_romlib(); 567 } 568 569 void __init bl31_plat_arch_setup(void) 570 { 571 arm_bl31_plat_arch_setup(); 572 } 573