1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * Copyright (c) 2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_FCS_H 9 #define SOCFPGA_FCS_H 10 11 /* FCS Definitions */ 12 13 #define FCS_RANDOM_WORD_SIZE 8U 14 #define FCS_PROV_DATA_WORD_SIZE 44U 15 #define FCS_SHA384_WORD_SIZE 12U 16 17 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 18 #define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U 19 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 20 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 21 22 #define FCS_RANDOM_EXT_OFFSET 3 23 24 #define FCS_MODE_DECRYPT 0x0 25 #define FCS_MODE_ENCRYPT 0x1 26 #define FCS_ENCRYPTION_DATA_0 0x10100 27 #define FCS_DECRYPTION_DATA_0 0x10102 28 #define FCS_OWNER_ID_OFFSET 0xC 29 #define FCS_CRYPTION_CRYPTO_HEADER 0x07000000 30 #define FCS_CRYPTION_RESP_WORD_SIZE 4U 31 #define FCS_CRYPTION_RESP_SIZE_OFFSET 3U 32 33 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 34 #define PSGSIGMA_SESSION_ID_ONE 0x1 35 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 36 37 #define RESERVED_AS_ZERO 0x0 38 /* FCS Single cert */ 39 40 #define FCS_BIG_CNTR_SEL 0x1 41 42 #define FCS_SVN_CNTR_0_SEL 0x2 43 #define FCS_SVN_CNTR_1_SEL 0x3 44 #define FCS_SVN_CNTR_2_SEL 0x4 45 #define FCS_SVN_CNTR_3_SEL 0x5 46 47 #define FCS_BIG_CNTR_VAL_MAX 495U 48 #define FCS_SVN_CNTR_VAL_MAX 64U 49 50 /* FCS Attestation Cert Request Parameter */ 51 52 #define FCS_ATTEST_FIRMWARE_CERT 0x01 53 #define FCS_ATTEST_DEV_ID_SELF_SIGN_CERT 0x02 54 #define FCS_ATTEST_DEV_ID_ENROLL_CERT 0x04 55 #define FCS_ATTEST_ENROLL_SELF_SIGN_CERT 0x08 56 #define FCS_ATTEST_ALIAS_CERT 0x10 57 #define FCS_ATTEST_CERT_MAX_REQ_PARAM 0xFF 58 59 /* FCS Crypto Service */ 60 61 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 62 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 63 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 64 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 65 66 #define FCS_CS_FIELD_SIZE_MASK 0xFFFF 67 #define FCS_CS_FIELD_FLAG_OFFSET 24 68 #define FCS_CS_FIELD_FLAG_INIT BIT(0) 69 #define FCS_CS_FIELD_FLAG_UPDATE BIT(1) 70 #define FCS_CS_FIELD_FLAG_FINALIZE BIT(2) 71 72 #define FCS_AES_MAX_DATA_SIZE 0x10000000 /* 256 MB */ 73 #define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */ 74 #define FCS_AES_CMD_MAX_WORD_SIZE 15U 75 76 #define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */ 77 #define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */ 78 79 #define FCS_AES_DATA_SIZE_CHECK(x) (((x >= FCS_AES_MIN_DATA_SIZE) && \ 80 (x <= FCS_AES_MAX_DATA_SIZE)) ? \ 81 true : false) 82 83 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U 84 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U 85 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U 86 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U 87 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U 88 89 #define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE 5U 90 #define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE 7U 91 #define FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE 43U 92 #define FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE 17U 93 #define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U 94 #define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U 95 96 #define FCS_CRYPTO_ECB_BUFFER_SIZE 12U 97 #define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U 98 #define FCS_CRYPTO_BLOCK_MODE_MASK 0x07 99 #define FCS_CRYPTO_ECB_MODE 0x00 100 #define FCS_CRYPTO_CBC_MODE 0x01 101 #define FCS_CRYPTO_CTR_MODE 0x02 102 #define FCS_CRYPTO_GCM_MODE 0x03 103 #define FCS_CRYPTO_GCM_GHASH_MODE 0x04 104 105 #define FCS_HKDF_REQUEST_DATA_SIZE 512U 106 #define FCS_HKDF_KEY_OBJ_MAX_SIZE 352U 107 #define FCS_HKDF_KEY_DATA_SIZE 168U 108 #define FCS_HKDF_STEP0_1_KEY_OBJ_SIZE_BITS 384U 109 #define FCS_HKDF_STEP2_KEY_OBJ_SIZE_BITS 256U 110 #define FCS_HKDF_INPUT_BLOCK_SIZE 80U 111 #define FCS_HKDF_SHA2_384_KEY_DATA_SIZE 48U 112 113 /* FCS Payload Structure */ 114 typedef struct fcs_rng_payload_t { 115 uint32_t session_id; 116 uint32_t context_id; 117 uint32_t crypto_header; 118 uint32_t size; 119 } fcs_rng_payload; 120 121 typedef struct fcs_encrypt_payload_t { 122 uint32_t first_word; 123 uint32_t src_addr; 124 uint32_t src_size; 125 uint32_t dst_addr; 126 uint32_t dst_size; 127 } fcs_encrypt_payload; 128 129 typedef struct fcs_decrypt_payload_t { 130 uint32_t first_word; 131 uint32_t owner_id[2]; 132 uint32_t src_addr; 133 uint32_t src_size; 134 uint32_t dst_addr; 135 uint32_t dst_size; 136 } fcs_decrypt_payload; 137 138 typedef struct fcs_encrypt_ext_payload_t { 139 uint32_t session_id; 140 uint32_t context_id; 141 uint32_t crypto_header; 142 uint32_t src_addr; 143 uint32_t src_size; 144 uint32_t dst_addr; 145 uint32_t dst_size; 146 } fcs_encrypt_ext_payload; 147 148 typedef struct fcs_decrypt_ext_payload_t { 149 uint32_t session_id; 150 uint32_t context_id; 151 uint32_t crypto_header; 152 uint32_t owner_id[2]; 153 uint32_t src_addr; 154 uint32_t src_size; 155 uint32_t dst_addr; 156 uint32_t dst_size; 157 } fcs_decrypt_ext_payload; 158 159 typedef struct psgsigma_teardown_msg_t { 160 uint32_t reserved_word; 161 uint32_t magic_word; 162 uint32_t session_id; 163 } psgsigma_teardown_msg; 164 165 typedef struct fcs_cntr_set_preauth_payload_t { 166 uint32_t first_word; 167 uint32_t counter_value; 168 } fcs_cntr_set_preauth_payload; 169 170 typedef struct fcs_cs_key_payload_t { 171 uint32_t session_id; 172 uint32_t reserved0; 173 uint32_t reserved1; 174 uint32_t key_id; 175 } fcs_cs_key_payload; 176 177 typedef struct fcs_crypto_service_data_t { 178 uint32_t session_id; 179 uint32_t context_id; 180 uint32_t key_id; 181 uint32_t crypto_param_size; 182 uint64_t crypto_param; 183 uint8_t is_updated; 184 } fcs_crypto_service_data; 185 186 typedef struct fcs_crypto_service_aes_data_t { 187 uint32_t session_id; 188 uint32_t context_id; 189 uint32_t param_size; 190 uint32_t key_id; 191 uint32_t crypto_param[7]; 192 uint8_t is_updated; 193 } fcs_crypto_service_aes_data; 194 195 /* Functions Definitions */ 196 197 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 198 uint32_t *mbox_error); 199 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id, 200 uint32_t size, uint32_t *send_id); 201 uint32_t intel_fcs_send_cert(uint32_t smc_fid, uint32_t trans_id, 202 uint64_t addr, uint64_t size, 203 uint32_t *send_id); 204 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 205 uint32_t intel_fcs_cntr_set_preauth(uint32_t smc_fid, uint32_t trans_id, 206 uint8_t counter_type, 207 int32_t counter_value, 208 uint32_t test_bit, 209 uint32_t *mbox_error); 210 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 211 uint32_t dst_addr, uint32_t dst_size, 212 uint32_t *send_id); 213 214 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 215 uint32_t dst_addr, uint32_t dst_size, 216 uint32_t *send_id); 217 218 int intel_fcs_encryption_ext(uint32_t smc_fid, uint32_t trans_id, 219 uint32_t session_id, uint32_t context_id, 220 uint32_t src_addr, uint32_t src_size, 221 uint32_t dst_addr, uint32_t *dst_size, 222 uint32_t *mbox_error, uint32_t smmu_src_addr, 223 uint32_t smmu_dst_addr); 224 int intel_fcs_decryption_ext(uint32_t smc_fid, uint32_t trans_id, 225 uint32_t sesion_id, uint32_t context_id, 226 uint32_t src_addr, uint32_t src_size, 227 uint32_t dst_addr, uint32_t *dst_size, 228 uint32_t *mbox_error, uint64_t owner_id, 229 uint32_t smmu_src_addr, uint32_t smmu_dst_addr); 230 231 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 232 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 233 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 234 uint64_t dst_addr, uint32_t *dst_size, 235 uint32_t *mbox_error); 236 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 237 uint64_t dst_addr, uint32_t *dst_size, 238 uint32_t *mbox_error); 239 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 240 uint32_t *mbox_error); 241 242 int intel_fcs_create_cert_on_reload(uint32_t smc_fid, uint32_t trans_id, 243 uint32_t cert_request, uint32_t *mbox_error); 244 int intel_fcs_get_attestation_cert(uint32_t smc_fid, uint32_t trans_id, 245 uint32_t cert_request, uint64_t dst_addr, 246 uint32_t *dst_size, uint32_t *mbox_error); 247 248 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 249 uint32_t *mbox_error); 250 int intel_fcs_close_crypto_service_session(uint32_t session_id, 251 uint32_t *mbox_error); 252 253 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 254 uint32_t *mbox_error); 255 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 256 uint64_t dst_addr, uint32_t *dst_size, 257 uint32_t *mbox_error); 258 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 259 uint32_t *mbox_error); 260 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 261 uint64_t dst_addr, uint32_t *dst_size, 262 uint32_t *mbox_error); 263 264 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id, 265 uint32_t key_id, uint32_t param_size, 266 uint64_t param_data, uint32_t *mbox_error); 267 int intel_fcs_get_digest_update_finalize(uint32_t smc_fid, uint32_t trans_id, 268 uint32_t session_id, uint32_t context_id, 269 uint32_t src_addr, uint32_t src_size, 270 uint64_t dst_addr, uint32_t *dst_size, 271 uint8_t is_finalised, uint32_t *mbox_error, 272 uint32_t smmu_src_addr); 273 int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id, uint32_t context_id, 274 uint32_t src_addr, uint32_t src_size, 275 uint64_t dst_addr, uint32_t *dst_size, 276 uint8_t is_finalised, uint32_t *mbox_error, 277 uint32_t *send_id); 278 279 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id, 280 uint32_t key_id, uint32_t param_size, 281 uint64_t param_data, uint32_t *mbox_error); 282 int intel_fcs_mac_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id, 283 uint32_t session_id, uint32_t context_id, 284 uint32_t src_addr, uint32_t src_size, 285 uint64_t dst_addr, uint32_t *dst_size, 286 uint32_t data_size, uint8_t is_finalised, 287 uint32_t *mbox_error, uint64_t smmu_src_addr); 288 int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id, uint32_t context_id, 289 uint32_t src_addr, uint32_t src_size, 290 uint64_t dst_addr, uint32_t *dst_size, 291 uint32_t data_size, uint8_t is_finalised, 292 uint32_t *mbox_error, uint32_t *send_id); 293 294 int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id, 295 uint32_t key_id, uint32_t param_size, 296 uint64_t param_data, uint32_t *mbox_error); 297 int intel_fcs_ecdsa_hash_sign_finalize(uint32_t smc_fid, uint32_t trans_id, 298 uint32_t session_id, uint32_t context_id, 299 uint32_t src_addr, uint32_t src_size, 300 uint64_t dst_addr, uint32_t *dst_size, 301 uint32_t *mbox_error); 302 303 int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id, 304 uint32_t key_id, uint32_t param_size, 305 uint64_t param_data, uint32_t *mbox_error); 306 int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t smc_fid, uint32_t trans_id, 307 uint32_t session_id, uint32_t context_id, 308 uint32_t src_addr, uint32_t src_size, 309 uint64_t dst_addr, uint32_t *dst_size, 310 uint32_t *mbox_error); 311 312 int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id, 313 uint32_t context_id, uint32_t key_id, 314 uint32_t param_size, uint64_t param_data, 315 uint32_t *mbox_error); 316 int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t smc_fid, uint32_t trans_id, 317 uint32_t session_id, uint32_t context_id, 318 uint32_t src_addr, uint32_t src_size, 319 uint64_t dst_addr, uint32_t *dst_size, 320 uint8_t is_finalised, uint32_t *mbox_error, 321 uint64_t smmu_src_addr); 322 int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id, 323 uint32_t context_id, uint32_t src_addr, 324 uint32_t src_size, uint64_t dst_addr, 325 uint32_t *dst_size, uint8_t is_finalised, 326 uint32_t *mbox_error, uint32_t *send_id); 327 328 int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id, 329 uint32_t context_id, uint32_t key_id, 330 uint32_t param_size, uint64_t param_data, 331 uint32_t *mbox_error); 332 int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id, 333 uint32_t session_id, uint32_t context_id, 334 uint32_t src_addr, uint32_t src_size, 335 uint64_t dst_addr, uint32_t *dst_size, 336 uint32_t data_size, uint8_t is_finalised, 337 uint32_t *mbox_error, uint64_t smmu_src_addr); 338 int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id, 339 uint32_t context_id, uint32_t src_addr, 340 uint32_t src_size, uint64_t dst_addr, 341 uint32_t *dst_size, uint32_t data_size, 342 uint8_t is_finalised, uint32_t *mbox_error, 343 uint32_t *send_id); 344 345 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id, 346 uint32_t key_id, uint32_t param_size, 347 uint64_t param_data, uint32_t *mbox_error); 348 int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t smc_fid, uint32_t trans_id, 349 uint32_t session_id, uint32_t context_id, 350 uint64_t dst_addr, uint32_t *dst_size, 351 uint32_t *mbox_error); 352 353 int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id, 354 uint32_t key_id, uint32_t param_size, 355 uint64_t param_data, uint32_t *mbox_error); 356 int intel_fcs_ecdh_request_finalize(uint32_t smc_fid, uint32_t trans_id, 357 uint32_t session_id, uint32_t context_id, 358 uint32_t src_addr, uint32_t src_size, 359 uint64_t dst_addr, uint32_t *dst_size, 360 uint32_t *mbox_error); 361 362 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id, 363 uint32_t key_id, uint64_t param_addr, 364 uint32_t param_size, uint32_t *mbox_error); 365 int intel_fcs_aes_crypt_update_finalize(uint32_t smc_fid, uint32_t trans_id, 366 uint32_t session_id, uint32_t context_id, 367 uint64_t src_addr, uint32_t src_size, 368 uint64_t dst_addr, uint32_t dst_size, 369 uint32_t padding_size, uint8_t is_finalised, 370 uint32_t *send_id, uint64_t smmu_src_addr, 371 uint64_t smmu_dst_addr); 372 373 int intel_fcs_hkdf_request(uint32_t smc_fid, uint32_t trans_id, 374 uint32_t session_id, uint32_t step_type, 375 uint32_t mac_mode, uint32_t src_addr, 376 uint32_t key_uid, uint32_t op_key_size); 377 #endif /* SOCFPGA_FCS_H */ 378