1 /* 2 * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_sdmmc2.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 /* Power cycle delays in ms */ 122 #define VCC_POWER_OFF_DELAY 2 123 #define VCC_POWER_ON_DELAY 2 124 #define POWER_CYCLE_DELAY 2 125 #define POWER_OFF_DELAY 2 126 #define POWER_ON_DELAY 1 127 128 #ifndef DT_SDMMC2_COMPAT 129 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 130 #endif 131 132 #ifdef STM32MP1X 133 #define SDMMC_FIFO_SIZE 64U 134 #else 135 #define SDMMC_FIFO_SIZE 1024U 136 #endif 137 138 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 139 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 140 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 141 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 142 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 143 144 static void stm32_sdmmc2_init(void); 145 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 146 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 147 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 148 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 149 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 150 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 151 152 static const struct mmc_ops stm32_sdmmc2_ops = { 153 .init = stm32_sdmmc2_init, 154 .send_cmd = stm32_sdmmc2_send_cmd, 155 .set_ios = stm32_sdmmc2_set_ios, 156 .prepare = stm32_sdmmc2_prepare, 157 .read = stm32_sdmmc2_read, 158 .write = stm32_sdmmc2_write, 159 }; 160 161 static struct stm32_sdmmc2_params sdmmc2_params; 162 163 static bool next_cmd_is_acmd; 164 165 #pragma weak plat_sdmmc2_use_dma 166 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 167 { 168 return false; 169 } 170 171 static void stm32_sdmmc2_init(void) 172 { 173 uint32_t clock_div; 174 uint32_t freq = STM32MP_MMC_INIT_FREQ; 175 uintptr_t base = sdmmc2_params.reg_base; 176 int ret; 177 178 if (sdmmc2_params.max_freq != 0U) { 179 freq = MIN(sdmmc2_params.max_freq, freq); 180 } 181 182 if (sdmmc2_params.vmmc_regu != NULL) { 183 ret = regulator_disable(sdmmc2_params.vmmc_regu); 184 if (ret < 0) { 185 panic(); 186 } 187 } 188 189 mdelay(VCC_POWER_OFF_DELAY); 190 191 mmio_write_32(base + SDMMC_POWER, 192 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); 193 mdelay(POWER_CYCLE_DELAY); 194 195 if (sdmmc2_params.vmmc_regu != NULL) { 196 ret = regulator_enable(sdmmc2_params.vmmc_regu); 197 if (ret < 0) { 198 panic(); 199 } 200 } 201 202 mdelay(VCC_POWER_ON_DELAY); 203 204 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); 205 mdelay(POWER_OFF_DELAY); 206 207 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 208 209 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 210 sdmmc2_params.negedge | 211 sdmmc2_params.pin_ckin); 212 213 mmio_write_32(base + SDMMC_POWER, 214 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 215 216 mdelay(POWER_ON_DELAY); 217 } 218 219 static int stm32_sdmmc2_stop_transfer(void) 220 { 221 struct mmc_cmd cmd_stop; 222 223 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 224 225 cmd_stop.cmd_idx = MMC_CMD(12); 226 cmd_stop.resp_type = MMC_RESPONSE_R1B; 227 228 return stm32_sdmmc2_send_cmd(&cmd_stop); 229 } 230 231 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 232 { 233 uint64_t timeout; 234 uint32_t flags_cmd, status; 235 uint32_t flags_data = 0; 236 int err = 0; 237 uintptr_t base = sdmmc2_params.reg_base; 238 unsigned int cmd_reg, arg_reg; 239 240 if (cmd == NULL) { 241 return -EINVAL; 242 } 243 244 flags_cmd = SDMMC_STAR_CTIMEOUT; 245 arg_reg = cmd->cmd_arg; 246 247 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 248 mmio_write_32(base + SDMMC_CMDR, 0); 249 } 250 251 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 252 253 if (cmd->resp_type == 0U) { 254 flags_cmd |= SDMMC_STAR_CMDSENT; 255 } 256 257 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 258 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 259 flags_cmd |= SDMMC_STAR_CMDREND; 260 cmd_reg |= SDMMC_CMDR_WAITRESP; 261 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 262 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 263 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 264 } else { 265 flags_cmd |= SDMMC_STAR_CMDREND; 266 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 267 } 268 } 269 270 switch (cmd->cmd_idx) { 271 case MMC_CMD(1): 272 arg_reg |= OCR_POWERUP; 273 break; 274 case MMC_CMD(6): 275 if ((sdmmc2_params.device_info->mmc_dev_type == MMC_IS_SD_HC) && 276 (!next_cmd_is_acmd)) { 277 cmd_reg |= SDMMC_CMDR_CMDTRANS; 278 if (sdmmc2_params.use_dma) { 279 flags_data |= SDMMC_STAR_DCRCFAIL | 280 SDMMC_STAR_DTIMEOUT | 281 SDMMC_STAR_DATAEND | 282 SDMMC_STAR_RXOVERR | 283 SDMMC_STAR_IDMATE | 284 SDMMC_STAR_DBCKEND; 285 } 286 } 287 break; 288 case MMC_CMD(8): 289 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 290 cmd_reg |= SDMMC_CMDR_CMDTRANS; 291 } 292 break; 293 case MMC_CMD(12): 294 cmd_reg |= SDMMC_CMDR_CMDSTOP; 295 break; 296 case MMC_CMD(17): 297 case MMC_CMD(18): 298 cmd_reg |= SDMMC_CMDR_CMDTRANS; 299 if (sdmmc2_params.use_dma) { 300 flags_data |= SDMMC_STAR_DCRCFAIL | 301 SDMMC_STAR_DTIMEOUT | 302 SDMMC_STAR_DATAEND | 303 SDMMC_STAR_RXOVERR | 304 SDMMC_STAR_IDMATE; 305 } 306 break; 307 case MMC_ACMD(41): 308 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 309 break; 310 case MMC_ACMD(51): 311 cmd_reg |= SDMMC_CMDR_CMDTRANS; 312 if (sdmmc2_params.use_dma) { 313 flags_data |= SDMMC_STAR_DCRCFAIL | 314 SDMMC_STAR_DTIMEOUT | 315 SDMMC_STAR_DATAEND | 316 SDMMC_STAR_RXOVERR | 317 SDMMC_STAR_IDMATE | 318 SDMMC_STAR_DBCKEND; 319 } 320 break; 321 default: 322 break; 323 } 324 325 next_cmd_is_acmd = (cmd->cmd_idx == MMC_CMD(55)); 326 327 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 328 329 /* 330 * Clear the SDMMC_DCTRLR if the command does not await data. 331 * Skip CMD55 as the next command could be data related, and 332 * the register could have been set in prepare function. 333 */ 334 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && !next_cmd_is_acmd) { 335 mmio_write_32(base + SDMMC_DCTRLR, 0U); 336 } 337 338 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 339 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 340 } 341 342 mmio_write_32(base + SDMMC_ARGR, arg_reg); 343 344 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 345 346 status = mmio_read_32(base + SDMMC_STAR); 347 348 timeout = timeout_init_us(TIMEOUT_US_10_MS); 349 350 while ((status & flags_cmd) == 0U) { 351 if (timeout_elapsed(timeout)) { 352 err = -ETIMEDOUT; 353 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 354 __func__, cmd->cmd_idx, status); 355 goto err_exit; 356 } 357 358 status = mmio_read_32(base + SDMMC_STAR); 359 } 360 361 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 362 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 363 err = -ETIMEDOUT; 364 /* 365 * Those timeouts can occur, and framework will handle 366 * the retries. CMD8 is expected to return this timeout 367 * for eMMC 368 */ 369 if (!((cmd->cmd_idx == MMC_CMD(1)) || 370 (cmd->cmd_idx == MMC_CMD(13)) || 371 ((cmd->cmd_idx == MMC_CMD(8)) && 372 (cmd->resp_type == MMC_RESPONSE_R7)))) { 373 ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n", 374 __func__, cmd->cmd_idx, status); 375 } 376 } else { 377 err = -EIO; 378 ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n", 379 __func__, cmd->cmd_idx, status); 380 } 381 382 goto err_exit; 383 } 384 385 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 386 if ((cmd->cmd_idx == MMC_CMD(9)) && 387 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 388 /* Need to invert response to match CSD structure */ 389 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 390 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 391 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 392 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 393 } else { 394 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 395 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 396 SDMMC_CMDR_WAITRESP) { 397 cmd->resp_data[1] = mmio_read_32(base + 398 SDMMC_RESP2R); 399 cmd->resp_data[2] = mmio_read_32(base + 400 SDMMC_RESP3R); 401 cmd->resp_data[3] = mmio_read_32(base + 402 SDMMC_RESP4R); 403 } 404 } 405 } 406 407 if (flags_data == 0U) { 408 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 409 410 return 0; 411 } 412 413 status = mmio_read_32(base + SDMMC_STAR); 414 415 timeout = timeout_init_us(TIMEOUT_US_10_MS); 416 417 while ((status & flags_data) == 0U) { 418 if (timeout_elapsed(timeout)) { 419 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 420 __func__, cmd->cmd_idx, status); 421 err = -ETIMEDOUT; 422 goto err_exit; 423 } 424 425 status = mmio_read_32(base + SDMMC_STAR); 426 }; 427 428 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 429 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 430 SDMMC_STAR_IDMATE)) != 0U) { 431 ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__, 432 cmd->cmd_idx, status); 433 err = -EIO; 434 } 435 436 err_exit: 437 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 438 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 439 440 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 441 int ret_stop = stm32_sdmmc2_stop_transfer(); 442 443 if (ret_stop != 0) { 444 return ret_stop; 445 } 446 } 447 448 return err; 449 } 450 451 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 452 { 453 uint8_t retry; 454 int err; 455 456 assert(cmd != NULL); 457 458 for (retry = 0U; retry < 3U; retry++) { 459 err = stm32_sdmmc2_send_cmd_req(cmd); 460 if (err == 0) { 461 return 0; 462 } 463 464 if ((cmd->cmd_idx == MMC_CMD(1)) || 465 (cmd->cmd_idx == MMC_CMD(13))) { 466 return 0; /* Retry managed by framework */ 467 } 468 469 /* Command 8 is expected to fail for eMMC */ 470 if (cmd->cmd_idx != MMC_CMD(8)) { 471 WARN(" CMD%u, Retry: %u, Error: %d\n", 472 cmd->cmd_idx, retry + 1U, err); 473 } 474 475 udelay(10U); 476 } 477 478 return err; 479 } 480 481 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 482 { 483 uintptr_t base = sdmmc2_params.reg_base; 484 uint32_t bus_cfg = 0; 485 uint32_t clock_div, max_freq, freq; 486 uint32_t clk_rate = sdmmc2_params.clk_rate; 487 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 488 489 switch (width) { 490 case MMC_BUS_WIDTH_1: 491 break; 492 case MMC_BUS_WIDTH_4: 493 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 494 break; 495 case MMC_BUS_WIDTH_8: 496 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 497 break; 498 default: 499 panic(); 500 break; 501 } 502 503 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 504 if (max_bus_freq >= 52000000U) { 505 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 506 } else { 507 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 508 } 509 } else { 510 if (max_bus_freq >= 50000000U) { 511 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 512 } else { 513 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 514 } 515 } 516 517 if (sdmmc2_params.max_freq != 0U) { 518 freq = MIN(sdmmc2_params.max_freq, max_freq); 519 } else { 520 freq = max_freq; 521 } 522 523 clock_div = div_round_up(clk_rate, freq * 2U); 524 525 mmio_write_32(base + SDMMC_CLKCR, 526 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 527 sdmmc2_params.negedge | 528 sdmmc2_params.pin_ckin); 529 530 return 0; 531 } 532 533 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 534 { 535 struct mmc_cmd cmd; 536 int ret; 537 uintptr_t base = sdmmc2_params.reg_base; 538 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 539 uint32_t arg_size; 540 541 assert((size != 0U) && (size <= UINT32_MAX)); 542 543 if (size > MMC_BLOCK_SIZE) { 544 arg_size = MMC_BLOCK_SIZE; 545 } else { 546 arg_size = (uint32_t)size; 547 } 548 549 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 550 551 if (sdmmc2_params.use_dma) { 552 inv_dcache_range(buf, size); 553 } 554 555 /* Prepare CMD 16*/ 556 mmio_write_32(base + SDMMC_DTIMER, 0); 557 558 mmio_write_32(base + SDMMC_DLENR, 0); 559 560 mmio_write_32(base + SDMMC_DCTRLR, 0); 561 562 zeromem(&cmd, sizeof(struct mmc_cmd)); 563 564 cmd.cmd_idx = MMC_CMD(16); 565 cmd.cmd_arg = arg_size; 566 cmd.resp_type = MMC_RESPONSE_R1; 567 568 ret = stm32_sdmmc2_send_cmd(&cmd); 569 if (ret != 0) { 570 ERROR("CMD16 failed\n"); 571 return ret; 572 } 573 574 /* Prepare data command */ 575 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 576 577 mmio_write_32(base + SDMMC_DLENR, size); 578 579 if (sdmmc2_params.use_dma) { 580 mmio_write_32(base + SDMMC_IDMACTRLR, 581 SDMMC_IDMACTRLR_IDMAEN); 582 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 583 584 flush_dcache_range(buf, size); 585 } 586 587 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 588 589 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 590 SDMMC_DCTRLR_CLEAR_MASK, 591 data_ctrl); 592 593 return 0; 594 } 595 596 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 597 { 598 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 599 SDMMC_STAR_DTIMEOUT; 600 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 601 uint32_t status; 602 uint32_t *buffer; 603 uintptr_t base = sdmmc2_params.reg_base; 604 uintptr_t fifo_reg = base + SDMMC_FIFOR; 605 uint64_t timeout; 606 int ret; 607 608 /* Assert buf is 4 bytes aligned */ 609 assert((buf & GENMASK(1, 0)) == 0U); 610 611 buffer = (uint32_t *)buf; 612 613 if (sdmmc2_params.use_dma) { 614 inv_dcache_range(buf, size); 615 616 return 0; 617 } 618 619 if (size <= MMC_BLOCK_SIZE) { 620 flags |= SDMMC_STAR_DBCKEND; 621 } 622 623 timeout = timeout_init_us(TIMEOUT_US_1_S); 624 625 do { 626 status = mmio_read_32(base + SDMMC_STAR); 627 628 if ((status & error_flags) != 0U) { 629 ERROR("%s: Read error (status = %x)\n", __func__, 630 status); 631 mmio_write_32(base + SDMMC_DCTRLR, 632 SDMMC_DCTRLR_FIFORST); 633 634 mmio_write_32(base + SDMMC_ICR, 635 SDMMC_STATIC_FLAGS); 636 637 ret = stm32_sdmmc2_stop_transfer(); 638 if (ret != 0) { 639 return ret; 640 } 641 642 return -EIO; 643 } 644 645 if (timeout_elapsed(timeout)) { 646 ERROR("%s: timeout 1s (status = %x)\n", 647 __func__, status); 648 mmio_write_32(base + SDMMC_ICR, 649 SDMMC_STATIC_FLAGS); 650 651 ret = stm32_sdmmc2_stop_transfer(); 652 if (ret != 0) { 653 return ret; 654 } 655 656 return -ETIMEDOUT; 657 } 658 659 if (size < (SDMMC_FIFO_SIZE / 2U)) { 660 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 661 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 662 *buffer = mmio_read_32(fifo_reg); 663 buffer++; 664 } 665 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 666 uint32_t count; 667 668 /* Read data from SDMMC Rx FIFO */ 669 for (count = 0; count < (SDMMC_FIFO_SIZE / 2U); 670 count += sizeof(uint32_t)) { 671 *buffer = mmio_read_32(fifo_reg); 672 buffer++; 673 } 674 } 675 } while ((status & flags) == 0U); 676 677 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 678 679 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 680 WARN("%s: DPSMACT=1, send stop\n", __func__); 681 return stm32_sdmmc2_stop_transfer(); 682 } 683 684 return 0; 685 } 686 687 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 688 { 689 return 0; 690 } 691 692 static int stm32_sdmmc2_dt_get_config(void) 693 { 694 int sdmmc_node; 695 void *fdt = NULL; 696 const fdt32_t *cuint; 697 struct dt_node_info dt_info; 698 699 if (fdt_get_address(&fdt) == 0) { 700 return -FDT_ERR_NOTFOUND; 701 } 702 703 if (fdt == NULL) { 704 return -FDT_ERR_NOTFOUND; 705 } 706 707 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 708 sdmmc2_params.reg_base); 709 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 710 return -FDT_ERR_NOTFOUND; 711 } 712 713 dt_fill_device_info(&dt_info, sdmmc_node); 714 if (dt_info.status == DT_DISABLED) { 715 return -FDT_ERR_NOTFOUND; 716 } 717 718 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 719 return -FDT_ERR_BADVALUE; 720 } 721 722 sdmmc2_params.clock_id = dt_info.clock; 723 sdmmc2_params.reset_id = dt_info.reset; 724 725 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 726 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 727 } 728 729 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 730 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 731 } 732 733 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 734 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 735 } 736 737 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 738 if (cuint != NULL) { 739 switch (fdt32_to_cpu(*cuint)) { 740 case 4: 741 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 742 break; 743 744 case 8: 745 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 746 break; 747 748 default: 749 break; 750 } 751 } 752 753 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 754 if (cuint != NULL) { 755 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 756 } 757 758 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); 759 760 return 0; 761 } 762 763 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 764 { 765 return sdmmc2_params.device_info->device_size; 766 } 767 768 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 769 { 770 assert((params != NULL) && 771 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 772 ((params->bus_width == MMC_BUS_WIDTH_1) || 773 (params->bus_width == MMC_BUS_WIDTH_4) || 774 (params->bus_width == MMC_BUS_WIDTH_8))); 775 776 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 777 778 sdmmc2_params.vmmc_regu = NULL; 779 780 if (stm32_sdmmc2_dt_get_config() != 0) { 781 ERROR("%s: DT error\n", __func__); 782 return -ENOMEM; 783 } 784 785 clk_enable(sdmmc2_params.clock_id); 786 787 if ((int)sdmmc2_params.reset_id >= 0) { 788 int rc; 789 790 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 791 if (rc != 0) { 792 panic(); 793 } 794 udelay(2); 795 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 796 if (rc != 0) { 797 panic(); 798 } 799 mdelay(1); 800 } 801 802 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 803 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 804 805 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 806 sdmmc2_params.bus_width, sdmmc2_params.flags, 807 sdmmc2_params.device_info); 808 } 809