Merge "fix(build): use ARM_ARCH_FEATURE instead of -march directly" into integration

Merge changes from topic "xl/n2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-N2 erratum 2138953
fix(cpus): workaround for Neoverse-N2 erratum 4302970
fix(cpus): worka

Merge changes from topic "xl/n2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-N2 erratum 2138953
fix(cpus): workaround for Neoverse-N2 erratum 4302970
fix(cpus): workaround for Neoverse-N2 erratum 3888123
refactor(cpus): reorder the errratum build flag for Neoverse-N2

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Merge changes from topic "xl/cortex-x3-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 4302966
fix(cpus): workaround for Cortex-X3 erratum 3888125

Merge changes from topic "xl/cortex-x2-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 4302969
fix(cpus): workaround for Cortex-X2 erratum 3888122

fix(cpus): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 that applies to revisions
r0p0, r0p1, r0p2 and r0p3, and is still open.

The erratum can be avoided by executing a s

fix(cpus): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 that applies to revisions
r0p0, r0p1, r0p2 and r0p3, and is still open.

The erratum can be avoided by executing a specific instruction
sequence when disabling the hardware prefetcher.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: Ie465328e87754a1ec511a2f77243b4b0b09134cc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-N2 erratum 4302970

Neoverse-N2 erratum 4302970 that applies to revisions
r0p0, r0p1, r0p2, r0p3, and is still open.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Neoverse-N2 erratum 4302970

Neoverse-N2 erratum 4302970 that applies to revisions
r0p0, r0p1, r0p2, r0p3, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I2436b11a36be204d549522f1176fcd49658c044c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-N2 erratum 3888123

Neoverse-N2 erratum 3888123 that applies to r0p0, r0p1,
r0p2 and r0p3, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] t

fix(cpus): workaround for Neoverse-N2 erratum 3888123

Neoverse-N2 erratum 3888123 that applies to r0p0, r0p1,
r0p2 and r0p3, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I6240d263fb5d153721b5b84a37df2f24e3d02d86
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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refactor(cpus): reorder the errratum build flag for Neoverse-N2

The erratum build flag is not in ascending for Neoverse-N2 cpu.
Reorder the build flag.

Change-Id: Ifb736adf8f06bf6202784bdeac51c0251

refactor(cpus): reorder the errratum build flag for Neoverse-N2

The erratum build flag is not in ascending for Neoverse-N2 cpu.
Reorder the build flag.

Change-Id: Ifb736adf8f06bf6202784bdeac51c02512519782
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1

fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I284ee7fe611c4c9861696fde62f796e6fae6dff6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting

fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I5c01dfcffc6e56163aba03428e21fedee8cc7042
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes I7af8857d,I7fc84d2c into integration

* changes:
docs(maintainers): add Gabriel as clock framework maintainer
docs(maintainers): sort frameworks alphabetically

Merge "docs(per-cpu): update diagram for NUMA enabled per-cpu layout" into integration

Merge "feat(docs): document PSCI power_state" into integration

Merge "docs: update Ignored Checkpatch Warnings chapter" into integration

Merge "docs(threat-model): clarify scope of experimental features" into integration

Merge changes from topic "xl/v2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 4302968
fix(cpus): workaround for Neoverse-V2 erratum 3888126

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FE

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FEATURE. Setting -march directly can lead to unexpected results
when using the above flags and is generally not recommended within tfa.

This patch migrates all instances of -march=armv8-a+crc to
ARM_ARCH_FEATURE=crc. Arm platforms (via arm_common.mk) are checked and
those that support cores greater than arm8.1 do not get the flag as it
is automatically pulled in.

Change-Id: I846f97367eab9529524a2805d5b87d34cce2360f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): workaround for Cortex-A76AE erratum 2753838" into integration

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_E

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I42b27e19d61a7f9c57efe1b5f5336d165eb98210
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[2

fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I4068aa73d38a70c00d66bb894169be2659d67de7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I6c5de5843f2199fa697f8336558fa56a87ee846d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[

fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I368cfdd216ea5875b81640415ff71b15f46ea953
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by addin

fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by adding a DSB instruction before
the ISB of the power-down code sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/latest/

Change-Id: I338834a21c14879faee5280876a59153d549cb7b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/x925-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 3865185
fix(cpus): workaround for Cortex-X925 erratum 3730893
fix(cpus): wor

Merge changes from topic "xl/x925-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 3865185
fix(cpus): workaround for Cortex-X925 erratum 3730893
fix(cpus): workaround for Cortex-X925 erratum 3692980
fix(cpus): workaround for Cortex-X925 erratum 3324334
fix(cpus): workaround for Cortex-X925 erratum 2933290
fix(cpus): workaround for Cortex-X925 erratum 2922378
fix(cpus): workaround for Cortex-X925 erratum 2921199

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fix(cpus): workaround for Cortex-X925 erratum 3865185

Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

Load issued to Non-Cacheable or De

fix(cpus): workaround for Cortex-X925 erratum 3865185

Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

Load issued to Non-Cacheable or Device GRE memory can
read stale data brought in by an earlier load to the
same cache-line thereby violating ordering requirements.
This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: Iff224ef82bd1cb9aff8d6b11451e2ac1d048149f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...