Merge "docs: remove RME out of box testing instructions" into integration

Merge changes from topic "hm/release" into integration

* changes:
chore: bump libeventlog to latest version
docs: update docs w/ min tool version

Merge "docs(juno): update PSCI instrumentation data" into integration

docs: remove RME out of box testing instructions

Those instructions have proven difficult to maintain over time with
multiple components as moving targets. Nowadays prefer relying on
shrinkwrap offe

docs: remove RME out of box testing instructions

Those instructions have proven difficult to maintain over time with
multiple components as moving targets. Nowadays prefer relying on
shrinkwrap offering an integrated end to end build system capable of
running most RME related scenarios on the Base FVP.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I27add62bf1fe9bd7a1a619566202192c3010ef10

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docs: update docs w/ min tool version

The minimum Node version was updated to the latest LTS release. Update
the docs to reflect this change. While we're at it, clean up remaining
references from th

docs: update docs w/ min tool version

The minimum Node version was updated to the latest LTS release. Update
the docs to reflect this change. While we're at it, clean up remaining
references from the Arm GNU toolchain version update and set the minimum
for GNU Make to whatever is provided by Ubuntu 22.04.

Change-Id: I16923c9cf69b34f78f19bc10e3bed72b70ae8132
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "docs: describe RAS KFH limitations and its mitigation in future" into integration

Merge changes Ib172b554,I9971fd47 into integration

* changes:
docs(per-cpu): clean up NUMA docs
fix(per-cpu): remove redundant casts

docs(per-cpu): clean up NUMA docs

This change incorporates resolutions for the remaining code review
comments on the NUMA documentation, which were intentionally left
unresolved when the NUMA stack

docs(per-cpu): clean up NUMA docs

This change incorporates resolutions for the remaining code review
comments on the NUMA documentation, which were intentionally left
unresolved when the NUMA stack was expedited.

Additionally, general improvements include:

- Documentation has been re-flowed with Pandoc;
- Diagram file-names follow naming conventions;
- Diagram alt-text better reflects the image content;
- Diagram widths scale with the content body width; and
- Grammar and spelling follow American English.

Change-Id: Ib172b554347caa8a72229081682b07fdb6417b64
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(cpufeat): mark RME_GDI, IDTE3 and RME_GPC2 as supported

Update architecture_features.rst to reflect that FEAT_RME_GDI,
FEAT_IDTE3, and FEAT_RME_GPC2 are now marked as OK instead of WIP.

Signed

docs(cpufeat): mark RME_GDI, IDTE3 and RME_GPC2 as supported

Update architecture_features.rst to reflect that FEAT_RME_GDI,
FEAT_IDTE3, and FEAT_RME_GPC2 are now marked as OK instead of WIP.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I27cfd01657fe6df4b0a4e4551f120dd279830213

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docs(juno): update PSCI instrumentation data

Update for v2.14 release based on v2.14-rc0

Change-Id: Id0cf75e284cc02a513d134ccd550fe9a73ac6909
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

docs(ff-a): document `sri-interrupts-policy` field

Add the encoding information for the `sri-interrupts-policy` field
for SP FF-A manifest.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ib

docs(ff-a): document `sri-interrupts-policy` field

Add the encoding information for the `sri-interrupts-policy` field
for SP FF-A manifest.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ib8f6a3ba02be3a312abd1f8ab4a75874290a244f

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docs: describe RAS KFH limitations and its mitigation in future

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I27b739413140fc310b2bcb3a0812e07ba29e36d8

Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register def

Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register defines and read helpers

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Merge "docs(cpufeat): add a checklist on how to add a feature" into integration

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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docs(maintainers): add per-cpu framework into maintainers.rst

Add Rohit Mathew <rohit.mathew@arm.com> and Sammit Joshi
<sammit.joshi@arm.com> as code owners for the per-CPU framework.

Add Manish Pa

docs(maintainers): add per-cpu framework into maintainers.rst

Add Rohit Mathew <rohit.mathew@arm.com> and Sammit Joshi
<sammit.joshi@arm.com> as code owners for the per-CPU framework.

Add Manish Pandey <manish.pandey2@arm.com> and
Chris Kay <chris.kay@arm.com> as a code owner alongside
the authors.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: If81e097d8b52d083cff9e0722c5550322cffd245

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feat(per-cpu): add documentation for per-cpu framework

add documentation for numa aware per-cpu framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Sammit Joshi <sammit.jos

feat(per-cpu): add documentation for per-cpu framework

add documentation for numa aware per-cpu framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ibd39adea95aa24abb588ff518547bdc1ec46b0fe

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feat(per-cpu): migrate spm_core_context to per-cpu framework

migrate spm_core_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed

feat(per-cpu): migrate spm_core_context to per-cpu framework

migrate spm_core_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie600ae755cfb738adde51cfc4af3cddbbccbbaef

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feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-of

feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ie8b9f4eea8c61d4de9996d9370634cbd08ff1d8d

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feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signe

feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idec3e3b74ecf03b420b339a183be2b9e00f8a78f

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feat(per-cpu): migrate rmm_context to per-cpu framework

migrate rmm_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: S

feat(per-cpu): migrate rmm_context to per-cpu framework

migrate rmm_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I72d49c3d860dac10bd3930ce400b0199bedd887b

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docs(cpufeat): add a checklist on how to add a feature

Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
m

docs(cpufeat): add a checklist on how to add a feature

Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
must be guided along, usually at code review. Further, the process
changes occasionally so it can be difficult even for an experienced
contributor to get right.

So add a checklist along with brief explanations on what to look for so
we can make our job nicer.

Change-Id: I09dd0062b742c9fce5a8f86a2067adc941db6899
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from diffe

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime the
same component.

This patch checks if the plat_lfa_load_auth_image return -EAGAIN
indicating that the platform expects the LFA_PRIME call to be
issued again. This is done by returning LFA_SUCCESS and setting
flags[0] to 1, indicating that LFA_PRIME is incomplete and must
be called again.

Change-Id: Ia3046b5467c50c4c51392bac3fb9e9533f2438db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot

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Merge changes Iad149a2c,Idcd2a07d,Id9429831 into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 3711916
fix(cpus): workaround for Cortex-A715 erratum 2376701
fix(cpus): w

Merge changes Iad149a2c,Idcd2a07d,Id9429831 into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 3711916
fix(cpus): workaround for Cortex-A715 erratum 2376701
fix(cpus): workaround for Cortex-A715 erratum 2409570

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