refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection

Introduce NXP_TBBR_USE_X509 (default 0) to select X.509/mbedTLS
versus CSF header flows, and update fuse_fip and ddr_fip gating
to

refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection

Introduce NXP_TBBR_USE_X509 (default 0) to select X.509/mbedTLS
versus CSF header flows, and update fuse_fip and ddr_fip gating
to use this flag instead of MBEDTLS_DIR.

Change-Id: Ifabf6bbb4a05f57b060e9af3c9ae6b29b8864280
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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test(bl): add short-read negative test scenario

Add an opt-in negative test mode that simulates a short read
for a selected image_id during image loading. This exercises
the partial-read error handl

test(bl): add short-read negative test scenario

Add an opt-in negative test mode that simulates a short read
for a selected image_id during image loading. This exercises
the partial-read error handling path and is intended for CI
validation only.

Disabled by default via build options.

Change-Id: I219b75898e1778c0b263f99a9370425098d52f8f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(fvp): update FVP versions used

Update FVP version used to 11.31.28

Change-Id: Ifb2c09f1335b12ff20a32bbc62e0589c49f623bb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge changes from topic "el3-rmm-itf" into integration

* changes:
docs(rmm): update EL3-RMM contract
feat(rmmd): expand RMM SMC return registers
fix(cm): don't context switch GICv3 registers

Merge changes from topic "el3-rmm-itf" into integration

* changes:
docs(rmm): update EL3-RMM contract
feat(rmmd): expand RMM SMC return registers
fix(cm): don't context switch GICv3 registers on NS<->RL transitions

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docs(rmm): update EL3-RMM contract

Update EL3-RMM context management document to clarify
GIC EL2 registers should not be saved/restored by EL3 in
NS/RL world switches.

expand RMM SMC return registe

docs(rmm): update EL3-RMM contract

Update EL3-RMM context management document to clarify
GIC EL2 registers should not be saved/restored by EL3 in
NS/RL world switches.

expand RMM SMC return registers that RMM can use when
returning from SMC calls,
increasing from 5 registers (x0-x4) to 8 registers (x0-x7).
The responsibility for preserving these registers
when not used lies with RMM.

The RMM-EL3 Interface version is bumped to 2.0 as this
is an incompatible change.

Change-Id: I7f735205e4517995d735dde9453a10986aa88491
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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fix(cm): don't context switch GICv3 registers on NS<->RL transitions

The GICv3 is architectured to solely manage interrupts targeted to
Normal and Secure world. It doesn't manage interrupts targetin

fix(cm): don't context switch GICv3 registers on NS<->RL transitions

The GICv3 is architectured to solely manage interrupts targeted to
Normal and Secure world. It doesn't manage interrupts targeting the
more recently introduced Realm world. Hence the new RMMv2.0
specification mandates that EL3 should not save and restore
the GIC registers on a world switch. This change is not backward
compatible with RMMv1.x ABI.

Note the change in implementation of cm_el2_sysregs_context_save()
and cm_el2_sysregs_context_restore() API as GIC state is not
managed by these APIs anymore.

Add new build flag RMM_V1_COMPAT to support backward compatibility
with RMMv1.x. This flag is currently enabled by default.

This patch is a reworked version of the original patch at:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45658

NOTE: If RMM_V1_COMPAT is not enabled, then RMM_EL3_IFC_VERSION
is bumped to 1.0 which makes it incompatible with an RMM supporting
0.x.

Change-Id: If4c53b85ef31091c254b383ed7b32c39124f0dbb
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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Merge "docs(poplar): update shawn's email in maintainers" into integration

Merge changes Iad777e77,I0eb24083 into integration

* changes:
feat(build): add Mbed TLS submodule
fix(brcm): fix bad Mbed TLS check

docs(poplar): update shawn's email in maintainers

Shawn is no longer with Linaro. Use his personal email in maintainers
file.

Change-Id: Ifddb83989aced0e43bad333d3363d9c7c4aabb7e
Signed-off-by: Sh

docs(poplar): update shawn's email in maintainers

Shawn is no longer with Linaro. Use his personal email in maintainers
file.

Change-Id: Ifddb83989aced0e43bad333d3363d9c7c4aabb7e
Signed-off-by: Shawn Guo <shawn.gsc@gmail.com>

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refactor(bl2): data cache invalidate on bl2 entry

Rely on build options BL2_RUNS_AT_EL3 and BL2_INV_DCACHE to invalidate
the data cache upon BL2 entry and this shouldn't be tied with ENABLE_RME
buil

refactor(bl2): data cache invalidate on bl2 entry

Rely on build options BL2_RUNS_AT_EL3 and BL2_INV_DCACHE to invalidate
the data cache upon BL2 entry and this shouldn't be tied with ENABLE_RME
build flag. This also ensures that if a platform sets
BL2_INV_DCACHE, it takes precedence over feature flags.

This change also restores documentation for BL2_INV_DCACHE, which was
accidentally removed by commit 43f35ef51.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I52bdfe351c730f62d79a518327f57b398c7b29c5

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Merge "feat(rza): add initial BL2 support for RZ/A platforms" into integration

Merge changes from topic "mp/live_activate_sp" into integration

* changes:
docs(spm): describe support for SP live activation and relevant build flags
docs(spm): document ff-a manifest binding f

Merge changes from topic "mp/live_activate_sp" into integration

* changes:
docs(spm): describe support for SP live activation and relevant build flags
docs(spm): document ff-a manifest binding for SP live activation
feat(fvp): implement SP live activation callback
feat(fvp): enable discovery of two Secure Partitions for live activation
feat(fvp): introduce SP live activation component manager
feat(spmd): helpers for SP live activation framework messages
feat(lfa): build flags for SP live activation support
chore(fvp): remove the dummy function fvp_get_partition_info
feat(spmd): support for extended partition info descriptor

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Merge changes from topic "a80x0_nbx-platform-v1" into integration

* changes:
fix(marvell): work around uutils coreutils truncate -s %SIZE bug
fix(a8k): add XFI params for NBX SFI 10G
fix(a8k):

Merge changes from topic "a80x0_nbx-platform-v1" into integration

* changes:
fix(marvell): work around uutils coreutils truncate -s %SIZE bug
fix(a8k): add XFI params for NBX SFI 10G
fix(a8k): mv_ddr path may not be a git repo
feat(a8k): add a80x0_nbx Free Mobile board
feat(a8k): add user callback for skip_image

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feat(rza): add initial BL2 support for RZ/A platforms

This patch introduces the initial BL2 support for Renesas RZ/A
platforms. It adds platform-specific sources, drivers, build files,
and memory co

feat(rza): add initial BL2 support for RZ/A platforms

This patch introduces the initial BL2 support for Renesas RZ/A
platforms. It adds platform-specific sources, drivers, build files,
and memory configuration needed to boot via BL2.

Key changes include:
- Board-specific makefiles for RZ/A3M board.
- Platform helpers and BL2 setup routines.
- Drivers for DDR, GPIO, and CPG drivers.
- Platform headers, register definitions, and configuration files.
- Scripts and makefiles for image generation.

Change-Id: I6cea17a76633998d746e7c7c429da9a5bd09ef0c
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

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feat(build): add Mbed TLS submodule

This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building confi

feat(build): add Mbed TLS submodule

This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building configurations which require it, as the build system will
now look inside the `contrib` directory if the parameter is missing.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: Mbed TLS is now included in the TF-A repository, and it
is no longer a requirement to pass `MBEDTLS_DIR` to the build system.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: Iad777e77936d1c373065f17fe5c4aadc45e56b64
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(spm): describe support for SP live activation and relevant build flags

This patch documents the support for SP live activation by a reference
SPM implementation as well as provides the guidance

docs(spm): describe support for SP live activation and relevant build flags

This patch documents the support for SP live activation by a reference
SPM implementation as well as provides the guidance for platform
integrators to build Logical Secure Partition, which is needed to
orchestrate live activation of an SP in coordination with SPMC.

The corresponding build flags have been documented as well.

Change-Id: I88920344267f86f5e9916ea3632de78af32469ef
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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docs(spm): document ff-a manifest binding for SP live activation

This patch documents the FF-A manifest bindings for supporting live
activation of Secure Partitions managed by SPMC in lower ELs.

Ch

docs(spm): document ff-a manifest binding for SP live activation

This patch documents the FF-A manifest bindings for supporting live
activation of Secure Partitions managed by SPMC in lower ELs.

Change-Id: I1bd90e1d4b8371a744b42e4f2a7d9ec3afe5dbf8
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "docs(maintainers): clean up QTI maintainers list" into integration

docs(maintainers): clean up QTI maintainers list

Drop inactive QTI maintainers with codearora email IDs except Sree who
committed to become active in TF-A upstream code reviews. So update
Sree's ema

docs(maintainers): clean up QTI maintainers list

Drop inactive QTI maintainers with codearora email IDs except Sree who
committed to become active in TF-A upstream code reviews. So update
Sree's email ID and github identity accordingly.

Change-Id: I6d1c34ae323133d111d20226841dc3841f9ada90
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(s32g274ardb): document DDR integration

Document the integration of DDR driver into
the boot process. Document the relocation
of BL31 and BL33 to DDR instead of SRAM.

Additionally, include the

feat(s32g274ardb): document DDR integration

Document the integration of DDR driver into
the boot process. Document the relocation
of BL31 and BL33 to DDR instead of SRAM.

Additionally, include the new build parameter
`DDR_FW_BIN_PATH` which must be provided to
specify the path to the DDR firmware binary.
This firmware is used by the DDR driver to
configure and initialize DDR memory.

Change-Id: Ib9fa850926d3dcd745a93eb4aa44846bbdf3e9d3
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge "refactor(platforms): remove A5DS platform (EOL)" into integration

feat(a8k): add a80x0_nbx Free Mobile board

Add TF-A platform support for the a80x0_nbx board (Free Mobile
Nodebox10G), a network appliance based on the Marvell Armada 8040
SoC with dual CP110 compan

feat(a8k): add a80x0_nbx Free Mobile board

Add TF-A platform support for the a80x0_nbx board (Free Mobile
Nodebox10G), a network appliance based on the Marvell Armada 8040
SoC with dual CP110 companion processors.

Hardware configuration:
- Quad-core ARM Cortex-A72 @ 1.3GHz
- DDR4 memory with ECC support (single channel, 32-bit)
- Dual CP110 companion processors (CP0 and CP1)
- SGMII 1G Ethernet on CP0 lane 5
- I2C buses for peripheral access (CP0: 100kHz, CP1: 400kHz)
- NS16550 UART console at 115200 baud
- eMMC boot via Xenon SDHCI controller

Key features implemented:

1. Ramoops buffer preservation across cold boot (ramoopsies driver)
On ECC-enabled DDR configurations, the memory controller must
scrub all memory during initialization to establish valid parity
bits. This would normally destroy the Linux kernel ramoops buffer
containing crash logs from the previous boot. The ramoopsies
driver intercepts the DDR scrubbing function using the GNU linker
--wrap feature, saving the 32KB ramoops buffer (at 0x3FFF8000) to
SRAM before scrubbing and restoring it afterward. The driver also
handles pending SError exceptions that occur when reading
uninitialized ECC memory by installing a minimal exception vector
that acknowledges and clears them.

2. UART-based skip image recovery mechanism
The platform uses the USER_DEFINED skip image detection callback
to implement software-based boot recovery without requiring a
dedicated GPIO button. Users can trigger recovery mode by holding
the 's' key during early boot, causing the bootloader to load
from the secondary/recovery image instead of the primary firmware.

3. SerDes/ComPhy configuration
PHY porting layer configured with default tuning values for
XFI (10G) and SATA interfaces, following the principle of minimal
bootloader configuration. Advanced SerDes tuning is deferred to
the Linux kernel where it can be more easily adjusted.

The implementation includes comprehensive documentation and a build
verification script to validate proper symbol exports, DDR driver
integration, and flash image format compliance.

Based on original work by Nicolas Schichan <nschichan@freebox.fr>
for the ramoops preservation mechanism and USER_DEFINED skip image
detection concept.

Change-Id: Iaacbb29631f27b47fbf5cc300d8c63aaf1e89e51
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STE

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STEP2
feat(docs): update the feature guide to mention FEAT_IDTE3
fix(cpufeat): remove the feature list from arch_features.h
docs(cpufeat): add analysis of 2022 features
fix(cpus): use hint instruction instead of the psb mnemonic

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Merge "fix(build): use the correct value of host-poetry" into integration

fix(build): use the correct value of host-poetry

The build system reads the POETRY variable and
internally sets host-poetry to the correct path
of the poetry tool. Update the build files to always
u

fix(build): use the correct value of host-poetry

The build system reads the POETRY variable and
internally sets host-poetry to the correct path
of the poetry tool. Update the build files to always
use the internal variable to run the tool.

Change-Id: I5acec9530a80661b0dcda8fba64abaa9d09165e9
Signed-off-by: Andrei Homescu <ahomescu@xwf.google.com>

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