| 7096a45a | 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Fix typos and misspellings" into integration |
| 0bd1a2e9 | 29-Oct-2020 |
Chris Kay <chris.kay@arm.com> |
docs: Update changelog for v2.4 release
Change-Id: I67c9db2fc6d4b83fec2d001745b9305102d4a2ae
Signed-off-by: Chris Kay <chris.kay@arm.com> |
| 9bbc03a6 | 12-Nov-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being revert
Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
show more ...
|
| 95ed9a9e | 12-Nov-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being revert
Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
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|
| 5d9101b3 | 12-Nov-2020 |
David Horstmann <david.horstmann@arm.com> |
Fix typos and misspellings
Fix a number of typos and misspellings in TF-A
documentation and comments.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9
Fix typos and misspellings
Fix a number of typos and misspellings in TF-A
documentation and comments.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee
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|
| 942d0c7c | 12-Nov-2020 |
Michal Simek <michal.simek@xilinx.com> |
Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms
Jolly left the company and Siva (DP) has moved to different possition
that's why it is necessary to change code ownership.
Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms
Jolly left the company and Siva (DP) has moved to different possition
that's why it is necessary to change code ownership.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I546d9a0f7a2abd0c7a65be807725bc609160f3b2
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|
| 95fca110 | 24-Oct-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "docs: marvell: update ddr3 build instructions" into integration |
| c4d919ee | 21-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tc0_sel2_spmc" into integration
* changes:
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
lib: el3_runtime: Conditionally save/restore EL2 NEVE regis
Merge changes from topic "tc0_sel2_spmc" into integration
* changes:
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
show more ...
|
| bd260fcb | 20-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: code review guidelines" into integration |
| 062f8aaf | 28-May-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform w
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.
Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
show more ...
|
| 3bd19575 | 08-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Remove deprecated information
There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the
docs: Remove deprecated information
There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the document.
Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| c20bbfa1 | 08-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Update Release information for v2.5
Updated tentative code freeze and release target date
for v2.5 release.
Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badark
docs: Update Release information for v2.5
Updated tentative code freeze and release target date
for v2.5 release.
Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| f329442c | 08-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Update code freeze and release target date for v2.4
Updated code freeze and release information date for v2.4
release.
Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0
Signed-off-by: Mani
docs: Update code freeze and release target date for v2.4
Updated code freeze and release information date for v2.4
release.
Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| dfe577a8 | 14-Oct-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Don't return error information from console_flush" into integration |
| 63544012 | 13-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
docs: update STM32MP1 with versions details
After introducing the new STM32MP1 SoC versions in patch [1], the
document describing STM32MP1 platform is updated with the information
given in the patch
docs: update STM32MP1 with versions details
After introducing the new STM32MP1 SoC versions in patch [1], the
document describing STM32MP1 platform is updated with the information
given in the patch commit message.
[1]: stm32mp1: add support for new SoC profiles
Change-Id: I6d7ce1a3c29678ddac78a6685f5d5daf28c3c3a1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| 583079ae | 07-Oct-2020 |
Pali Rohár <pali@kernel.org> |
docs: marvell: update ddr3 build instructions
Add information about 2GB variant of EspressoBin V5 and use Marvell git
branches which contain required fixes for EspressoBin.
Signed-off-by: Pali Rohá
docs: marvell: update ddr3 build instructions
Add information about 2GB variant of EspressoBin V5 and use Marvell git
branches which contain required fixes for EspressoBin.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1db510f1576f4762259ad7b0c10024b8ab434a59
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|
| 831b0e98 | 05-Aug-2020 |
Jimmy Brisson <jimmy.brisson@arm.com> |
Don't return error information from console_flush
And from crash_console_flush.
We ignore the error information return by console_flush in _every_
place where we call it, and casting the return typ
Don't return error information from console_flush
And from crash_console_flush.
We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.
Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
show more ...
|
| 35c75377 | 10-Sep-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A77 erratum 1925769
Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1
Workaround for Cortex A77 erratum 1925769
Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1 register, there is a small performance cost
(<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
show more ...
|
| 3fad9960 | 06-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "doc: Update list of supported FVP platforms" into integration |
| eeb77da6 | 06-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
plat: marvell: armada: a3k: allow image load to RAM address 0
marvell: comphy: cp110: add support for USB comphy polarity invert
marvell: comphy: cp110: add support for SATA comphy polarity invert
marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
drivers: marvell: mochi: Update AP incoming masters secure level
plat: marvell: armada: add ccu window for workaround errata-id 3033912
plat: marvell: ap806: implement workaround for errata-id FE-4265711
show more ...
|
| f8dee97b | 05-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Workaround for Cortex A76 erratum 1868343" into integration |
| 1f19411a | 17-Aug-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: code review guidelines
Document the code review process in TF-A.
Specifically:
* Give an overview of code review and best practices.
* Give guidelines for the participants in code review.
docs: code review guidelines
Document the code review process in TF-A.
Specifically:
* Give an overview of code review and best practices.
* Give guidelines for the participants in code review.
* Outline responsibilities of each type of participant.
* Explain the Gerrit labels used in the review process.
Change-Id: I519ca4b2859601a7b897706e310f149a0c92e390
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: David Horstmann <david.horstmann@arm.com>
show more ...
|
| 5ecfd890 | 04-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration |
| 1d935a1b | 04-Oct-2020 |
Marcin Wojtas <mw@semihalf.com> |
docs: marvell: update mv_ddr branch
Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.
Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Si
docs: marvell: update mv_ddr branch
Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.
Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| 55ff05f3 | 29-Sep-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1868343
Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_
Workaround for Cortex A76 erratum 1868343
Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.
This workaround is the same as workarounds for errata 1262606 and
1275112, so all 3 have been combined into one function call.
SDEN can be found here:
https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d
show more ...
|