1/* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* -------------------------------------------------- 25 * Errata Workaround for Cortex-A710 Erratum 1987031. 26 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 27 * open. 28 * Inputs: 29 * x0: variant[4:7] and revision[0:3] of current cpu. 30 * Shall clobber: x0-x17 31 * -------------------------------------------------- 32 */ 33func errata_a710_1987031_wa 34 /* Check revision. */ 35 mov x17, x30 36 bl check_errata_1987031 37 cbz x0, 1f 38 39 /* Apply instruction patching sequence */ 40 ldr x0,=0x6 41 msr S3_6_c15_c8_0,x0 42 ldr x0,=0xF3A08002 43 msr S3_6_c15_c8_2,x0 44 ldr x0,=0xFFF0F7FE 45 msr S3_6_c15_c8_3,x0 46 ldr x0,=0x40000001003ff 47 msr S3_6_c15_c8_1,x0 48 ldr x0,=0x7 49 msr S3_6_c15_c8_0,x0 50 ldr x0,=0xBF200000 51 msr S3_6_c15_c8_2,x0 52 ldr x0,=0xFFEF0000 53 msr S3_6_c15_c8_3,x0 54 ldr x0,=0x40000001003f3 55 msr S3_6_c15_c8_1,x0 56 isb 571: 58 ret x17 59endfunc errata_a710_1987031_wa 60 61func check_errata_1987031 62 /* Applies to r0p0, r1p0 and r2p0 */ 63 mov x1, #0x20 64 b cpu_rev_var_ls 65endfunc check_errata_1987031 66 67 /* ---------------------------------------------------- 68 * HW will do the cache maintenance while powering down 69 * ---------------------------------------------------- 70 */ 71func cortex_a710_core_pwr_dwn 72 /* --------------------------------------------------- 73 * Enable CPU power down bit in power control register 74 * --------------------------------------------------- 75 */ 76 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 77 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 78 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 79 isb 80 ret 81endfunc cortex_a710_core_pwr_dwn 82 83 /* 84 * Errata printing function for Cortex A710. Must follow AAPCS. 85 */ 86#if REPORT_ERRATA 87func cortex_a710_errata_report 88 stp x8, x30, [sp, #-16]! 89 90 bl cpu_get_rev_var 91 mov x8, x0 92 93 /* 94 * Report all errata. The revision-variant information is passed to 95 * checking functions of each errata. 96 */ 97 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 98 99 ldp x8, x30, [sp], #16 100 ret 101endfunc cortex_a710_errata_report 102#endif 103 104func cortex_a710_reset_func 105 mov x19, x30 106 107 /* Disable speculative loads */ 108 msr SSBS, xzr 109 110 bl cpu_get_rev_var 111 mov x18, x0 112 113#if ERRATA_A710_1987031 114 mov x0, x18 115 bl errata_a710_1987031_wa 116#endif 117 118 isb 119 ret x19 120endfunc cortex_a710_reset_func 121 122 /* --------------------------------------------- 123 * This function provides Cortex-A710 specific 124 * register information for crash reporting. 125 * It needs to return with x6 pointing to 126 * a list of register names in ascii and 127 * x8 - x15 having values of registers to be 128 * reported. 129 * --------------------------------------------- 130 */ 131.section .rodata.cortex_a710_regs, "aS" 132cortex_a710_regs: /* The ascii list of register names to be reported */ 133 .asciz "cpuectlr_el1", "" 134 135func cortex_a710_cpu_reg_dump 136 adr x6, cortex_a710_regs 137 mrs x8, CORTEX_A710_CPUECTLR_EL1 138 ret 139endfunc cortex_a710_cpu_reg_dump 140 141declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 142 cortex_a710_reset_func, \ 143 cortex_a710_core_pwr_dwn 144