Merge changes I32c5be5d,I15a652a0 into integration

* changes:
fix(qemu): add reason parameter to MEC update
refactor(rmmd): modify MEC update call to meet FIRME

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[1] https://developer.arm.com/documentation/den0149/1-0alp0/

Change-Id: I15a652a021561edca16e79d127e6f08975cf1361
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes from topic "mp/sp_lifecycle" into integration

* changes:
docs: ff-a manifest bindings for SP lifecycle support
feat(spmd): support for FFA_ABORT invocation from SWd

docs: ff-a manifest binding to document SPMC

The FF-A manifest binding section was extended
to document the SPMC manifest as well.

The configuration is for the SPMD, which is common
to SPMC impleme

docs: ff-a manifest binding to document SPMC

The FF-A manifest binding section was extended
to document the SPMC manifest as well.

The configuration is for the SPMD, which is common
to SPMC implementations.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If8747a701212cedebc4a9dd66f2040443ce5e30f

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docs: ff-a manifest bindings for SP lifecycle support

This patch documents the manifest bindings for SP lifecycle support
as described in the FF-A v1.3 ALP2 specification.

Change-Id: I5d2e80520bc98

docs: ff-a manifest bindings for SP lifecycle support

This patch documents the manifest bindings for SP lifecycle support
as described in the FF-A v1.3 ALP2 specification.

Change-Id: I5d2e80520bc98c8e808da7d3204c2b4d91386536
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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docs(tegra): add note that clang is not supported

This has never worked. Since the general docs indicate that clang is
supported, the Tegra docs should explicitly state that it is not
supported.

Ch

docs(tegra): add note that clang is not supported

This has never worked. Since the general docs indicate that clang is
supported, the Tegra docs should explicitly state that it is not
supported.

Change-Id: I07654e02717a1a53a5d64088f4a79b034030bf26
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>

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feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for BL2 separation

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feat(fwu): documentation for BL2 separation

The separation of BL2 introduce a new flag in the build
option, SEPARATE_BL2_FIP.

Change-Id: I64e231d40376c39112bce66851af9ccb37d37382
Signed-off-by: Xia

feat(fwu): documentation for BL2 separation

The separation of BL2 introduce a new flag in the build
option, SEPARATE_BL2_FIP.

Change-Id: I64e231d40376c39112bce66851af9ccb37d37382
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

Merge "docs(maintainers): add myself as code owner for the GICv5 driver" into integration

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_op

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C
fix(aarch32): make get_cpu_ops_ptr() PCS compliant

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docs(s32g274a): update compilation instructions

Changes to the Poetry memory module have removed
support for the `-f` option, following commit
8daebefe59e ("refactor(memmap)!: change behavioural fla

docs(s32g274a): update compilation instructions

Changes to the Poetry memory module have removed
support for the `-f` option, following commit
8daebefe59e ("refactor(memmap)!: change behavioural flags to commands").

This update replaces `-f` with `footprint` option
to ensure compatibility with the updated memory
module.

Change-Id: I58eb2c5e9ca649c7a00696b0a3b5c8e02fa29c84
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of assembly was
that the get_cpu_ops_ptr() function was not PCS compliant and needed a
wrapper to do that instead. That has now been fixed so move this to C so
it's more readable and more optimise-able by the compiler.

Change-Id: I5fcfe8ddb122dd35d58adc6d44a7484c5c595815
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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Merge "fix(drtm): remove plat_system_reset()" into integration

Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee s

Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee support
feat(imx95): support trusty os
feat(imx95): implement a semaphore for GIC quiescing
feat(imx95): add initial support for i.MX95
feat(imx9): add necessary ele api call support
feat(imx9): add imx9 common code base
refactor(imx): drop the __dead2 attribute
fix(imx): add static attribute for platform specific gic struct
feat(gic): change gic_cpuif_enable/disable to weak
feat(scmi): add i.MX9 SCMI vendor CPU protocol
feat(scmi): add base protocol agent API
feat(scmi): update version to 3.0
build(changelog): update for imx94/95 support

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fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that i

fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that is only implemented on FVP, that conflicts with it.
This sometimes results in failed builds.

DRTM remediation ends with a platform reset. However, there is currently
an error message printed that this is not supported. In this case, the
correct thing to do is to panic and as such this hook is not needed.

Further, the correct sequence to reset the system is different and is
only fully implemented by psci_system_reset(). This is a portable
implementation supported by a wide variety of platform.

So remove plat_system_reset(). Once DRTM remediation properly supports
resetting, the psci_system_reset() function should be used to achieve
reset correctly and portably.

Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs(security): update Advisory TFV-6" into integration

docs(maintainers): add i.MX9 to maintained paths

Add plat/imx/imx9 to maintained paths.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I990e230a99c48ec7aad59195845204620ad0beb8

docs(maintainers): add myself as code owner for the GICv5 driver

I am the author for the driver.

Change-Id: Iee3c6cf6607dbfebccb42ac66197caec69ee66b9
Signed-off-by: Boyan Karatotev <boyan.karatotev

docs(maintainers): add myself as code owner for the GICv5 driver

I am the author for the driver.

Change-Id: Iee3c6cf6607dbfebccb42ac66197caec69ee66b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topics "amd_scmi_in_nopm", "amd_versal2_custom_sip" into integration

* changes:
feat(versal2): add hooks for mmap and early setup
refactor(versal2): add tfa_no_pm flag for scmi

Merge changes from topic "bk/gicv5_full" into integration

* changes:
feat(fvp): add a GICv5 device tree
refactor(fvp): factor out interrupt information from the dts

feat(versal2): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory m

feat(versal2): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory map via custom_mmap_add(). This change may also
require alignment of the MAX_XLAT_TABLE and MAX_XLAT_TABLES macros.
These can be defined within the custom_pkg.mk makefile as follows:

MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

If PLATFORM_STACK_SIZE is not already defined, a default value
should be used. This allows for configurability of the stack size
across different interfaces, such as custom packages. The
custom_early_setup() function enables early low-level operations
to bring the system into a correct state. Support for a custom
SiP service is also added. A basic implementation of
custom_smc_handler() is provided by the platform, while the actual
definition is expected to be supplied by the custom package. This
feature is designed for use by external libraries, such as those
that require status checking. This code introduces a generic
framework for integrating custom logic via the
$(CUSTOM_PKG_PATH)/custom_pkg.mk makefile, including
optional support for custom SMC functionality, which is determined
by the custom package.

Change-Id: I40281acf2dc48be43471b8642e2ab1a93b1cf8f6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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