fix(cpus): workaround for C1-Nano erratum 3754876

C1-Nano erratum 3754876 is a Cat B erratum that applies
to revisions r0p0, and r0p1, and is fixed in r0p2.

This errata can be avoided by executing

fix(cpus): workaround for C1-Nano erratum 3754876

C1-Nano erratum 3754876 is a Cat B erratum that applies
to revisions r0p0, and r0p1, and is fixed in r0p2.

This errata can be avoided by executing a TSB CSYNC
before executing a WFI instruction for power down.
Which prevents core deadlock during power down if
Trace Buffer Extension (TRBE) is enabled.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I3528f08c028b50be848b8d6113d370414261ad48
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Nano erratum 3419531

C1-Nano erratum 3419531 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by setting IMP_CPUACTLR_

fix(cpus): workaround for C1-Nano erratum 3419531

C1-Nano erratum 3419531 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by setting IMP_CPUACTLR_EL1[27] to
1, which disable write streaming for MTE stores when MTE
feature is enabled.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: Ib5103483163a1f93cbb2df8c3b3fcfb2c6d487c6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Nano erratum 3630925

C1-Nano erratum 3630925 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by disable entering full

fix(cpus): workaround for C1-Nano erratum 3630925

C1-Nano erratum 3630925 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata can be avoided by disable entering full
retention mode by setting both IMP_CPUPWRCTLR_EL1[9:7] and
IMP_CPUPWRCTLR_EL1[6:4] to 3'b000.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I61cdf21b50dfb534ce2a1e74c22b06bde9a7c0a7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Nano erratum 3616450

C1-Nano erratum 3616450 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might result in data corruption under
u

fix(cpus): workaround for C1-Nano erratum 3616450

C1-Nano erratum 3616450 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might result in data corruption under
uncommon micro-architectural conditions for SME, SIMD&FP,
or SVE load or store. This can be avoided by setting
IMP_CPUACTLR_EL1[29] to 1. This workaround will reduce
the effectiveness of internal clock gating, and can have
a small impact on power efficiency. During power testing
of sample silicon, Arm recommends not applying the
workaround.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I542be9a051a1f17e93c21bef725f7ede429555f9
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Nano erratum 3516455

C1-Nano erratum 3516455 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might cause the core to deadlock in
str

fix(cpus): workaround for C1-Nano erratum 3516455

C1-Nano erratum 3516455 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

This errata might cause the core to deadlock in
streaming mode when Non-SME instruction abort.
Which can be avoided by restricts address generation
based on speculatively produced data for vector
load/stores accessing 4 vector registers in streaming SVE
mode. The workaround can have a minor impact on
performance in heavy streaming SVE workloads, depending
on the density of the affected instructions

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: Id97fbfd1d76e9dc1a3488ce33e353c032c41e0f1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Nano erratum 3437202

C1-Nano erratum 3437202 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might might lead to data corruption, wh

fix(cpus): workaround for C1-Nano erratum 3437202

C1-Nano erratum 3437202 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might might lead to data corruption, which
can be avoided by seting IMP_CPUACTLR_EL1[26] to 1.
The workaround is expected to have negligible performance
and power impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: If6c12a7a26ccd67496909481a9683151d30d4339
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Nano erratum 3392149

C1-Nano erratum 3392149 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might cause deadlock when receiving an

fix(cpus): workaround for C1-Nano erratum 3392149

C1-Nano erratum 3392149 is a Cat B erratum that applies
to revision r0p0, and is fixed in r0p1.

The erratum might cause deadlock when receiving an I-cache
invalidation, which can be avoided by seting
IMP_CPUACTLR3_EL1[39] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273788/0800/

Change-Id: I530c75acf25ee57efaf7ff58ef4a43508fb6d52a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Neoverse-N3 erratum 3456111
fix(cpus): workaround for Neoverse-N2 erratum 3324339
fix(cpus)

Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Neoverse-N3 erratum 3456111
fix(cpus): workaround for Neoverse-N2 erratum 3324339
fix(cpus): workaround for Neoverse-N1 erratum 3324349

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Merge "fix(cpus): workaround for Neoverse-V2 erratum 3442699" into integration

fix(cpus): workaround for Neoverse-N3 erratum 3456111

Neoverse-N3 erratum 3456111 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.

This errata can be avoided by adding

fix(cpus): workaround for Neoverse-N3 erratum 3456111

Neoverse-N3 erratum 3456111 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973

Change-Id: I1685c2cacbe64ddf70501e8cce94b4fbf03f0ba0
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(cpus): workaround for C1-Pro erratum 3619847" into integration

Merge changes from topic "xl/c1pro-errata" into integration

* changes:
fix(cpus): workaround for C1-Pro erratum 3686597
fix(cpus): workaround for C1-Pro erratum 3300099
fix(cpus): workaround f

Merge changes from topic "xl/c1pro-errata" into integration

* changes:
fix(cpus): workaround for C1-Pro erratum 3686597
fix(cpus): workaround for C1-Pro erratum 3300099
fix(cpus): workaround for C1-Pro erratum 3338470
fix(cpus): workaround for C1-Pro erratum 3362007
fix(cpus): workaround for C1-Pro erratum 3684268
fix(cpus): workaround for C1-Pro erratum 3694158
fix(cpus): workaround for C1-Pro erratum 3706576

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fix(cpus): workaround for Neoverse-N2 erratum 3324339

Neoverse-N2 erratum 3324339 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2 and r0p3 and is still open.

This errata can be avoide

fix(cpus): workaround for Neoverse-N2 erratum 3324339

Neoverse-N2 erratum 3324339 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2 and r0p3 and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442

Change-Id: I6b023279816005cfa459bc6947f60b1a3c0f2380
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse-N1 erratum 3324349

Neoverse-N1 erratum 3324349 is a Cat B erratum that applies
to all revisions <= r4p1, and is still open.

This errata can be avoided by adding a

fix(cpus): workaround for Neoverse-N1 erratum 3324349

Neoverse-N1 erratum 3324349 is a Cat B erratum that applies
to all revisions <= r4p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885747

Change-Id: I1f142027ed73135d78c368be926072c2f73eab46
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3442699

Neoverse-V2 erratum 3442699 applies to r0p0, r0p1, and r0p2
and it is still open.

PE may execute incorrect instructions when icache is enabled.

fix(cpus): workaround for Neoverse-V2 erratum 3442699

Neoverse-V2 erratum 3442699 applies to r0p0, r0p1, and r0p2
and it is still open.

PE may execute incorrect instructions when icache is enabled.
As workaround, Set CPUACTLR_EL1[36] before enabling icache.

SDEN: https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I38edc6ba445223091c3933cbca35b56db491c926
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>
Signed-off-by: Chandrakala Chavva <cchavva@cavium.com>
Reviewed-by: Chandrakala Chavva <cchavva@marvell.com>
Tested-by: Chandrakala Chavva <cchavva@marvell.com>

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fix(cpus): workaround for C1-Pro erratum 3619847

C1-Pro erratum 3619847 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_E

fix(cpus): workaround for C1-Pro erratum 3619847

C1-Pro erratum 3619847 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_EL1[42] to 1.
Only a minor performance drop is expected when mixing SME and
non-SME store instructions.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: Id92e7180df20d973e4e2d112c4f187a561a4d924
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3686597

C1-Pro erratum 3686597 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is fixed in r1p1.

This erratum can be avoided by setting IMP_CPUE

fix(cpus): workaround for C1-Pro erratum 3686597

C1-Pro erratum 3686597 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is fixed in r1p1.

This erratum can be avoided by setting IMP_CPUECTLR_EL1[57]
to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I59a5d9316bf66793eae5dac08102231d0e2640fb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3300099

C1-Pro erratum 3300099 is a Cat B erratum that applies
to revisions r0p0, r1p0, and is fixed in r1p1.

This is workaround for accessing ICH_VMCR_EL2.

fix(cpus): workaround for C1-Pro erratum 3300099

C1-Pro erratum 3300099 is a Cat B erratum that applies
to revisions r0p0, r1p0, and is fixed in r1p1.

This is workaround for accessing ICH_VMCR_EL2.
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: If24d3230c4b4e87fcb831d446cf0d0c68c95ea18
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-V3 erratum 3312417

Neoverse-V3 erratum 3312417 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is fixed in r0p2.

This errata can be avoided by add

fix(cpus): workaround for Neoverse-V3 erratum 3312417

Neoverse-V3 erratum 3312417 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is fixed in r0p2.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: I78a7682cbdf3dbc4c31fcca8cbd892350b998cf4
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3878291

Neoverse V3 erratum 3878291 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by

fix(cpus): workaround for Neoverse V3 erratum 3878291

Neoverse V3 erratum 3878291 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by setting CPUACTLR4_EL1[57]. Setting this
bit causes the PE to treat GPT invalidations as TLBI PAALL, thereby
invalidating all GPT entries. If the physical memory map does not use
addresses with bits 46 or 47 set, then no workaround is necessary.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: I0ebab877b6481a18bec963b95cf2f37c97d8de65
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3864536

Neoverse V3 erratum 3864536 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by

fix(cpus): workaround for Neoverse V3 erratum 3864536

Neoverse V3 erratum 3864536 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: If4b20d941d628b92748b14d027b8127f74005eff
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3782181

Neoverse V3 erratum 3782181 is a Cat B erratum that applies to
revision r0p1 and is fixed in r0p2.

If the erratum condition occurs, then the co

fix(cpus): workaround for Neoverse V3 erratum 3782181

Neoverse V3 erratum 3782181 is a Cat B erratum that applies to
revision r0p1 and is fixed in r0p2.

If the erratum condition occurs, then the core will not leave the
FULL_RET power mode, which will cause the system to deadlock. The
FULL_RET power mode should not be enabled. This can be done by setting
both IMP_CPUPWRCTLR_EL1.WFE_RET_CTL and IMP_CPUPWRCTLR_EL1.WFI_RET_CTL
to 0b000 which is the default value.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: Icfa463cf4888bd48f16a218e7ad399528feca55e
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3734562

Neoverse V3 erratum 3734562 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This erratum can be avoided throu

fix(cpus): workaround for Neoverse V3 erratum 3734562

Neoverse V3 erratum 3734562 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This erratum can be avoided through the following write sequence to
several IMPLEMENTATION DEFINED registers, which will execute a PSB
instruction following the TSB CSYNC instruction. The code sequence
should be applied early in the boot sequence prior to executing a TSB
CSYNC instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: Ib3c35c7e619e6a836c974b7016bb6a4d66da48d6
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3696307

Neoverse V3 erratum 3696307 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

The erratum can be avoided by dis

fix(cpus): workaround for Neoverse V3 erratum 3696307

Neoverse V3 erratum 3696307 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

The erratum can be avoided by disabling the affected prefetcher by
setting CPUACTLR6_EL1[41].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: If274749621549356e41485d0bf09682281df3a9b
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3338470

C1-Pro erratum 3338470 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barr

fix(cpus): workaround for C1-Pro erratum 3338470

C1-Pro erratum 3338470 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I86e2b8f70ceb468c75c0386a790641d51eeea9cb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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