1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 54 55The errata workarounds are implemented for a particular revision or a set of 56processor revisions. This is checked by the reset handler at runtime. Each 57errata workaround is identified by its ``ID`` as specified in the processor's 58errata notice document. The format of the define used to enable/disable the 59errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 60is for example ``A57`` for the ``Cortex_A57`` CPU. 61 62Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 63write errata workaround functions. 64 65All workarounds are disabled by default. The platform is responsible for 66enabling these workarounds according to its requirement by defining the 67errata workaround build flags in the platform specific makefile. In case 68these workarounds are enabled for the wrong CPU revision then the errata 69workaround is not applied. In the DEBUG build, this is indicated by 70printing a warning to the crash console. 71 72In the current implementation, a platform which has more than 1 variant 73with different revisions of a processor has no runtime mechanism available 74for it to specify which errata workarounds should be enabled or not. 75 76The value of the build flags is 0 by default, that is, disabled. A value of 1 77will enable it. 78 79For Cortex-A9, the following errata build flags are defined : 80 81- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 82 CPU. This needs to be enabled for all revisions of the CPU. 83 84For Cortex-A15, the following errata build flags are defined : 85 86- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 87 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 88 89- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92For Cortex-A17, the following errata build flags are defined : 93 94- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 95 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 96 97- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100For Cortex-A35, the following errata build flags are defined : 101 102- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 103 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 104 105For Cortex-A53, the following errata build flags are defined : 106 107- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 108 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 109 110- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 114 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 115 116- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 117 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 118 119- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 120 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 121 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 122 sections. 123 124- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 125 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 126 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 127 ``A53_DISABLE_NON_TEMPORAL_HINT``. 128 129- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 130 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 131 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 132 which are 4kB aligned. 133 134- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 135 CPUs. Though the erratum is present in every revision of the CPU, 136 this workaround is only applied to CPUs from r0p3 onwards, which feature 137 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 138 Earlier revisions of the CPU have other errata which require the same 139 workaround in software, so they should be covered anyway. 140 141- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 142 revisions of Cortex-A53 CPU. 143 144For Cortex-A55, the following errata build flags are defined : 145 146- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 157 158- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 163 164- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 165 revisions of Cortex-A55 CPU. 166 167For Cortex-A57, the following errata build flags are defined : 168 169- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 183 184- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 195 196- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 201 202- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 203 revisions of Cortex-A57 CPU. 204 205For Cortex-A65, the following errata build flags are defined : 206 207- ``ERRATA_A65_1179935``: This applies errata 1179935 workaround to Cortex-A65 208 CPU. This needs to be enabled only for revision r0p0 of the CPU, and is fixed 209 in r1p0. 210 211- ``ERRATA_A65_1227419``: This applies errata 1227419 workaround to Cortex-A65 212 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU and 213 is fixed in r1p1. 214 215- ``ERRATA_A65_1541130``: This applies errata 1541130 workaround to r0p0, r1p0, 216 r1p1, r1p2 revisions of the CPU and is still open. 217 218For Cortex-A72, the following errata build flags are defined : 219 220- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 221 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 222 223- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 224 revisions of Cortex-A72 CPU. 225 226For Cortex-A73, the following errata build flags are defined : 227 228- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 229 CPU. This needs to be enabled only for revision r0p0 of the CPU. 230 231- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 232 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 233 234For Cortex-A75, the following errata build flags are defined : 235 236- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 237 CPU. This needs to be enabled only for revision r0p0 of the CPU. 238 239- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 240 CPU. This needs to be enabled only for revision r0p0 of the CPU. 241 242For Cortex-A76, the following errata build flags are defined : 243 244- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 245 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 246 247- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 248 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 249 250- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 251 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 252 253- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 255 256- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 258 259- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 260 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 261 262- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 263 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 264 265- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 266 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 267 268- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 269 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 270 limitation of errata framework this errata is applied to all revisions 271 of Cortex-A76 CPU. 272 273- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 274 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 275 276- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 277 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 278 279- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 280 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 281 still open. 282 283For Cortex-A77, the following errata build flags are defined : 284 285- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 286 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 287 288- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 289 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 290 291- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 292 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 293 294- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 295 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 296 297- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 298 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 299 300 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 301 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 302 303 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 304 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 305 306For Cortex-A78, the following errata build flags are defined : 307 308- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 309 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 310 311- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 312 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 313 314- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 315 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 316 issue but there is no workaround for that revision. 317 318- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 319 CPU. This needs to be enabled for revisions r0p0 and r1p0. 320 321- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 322 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 323 324- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 325 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 326 is present in r0p0 but there is no workaround. It is still open. 327 328- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 329 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 330 it is still open. 331 332- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 333 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 334 it is still open. 335 336- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 337 CPU, this erratum affects system configurations that do not use an ARM 338 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 339 and r1p2 and it is still open. 340 341- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 342 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 343 it is still open. 344 345- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 346 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 347 it is still open. 348 349- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 350 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 351 it is still open. 352 353For Cortex-A78AE, the following errata build flags are defined : 354 355- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 356 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 357 This erratum is still open. 358 359- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 360 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 361 erratum is still open. 362 363- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 364 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 365 This erratum is still open. 366 367- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 368 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 369 erratum is still open. 370 371- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 372 Cortex-A78AE CPU. This erratum affects system configurations that do not use 373 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 374 r0p2. This erratum is still open. 375 376For Cortex-A78C, the following errata build flags are defined : 377 378- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 379 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 380 fixed in r0p1. 381 382- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 383 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 384 fixed in r0p1. 385 386- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 387 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 388 it is still open. 389 390- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 391 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 392 erratum is still open. 393 394- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 395 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 396 erratum is still open. 397 398- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 399 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 400 erratum is still open. 401 402- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 403 Cortex-A78C CPU, this erratum affects system configurations that do not use 404 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 405 and is still open. 406 407- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 408 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 409 This erratum is still open. 410 411- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 412 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 413 This erratum is still open. 414 415- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 416 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 417 This erratum is still open. 418 419For Cortex-X1 CPU, the following errata build flags are defined: 420 421- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 422 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 423 424- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 425 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 426 427- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 428 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 429 430For Neoverse N1, the following errata build flags are defined : 431 432- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 433 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 434 435- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 436 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 437 438- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 439 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 440 441- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 442 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 443 444- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 445 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 446 447- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 448 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 449 450- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 451 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 452 453- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 454 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 455 456- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 457 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 458 459- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 460 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 461 462- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 463 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 464 465- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 466 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 467 468- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 469 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 470 revisions r0p0, r1p0, and r2p0 there is no workaround. 471 472- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 473 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 474 still open. 475 476For Neoverse V1, the following errata build flags are defined : 477 478- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 479 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 480 r1p0. 481 482- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 483 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 484 in r1p1. 485 486- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 487 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 488 in r1p1. 489 490- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 491 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 492 in r1p1. 493 494- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 495 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 496 497- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 498 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 499 CPU. 500 501- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 502 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 503 issue is present in r0p0 as well but there is no workaround for that 504 revision. It is still open. 505 506- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 507 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 508 CPU. It is still open. 509 510- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 511 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 512 issue is present in r0p0 as well but there is no workaround for that 513 revision. It is still open. 514 515- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 516 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 517 the CPU. 518 519- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 520 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 521 It has been fixed in r1p2. 522 523- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 524 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 525 It is still open. 526 527- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 528 CPU, this erratum affects system configurations that do not use an ARM 529 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 530 It has been fixed in r1p2. 531 532- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 533 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 534 CPU. It is still open. 535 536- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 537 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 538 CPU. It is still open. 539 540- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 541 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 542 CPU. It is still open. 543 544For Neoverse V2, the following errata build flags are defined : 545 546- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 547 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 548 r0p2. 549 550- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 551 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 552 r0p2. 553 554- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 555 CPU, this affects system configurations that do not use and ARM interconnect 556 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 557 in r0p2. 558 559- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 560 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 561 r0p2. 562 563- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 564 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 565 r0p2. 566 567- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 568 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 569 r0p2. 570 571- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 572 CPU, this affects all configurations. This needs to be enabled for revisions 573 r0p0 and r0p1. It has been fixed in r0p2. 574 575- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 576 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 577 still open. 578 579- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 580 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 581 the CPU. It is fixed in r0p2. 582 583For Neoverse V3, the following errata build flags are defined : 584 585- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 586 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 587 588- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 589 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 590 is still open. 591 592For Cortex-A710, the following errata build flags are defined : 593 594- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 595 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 596 been fixed in r2p0. 597 598- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 599 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 600 It has been fixed in r2p0. 601 602- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 603 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 604 It has been fixed in r2p0. 605 606- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 607 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 608 It has been fixed in r2p0. 609 610- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 611 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 612 r2p0 of the CPU. It is still open. 613 614- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 615 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 616 r2p0 of the CPU. It is still open. 617 618- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 619 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 620 and is still open. 621 622- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 623 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 624 of the CPU and is still open. 625 626- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 627 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 628 is still open. 629 630- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 631 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 632 of the CPU and is fixed in r2p1. 633 634- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 635 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 636 of the CPU and is fixed in r2p1. 637 638- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 639 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 640 and is fixed in r2p1. 641 642- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 643 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 644 of the CPU and is fixed in r2p1. 645 646- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 647 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 648 r2p1 of the CPU and is still open. 649 650- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 651 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 652 of the CPU and is fixed in r2p1. 653 654- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 655 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 656 of the CPU and is fixed in r2p1. 657 658- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 659 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 660 of the CPU and is fixed in r2p1. 661 662- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 663 CPU, and applies to system configurations that do not use and ARM 664 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 665 is still open. 666 667- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 668 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 669 r2p1 of the CPU and is still open. 670 671- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 672 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 673 r2p1 of the CPU and is still open. 674 675- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 676 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 677 CPU and is still open. 678 679- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 680 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 681 CPU and is still open. 682 683For Neoverse N2, the following errata build flags are defined : 684 685- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 686 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 687 688- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 689 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 690 691- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 692 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 693 694- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 695 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 696 697- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 698 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 699 700- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 701 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 702 703- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 704 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 705 706- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 707 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 708 709- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 710 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 711 712- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 713 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 714 715- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 716 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 717 r0p1. 718 719- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 720 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 721 r0p1. 722 723- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 724 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 725 it is fixed in r0p3. 726 727- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 728 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 729 730- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 731 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 732 r0p1. 733 734- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 735 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 736 in r0p3. 737 738- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 739 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 740 in r0p3. 741 742- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 743 CPU, this erratum affects system configurations that do not use and ARM 744 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 745 It is fixed in r0p3. 746 747- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 748 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 749 in r0p3. 750 751- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 752 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 753 still open. 754 755For Neoverse N3, the following errata build flags are defined : 756 757- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 758 CPU. This needs to be enabled for revisions r0p0 and is still open. 759 760For Cortex-X2, the following errata build flags are defined : 761 762- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 763 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 764 765- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 766 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 767 is fixed in r2p0. 768 769- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 770 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 771 is fixed in r2p0. 772 773- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 774 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 775 is fixed in r2p0. 776 777- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 778 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 779 in r2p0. 780 781- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 782 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 783 CPU, it is fixed in r2p1. 784 785- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 786 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 787 CPU, it is fixed in r2p1. 788 789- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 790 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 791 CPU, it is fixed in r2p1. 792 793- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 794 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 795 in r2p1. 796 797- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 798 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 799 CPU, it is fixed in r2p1. 800 801- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 802 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 803 in r2p1. 804 805- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 806 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 807 CPU, it is fixed in r2p1. 808 809- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 810 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 811 CPU, it is fixed in r2p1. 812 813- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 814 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 815 CPU and is still open. 816 817- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 818 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 819 CPU, it is fixed in r2p1. 820 821- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 822 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 823 CPU, it is fixed in r2p1. 824 825- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 826 CPU and affects system configurations that do not use an Arm interconnect IP. 827 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 828 still open. 829 830- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 831 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 832 CPU and is still open. 833 834- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 835 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 836 CPU and is still open. 837 838- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 839 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 840 CPU and is still open. 841 842- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 843 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 844 CPU and is still open. 845 846For Cortex-X3, the following errata build flags are defined : 847 848- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 849 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 850 is fixed in r1p1. 851 852- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 853 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 854 fixed in r1p2. 855 856- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 857 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 858 of the CPU, it is fixed in r1p1. 859 860- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 861 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 862 of the CPU, it is fixed in r1p1. 863 864- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 865 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 866 CPU, it is fixed in r1p2. 867 868- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 869 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 870 It is fixed in r1p1. 871 872- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 873 CPU and affects system configurations that do not use an ARM interconnect 874 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 875 in r1p2. 876 877- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 878 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 879 r1p1. It is fixed in r1p2. 880 881- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 882 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 883 fixed in r1p2. 884 885- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 886 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 887 CPU. It is fixed in r1p2. 888 889- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 890 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 891 of the CPU. It is still open. 892 893- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 894 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 895 of the CPU. It is still open. 896 897- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 898 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 899 of the CPU and it is still open. 900 901- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 902 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 903 the CPU. It is fixed in r1p2. 904 905For Cortex-X4, the following errata build flags are defined : 906 907- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 908 CPU and affects system configurations that do not use an Arm interconnect IP. 909 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 910 The workaround for this erratum is not implemented in EL3, but the flag can 911 be enabled/disabled at the platform level. The flag is used when the errata ABI 912 feature is enabled and can assist the Kernel in the process of 913 mitigation of the erratum. 914 915- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 916 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 917 r0p2. 918 919- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 920 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 921 in r0p2. 922 923- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 924 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 925 926- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 927 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 928 929- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 930 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 931 932- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 933 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 934 935- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 936 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 937 938- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 939 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 940 941- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 942 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 943 944- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 945 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 946 It is still open. 947 948- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 949 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 950 It is still open. 951 952For Cortex-X925, the following errata build flags are defined : 953 954- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 955 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 956 957- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 958 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 959 960For Cortex-A510, the following errata build flags are defined : 961 962- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 963 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 964 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 965 966- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 967 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 968 r0p2, r0p3 and r1p0, it is fixed in r1p1. 969 970- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 971 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 972 r0p2, it is fixed in r0p3. 973 974- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 975 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 976 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 977 workaround for those revisions. 978 979- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 980 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 981 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 982 workaround for those revisions. 983 984- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 985 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 986 r0p2, r0p3 and r1p0, it is fixed in r1p1. 987 988- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 989 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 990 in r1p1. 991 992- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 993 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 994 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 995 ENABLE_MPMM=1. 996 997- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 998 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 999 r0p3 and r1p0, it is fixed in r1p1. 1000 1001- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 1002 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1003 r0p3 and r1p0, it is fixed in r1p1. 1004 1005- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 1006 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1007 r0p3, r1p0 and r1p1. It is fixed in r1p2. 1008 1009- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 1010 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1011 r0p3, r1p0, r1p1, and is fixed in r1p2. 1012 1013- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1014 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1015 fixed in r1p2. 1016 1017- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1018 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1019 r0p3, r1p0, r1p1. It is fixed in r1p2. 1020 1021- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1022 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1023 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1024 1025- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1026 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1027 r1p0, r1p1, r1p2 and r1p3 and is still open. 1028 1029- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1030 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1031 r1p0, r1p1, r1p2 and r1p3 and is still open. 1032 1033- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1034 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1035 r1p0, r1p1, r1p2 and r1p3 and is still open. 1036 1037For Cortex-A520, the following errata build flags are defined : 1038 1039- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1040 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1041 CPU and is still open. 1042 1043- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1044 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1045 It is still open. 1046 1047- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1048 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1049 It is fixed in r0p2. 1050 1051For Cortex-A715, the following errata build flags are defined : 1052 1053- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1054 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1055 It is fixed in r1p1. 1056 1057- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1058 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1059 fixed in r1p1. 1060 1061- ``ERRATA_A715_2376701``: This applies errata 2376701 workaround to 1062 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1063 fixed in r1p1. 1064 1065- ``ERRATA_A715_2409570``: This applies errata 2409570 workaround to 1066 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1067 It is fixed in r1p1. This errata also applies to r0p0 but that revision has a 1068 different workaround, and since r0p0 is not used in production hardware it is 1069 not implemented. 1070 1071- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1072 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1073 when SPE(Statistical profiling extension)=True. The errata is fixed 1074 in r1p1. 1075 1076- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1077 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1078 It is fixed in r1p1. 1079 1080- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1081 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1082 workaround for revision r0p0. It is fixed in r1p1. 1083 1084- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1085 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1086 It is fixed in r1p1. 1087 1088- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1089 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1090 and r1p1. It is fixed in r1p2. 1091 1092- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1093 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1094 r1p1 and r1p2. It is fixed in r1p3. 1095 1096- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1097 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1098 r1p2 and r1p3. It is still open. 1099 1100- ``ERRATA_A715_3711916``: This applies errata 3711916 workaround to 1101 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1102 r1p1, r1p2 and r1p3. It is still open. 1103 1104For Cortex-A720, the following errata build flags are defined : 1105 1106- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1107 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1108 It is fixed in r0p2. 1109 1110- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1111 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1112 It is fixed in r0p2. 1113 1114- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1115 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1116 It is fixed in r0p2. 1117 1118- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1119 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1120 It is fixed in r0p2. 1121 1122- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1123 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1124 It is fixed in r0p2. 1125 1126- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1127 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1128 and r0p2. It is still open. 1129 1130- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1131 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1132 and r0p2. It is still open. 1133 1134For Cortex-A720_AE, the following errata build flags are defined : 1135 1136- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1137 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1138 It is still open. 1139 1140For Cortex-A725, the following errata build flags are defined : 1141 1142- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1143 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1144 It is fixed in r0p2. 1145 1146DSU Errata Workarounds 1147---------------------- 1148 1149Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1150Shared Unit) errata. The DSU errata details can be found in the respective Arm 1151documentation: 1152 1153- `Arm DSU Software Developers Errata Notice`_. 1154 1155Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1156document. Thus, the build flags which enable/disable the errata workarounds 1157have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1158of DSU errata workarounds are similar to `CPU errata workarounds`_. 1159 1160For DSU errata, the following build flags are defined: 1161 1162- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1163 affected DSU configurations. This errata applies only for those DSUs that 1164 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1165 workaround results in increased DSU power consumption on idle. 1166 1167- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1168 affected DSU configurations. This errata applies only for those DSUs that 1169 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1170 r2p0 it is fixed). However, please note that this workaround results in 1171 increased DSU power consumption on idle. 1172 1173- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1174 affected DSU configurations. This errata applies for those DSUs with 1175 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1176 please note that this workaround results in increased DSU power consumption 1177 on idle. 1178 1179- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1180 affected DSU-120 configurations. This erratum applies to some r2p0 1181 implementations and is fixed in r2p1. The affected r2p0 implementations 1182 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1183 and making sure it's clear. 1184 1185CPU Specific optimizations 1186-------------------------- 1187 1188This section describes some of the optimizations allowed by the CPU micro 1189architecture that can be enabled by the platform as desired. 1190 1191- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1192 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1193 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1194 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1195 is a known safe deviation from the Cortex-A57 TRM defined power down 1196 sequence. Each Cortex-A57 based platform must make its own decision on 1197 whether to use the optimization. 1198 1199- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1200 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1201 in a way most programmers expect, and will most probably result in a 1202 significant speed degradation to any code that employs them. The Armv8-A 1203 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1204 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1205 flag enforces this behaviour. This needs to be enabled only for revisions 1206 <= r0p3 of the CPU and is enabled by default. 1207 1208- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1209 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1210 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1211 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1212 `Cortex-A57 Software Optimization Guide`_. 1213 1214- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1215 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1216 this bit only if their memory system meets the requirement that cache 1217 line fill requests from the Cortex-A57 processor are atomic. Each 1218 Cortex-A57 based platform must make its own decision on whether to use 1219 the optimization. This flag is disabled by default. 1220 1221- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1222 level cache(LLC) is present in the system, and that the DataSource field 1223 on the master CHI interface indicates when data is returned from the LLC. 1224 This is used to control how the LL_CACHE* PMU events count. 1225 Default value is 0 (Disabled). 1226 1227- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1228 on the Neoverse N2 core. This is used during performance analysis to get clean 1229 and repeatable measurements of the cache by preventing speculative data fetches 1230 from interfering with benchmark results. 1231 Default value is 0 (Disabled). 1232 1233GIC Errata Workarounds 1234---------------------- 1235- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1236 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1237 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1238 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1239 then this flag is enabled; otherwise, it is 0 (Disabled). 1240 1241-------------- 1242 1243*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1244 1245.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1246.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1247.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1248.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1249.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1250.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1251