1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a65.h> 12#include <cpu_macros.S> 13#include <dsu_macros.S> 14#include <plat_macros.S> 15 16/* Hardware handled coherency */ 17#if !HW_ASSISTED_COHERENCY 18#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS 23#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a65 27 28workaround_reset_start cortex_a65, ERRATUM(936184), ERRATA_DSU_936184 29 errata_dsu_936184_wa_impl 30workaround_reset_end cortex_a65, ERRATUM(936184) 31 32check_erratum_custom_start cortex_a65, ERRATUM(936184) 33 check_errata_dsu_936184_impl 34 ret 35check_erratum_custom_end cortex_a65, ERRATUM(936184) 36 37workaround_reset_start cortex_a65, ERRATUM(1179935), ERRATA_A65_1179935 38 sysreg_bit_set CORTEX_A65_CPUACTLR_EL1, BIT(49) 39workaround_reset_end cortex_a65, ERRATUM(1179935) 40 41check_erratum_ls cortex_a65, ERRATUM(1179935), CPU_REV(0, 0) 42 43workaround_reset_start cortex_a65, ERRATUM(1227419), ERRATA_A65_1227419 44 sysreg_bit_set CORTEX_A65_CPUACTLR_EL1, BIT(51) 45workaround_reset_end cortex_a65, ERRATUM(1227419) 46 47check_erratum_ls cortex_a65, ERRATUM(1227419), CPU_REV(1, 0) 48 49cpu_reset_func_start cortex_a65 50cpu_reset_func_end cortex_a65 51 52func cortex_a65_cpu_pwr_dwn 53 mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 54 orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 55 msr CORTEX_A65_CPUPWRCTLR_EL1, x0 56 isb 57 ret 58endfunc cortex_a65_cpu_pwr_dwn 59 60.section .rodata.cortex_a65_regs, "aS" 61cortex_a65_regs: /* The ascii list of register names to be reported */ 62 .asciz "cpuectlr_el1", "" 63 64func cortex_a65_cpu_reg_dump 65 adr x6, cortex_a65_regs 66 mrs x8, CORTEX_A65_ECTLR_EL1 67 ret 68endfunc cortex_a65_cpu_reg_dump 69 70declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ 71 cortex_a65_reset_func, \ 72 cortex_a65_cpu_pwr_dwn 73