1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a76ae.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a76ae 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 31 32workaround_reset_start cortex_a76ae, ERRATUM(1931427), ERRATA_A76AE_1931427 33 sysreg_bit_set CORTEX_A76AE_CPUACTLR2_EL1, BIT(2) 34workaround_reset_end cortex_a76ae, ERRATUM(1931427) 35 36check_erratum_ls cortex_a76ae, ERRATUM(1931427), CPU_REV(1, 0) 37 38workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 39#if IMAGE_BL31 40 /* 41 * The Cortex-A76ae generic vectors are overridden to apply errata 42 * mitigation on exception entry from lower ELs. 43 */ 44 override_vector_table wa_cve_vbar_cortex_a76ae 45 isb 46#endif /* IMAGE_BL31 */ 47workaround_reset_end cortex_a76ae, CVE(2022, 23960) 48 49cpu_reset_func_start cortex_a76ae 50cpu_reset_func_end cortex_a76ae 51 52 /* ---------------------------------------------------- 53 * HW will do the cache maintenance while powering down 54 * ---------------------------------------------------- 55 */ 56func cortex_a76ae_core_pwr_dwn 57 sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK 58 isb 59 ret 60endfunc cortex_a76ae_core_pwr_dwn 61 62 /* --------------------------------------------- 63 * This function provides cortex_a76ae specific 64 * register information for crash reporting. 65 * It needs to return with x6 pointing to 66 * a list of register names in ascii and 67 * x8 - x15 having values of registers to be 68 * reported. 69 * --------------------------------------------- 70 */ 71.section .rodata.cortex_a76ae_regs, "aS" 72cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 73 .asciz "cpuectlr_el1", "" 74 75func cortex_a76ae_cpu_reg_dump 76 adr x6, cortex_a76ae_regs 77 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 78 ret 79endfunc cortex_a76ae_cpu_reg_dump 80 81declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ 82 cortex_a76ae_core_pwr_dwn 83