1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 54 55The errata workarounds are implemented for a particular revision or a set of 56processor revisions. This is checked by the reset handler at runtime. Each 57errata workaround is identified by its ``ID`` as specified in the processor's 58errata notice document. The format of the define used to enable/disable the 59errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 60is for example ``A57`` for the ``Cortex_A57`` CPU. 61 62Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 63write errata workaround functions. 64 65All workarounds are disabled by default. The platform is responsible for 66enabling these workarounds according to its requirement by defining the 67errata workaround build flags in the platform specific makefile. In case 68these workarounds are enabled for the wrong CPU revision then the errata 69workaround is not applied. In the DEBUG build, this is indicated by 70printing a warning to the crash console. 71 72In the current implementation, a platform which has more than 1 variant 73with different revisions of a processor has no runtime mechanism available 74for it to specify which errata workarounds should be enabled or not. 75 76The value of the build flags is 0 by default, that is, disabled. A value of 1 77will enable it. 78 79For Cortex-A9, the following errata build flags are defined : 80 81- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 82 CPU. This needs to be enabled for all revisions of the CPU. 83 84For Cortex-A15, the following errata build flags are defined : 85 86- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 87 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 88 89- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92For Cortex-A17, the following errata build flags are defined : 93 94- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 95 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 96 97- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100For Cortex-A35, the following errata build flags are defined : 101 102- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 103 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 104 105For Cortex-A53, the following errata build flags are defined : 106 107- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 108 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 109 110- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 114 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 115 116- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 117 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 118 119- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 120 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 121 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 122 sections. 123 124- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 125 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 126 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 127 ``A53_DISABLE_NON_TEMPORAL_HINT``. 128 129- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 130 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 131 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 132 which are 4kB aligned. 133 134- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 135 CPUs. Though the erratum is present in every revision of the CPU, 136 this workaround is only applied to CPUs from r0p3 onwards, which feature 137 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 138 Earlier revisions of the CPU have other errata which require the same 139 workaround in software, so they should be covered anyway. 140 141- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 142 revisions of Cortex-A53 CPU. 143 144For Cortex-A55, the following errata build flags are defined : 145 146- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 157 158- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 163 164- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 165 revisions of Cortex-A55 CPU. 166 167For Cortex-A57, the following errata build flags are defined : 168 169- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 183 184- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 195 196- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 201 202- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 203 revisions of Cortex-A57 CPU. 204 205For Cortex-A72, the following errata build flags are defined : 206 207- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 208 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 209 210- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 211 revisions of Cortex-A72 CPU. 212 213For Cortex-A73, the following errata build flags are defined : 214 215- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 216 CPU. This needs to be enabled only for revision r0p0 of the CPU. 217 218- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 219 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 220 221For Cortex-A75, the following errata build flags are defined : 222 223- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 224 CPU. This needs to be enabled only for revision r0p0 of the CPU. 225 226- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 227 CPU. This needs to be enabled only for revision r0p0 of the CPU. 228 229For Cortex-A76, the following errata build flags are defined : 230 231- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 232 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 233 234- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 235 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 236 237- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 238 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 239 240- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 241 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 242 243- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 245 246- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 247 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 248 249- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 250 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 251 252- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 253 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 254 255- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 256 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 257 limitation of errata framework this errata is applied to all revisions 258 of Cortex-A76 CPU. 259 260- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 261 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 262 263- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 264 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 265 266- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 267 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 268 still open. 269 270For Cortex-A76AE, the following errata build flags are defined : 271 272- ``ERRATA_A76AE_1931427``: This applies errata 1931427 workaround to Cortex-A76AE 273 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 274 fixed in r1p1. 275 276- ``ERRATA_A76AE_1931435``: This applies errata 1931435 workaround to Cortex-A76AE 277 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 278 fixed in r1p1. 279 280- ``ERRATA_A76AE_1969401``: This applies errata 1969401 workaround to Cortex-A76AE 281 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 282 fixed in r1p1. 283 284- ``ERRATA_A76AE_2371140``: This applies errata 2371140 workaround to Cortex-A76AE 285 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 286 still open. 287 288For Cortex-A77, the following errata build flags are defined : 289 290- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 291 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 292 293- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 294 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 295 296- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 297 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 298 299- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 300 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 301 302- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 303 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 304 305 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 306 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 307 308 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 309 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 310 311For Cortex-A78, the following errata build flags are defined : 312 313- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 314 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 315 316- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 317 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 318 319- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 320 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 321 issue but there is no workaround for that revision. 322 323- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 324 CPU. This needs to be enabled for revisions r0p0 and r1p0. 325 326- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 327 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 328 329- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 330 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 331 is present in r0p0 but there is no workaround. It is still open. 332 333- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 334 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 335 it is still open. 336 337- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 338 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 339 it is still open. 340 341- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 342 CPU, this erratum affects system configurations that do not use an ARM 343 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 344 and r1p2 and it is still open. 345 346- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 347 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 348 it is still open. 349 350- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 351 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 352 it is still open. 353 354- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 355 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 356 it is still open. 357 358For Cortex-A78AE, the following errata build flags are defined : 359 360- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 361 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 362 This erratum is still open. 363 364- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 365 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 366 erratum is still open. 367 368- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 369 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 370 This erratum is still open. 371 372- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 373 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 374 erratum is still open. 375 376- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 377 Cortex-A78AE CPU. This erratum affects system configurations that do not use 378 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 379 r0p2. This erratum is still open. 380 381For Cortex-A78C, the following errata build flags are defined : 382 383- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 384 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 385 fixed in r0p1. 386 387- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 388 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 389 fixed in r0p1. 390 391- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 392 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 393 it is still open. 394 395- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 396 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 397 erratum is still open. 398 399- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 400 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 401 erratum is still open. 402 403- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 404 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 405 erratum is still open. 406 407- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 408 Cortex-A78C CPU, this erratum affects system configurations that do not use 409 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 410 and is still open. 411 412- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 413 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 414 This erratum is still open. 415 416- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 417 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 418 This erratum is still open. 419 420- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 421 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 422 This erratum is still open. 423 424For Cortex-X1 CPU, the following errata build flags are defined: 425 426- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 427 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 428 429- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 430 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 431 432- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 433 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 434 435For Neoverse N1, the following errata build flags are defined : 436 437- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 438 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 439 440- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 441 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 442 443- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 444 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 445 446- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 447 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 448 449- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 450 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 451 452- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 453 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 454 455- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 456 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 457 458- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 459 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 460 461- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 462 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 463 464- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 465 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 466 467- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 468 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 469 470- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 471 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 472 473- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 474 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 475 revisions r0p0, r1p0, and r2p0 there is no workaround. 476 477- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 478 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 479 still open. 480 481For Neoverse V1, the following errata build flags are defined : 482 483- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 484 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 485 r1p0. 486 487- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 488 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 489 in r1p1. 490 491- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 492 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 493 in r1p1. 494 495- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 496 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 497 in r1p1. 498 499- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 500 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 501 502- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 503 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 504 CPU. 505 506- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 507 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 508 issue is present in r0p0 as well but there is no workaround for that 509 revision. It is still open. 510 511- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 512 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 513 CPU. It is still open. 514 515- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 516 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 517 issue is present in r0p0 as well but there is no workaround for that 518 revision. It is still open. 519 520- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 521 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 522 the CPU. 523 524- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 525 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 526 It has been fixed in r1p2. 527 528- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 529 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 530 It is still open. 531 532- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 533 CPU, this erratum affects system configurations that do not use an ARM 534 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 535 It has been fixed in r1p2. 536 537- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 538 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 539 CPU. It is still open. 540 541- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 542 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 543 CPU. It is still open. 544 545- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 546 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 547 CPU. It is still open. 548 549For Neoverse V2, the following errata build flags are defined : 550 551- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 552 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 553 r0p2. 554 555- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 556 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 557 r0p2. 558 559- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 560 CPU, this affects system configurations that do not use and ARM interconnect 561 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 562 in r0p2. 563 564- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 565 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 566 r0p2. 567 568- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 569 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 570 r0p2. 571 572- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 573 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 574 r0p2. 575 576- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 577 CPU, this affects all configurations. This needs to be enabled for revisions 578 r0p0 and r0p1. It has been fixed in r0p2. 579 580- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 581 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 582 still open. 583 584- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 585 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 586 the CPU. It is fixed in r0p2. 587 588For Neoverse V3, the following errata build flags are defined : 589 590- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 591 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 592 593- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 594 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 595 is still open. 596 597For Cortex-A710, the following errata build flags are defined : 598 599- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 600 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 601 been fixed in r2p0. 602 603- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 604 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 605 It has been fixed in r2p0. 606 607- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 608 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 609 It has been fixed in r2p0. 610 611- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 612 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 613 It has been fixed in r2p0. 614 615- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 616 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 617 r2p0 of the CPU. It is still open. 618 619- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 620 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 621 r2p0 of the CPU. It is still open. 622 623- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 624 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 625 and is still open. 626 627- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 628 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 629 of the CPU and is still open. 630 631- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 632 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 633 is still open. 634 635- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 636 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 637 of the CPU and is fixed in r2p1. 638 639- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 640 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 641 of the CPU and is fixed in r2p1. 642 643- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 644 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 645 and is fixed in r2p1. 646 647- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 648 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 649 of the CPU and is fixed in r2p1. 650 651- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 652 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 653 r2p1 of the CPU and is still open. 654 655- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 656 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 657 of the CPU and is fixed in r2p1. 658 659- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 660 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 661 of the CPU and is fixed in r2p1. 662 663- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 664 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 665 of the CPU and is fixed in r2p1. 666 667- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 668 CPU, and applies to system configurations that do not use and ARM 669 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 670 is still open. 671 672- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 673 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 674 r2p1 of the CPU and is still open. 675 676- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 677 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 678 r2p1 of the CPU and is still open. 679 680- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 681 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 682 CPU and is still open. 683 684- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 685 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 686 CPU and is still open. 687 688For Neoverse N2, the following errata build flags are defined : 689 690- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 691 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 692 693- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 694 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 695 696- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 697 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 698 699- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 700 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 701 702- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 703 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 704 705- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 706 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 707 708- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 709 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 710 711- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 712 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 713 714- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 715 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 716 717- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 718 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 719 720- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 721 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 722 r0p1. 723 724- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 725 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 726 r0p1. 727 728- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 729 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 730 it is fixed in r0p3. 731 732- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 733 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 734 735- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 736 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 737 r0p1. 738 739- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 740 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 741 in r0p3. 742 743- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 744 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 745 in r0p3. 746 747- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 748 CPU, this erratum affects system configurations that do not use and ARM 749 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 750 It is fixed in r0p3. 751 752- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 753 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 754 in r0p3. 755 756- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 757 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 758 still open. 759 760For Neoverse N3, the following errata build flags are defined : 761 762- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 763 CPU. This needs to be enabled for revisions r0p0 and is still open. 764 765For Cortex-X2, the following errata build flags are defined : 766 767- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 768 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 769 770- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 771 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 772 is fixed in r2p0. 773 774- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 775 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 776 is fixed in r2p0. 777 778- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 779 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 780 is fixed in r2p0. 781 782- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 783 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 784 in r2p0. 785 786- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 787 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 788 CPU, it is fixed in r2p1. 789 790- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 791 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 792 CPU, it is fixed in r2p1. 793 794- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 795 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 796 CPU, it is fixed in r2p1. 797 798- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 799 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 800 in r2p1. 801 802- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 803 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 804 CPU, it is fixed in r2p1. 805 806- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 807 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 808 in r2p1. 809 810- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 811 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 812 CPU, it is fixed in r2p1. 813 814- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 815 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 816 CPU, it is fixed in r2p1. 817 818- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 819 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 820 CPU and is still open. 821 822- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 823 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 824 CPU, it is fixed in r2p1. 825 826- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 827 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 828 CPU, it is fixed in r2p1. 829 830- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 831 CPU and affects system configurations that do not use an Arm interconnect IP. 832 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 833 still open. 834 835- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 836 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 837 CPU and is still open. 838 839- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 840 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 841 CPU and is still open. 842 843- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 844 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 845 CPU and is still open. 846 847- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 848 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 849 CPU and is still open. 850 851For Cortex-X3, the following errata build flags are defined : 852 853- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 854 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 855 is fixed in r1p1. 856 857- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 858 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 859 fixed in r1p2. 860 861- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 862 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 863 of the CPU, it is fixed in r1p1. 864 865- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 866 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 867 of the CPU, it is fixed in r1p1. 868 869- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 870 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 871 CPU, it is fixed in r1p2. 872 873- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 874 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 875 It is fixed in r1p1. 876 877- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 878 CPU and affects system configurations that do not use an ARM interconnect 879 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 880 in r1p2. 881 882- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 883 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 884 r1p1. It is fixed in r1p2. 885 886- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 887 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 888 fixed in r1p2. 889 890- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 891 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 892 CPU. It is fixed in r1p2. 893 894- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 895 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 896 of the CPU. It is still open. 897 898- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 899 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 900 of the CPU. It is still open. 901 902- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 903 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 904 of the CPU and it is still open. 905 906- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 907 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 908 the CPU. It is fixed in r1p2. 909 910For Cortex-X4, the following errata build flags are defined : 911 912- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 913 CPU and affects system configurations that do not use an Arm interconnect IP. 914 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 915 The workaround for this erratum is not implemented in EL3, but the flag can 916 be enabled/disabled at the platform level. The flag is used when the errata ABI 917 feature is enabled and can assist the Kernel in the process of 918 mitigation of the erratum. 919 920- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 921 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 922 r0p2. 923 924- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 925 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 926 in r0p2. 927 928- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 929 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 930 931- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 932 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 933 934- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 935 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 936 937- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 938 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 939 940- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 941 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 942 943- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 944 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 945 946- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 947 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 948 949- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 950 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 951 It is still open. 952 953- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 954 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 955 It is still open. 956 957For Cortex-X925, the following errata build flags are defined : 958 959- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 960 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 961 962- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 963 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 964 965For Cortex-A510, the following errata build flags are defined : 966 967- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 968 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 969 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 970 971- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 972 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 973 r0p2, r0p3 and r1p0, it is fixed in r1p1. 974 975- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 976 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 977 r0p2, it is fixed in r0p3. 978 979- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 980 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 981 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 982 workaround for those revisions. 983 984- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 985 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 986 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 987 workaround for those revisions. 988 989- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 990 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 991 r0p2, r0p3 and r1p0, it is fixed in r1p1. 992 993- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 994 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 995 in r1p1. 996 997- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 998 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 999 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 1000 ENABLE_MPMM=1. 1001 1002- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 1003 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1004 r0p3 and r1p0, it is fixed in r1p1. 1005 1006- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 1007 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1008 r0p3 and r1p0, it is fixed in r1p1. 1009 1010- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 1011 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1012 r0p3, r1p0 and r1p1. It is fixed in r1p2. 1013 1014- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 1015 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1016 r0p3, r1p0, r1p1, and is fixed in r1p2. 1017 1018- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1019 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1020 fixed in r1p2. 1021 1022- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1023 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1024 r0p3, r1p0, r1p1. It is fixed in r1p2. 1025 1026- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1027 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1028 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1029 1030- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1031 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1032 r1p0, r1p1, r1p2 and r1p3 and is still open. 1033 1034- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1035 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1036 r1p0, r1p1, r1p2 and r1p3 and is still open. 1037 1038- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1039 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1040 r1p0, r1p1, r1p2 and r1p3 and is still open. 1041 1042For Cortex-A520, the following errata build flags are defined : 1043 1044- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1045 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1046 CPU and is still open. 1047 1048- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1049 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1050 It is still open. 1051 1052- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1053 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1054 It is fixed in r0p2. 1055 1056For Cortex-A715, the following errata build flags are defined : 1057 1058- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1059 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1060 It is fixed in r1p1. 1061 1062- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1063 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1064 fixed in r1p1. 1065 1066- ``ERRATA_A715_2376701``: This applies errata 2376701 workaround to 1067 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1068 fixed in r1p1. 1069 1070- ``ERRATA_A715_2409570``: This applies errata 2409570 workaround to 1071 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1072 It is fixed in r1p1. This errata also applies to r0p0 but that revision has a 1073 different workaround, and since r0p0 is not used in production hardware it is 1074 not implemented. 1075 1076- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1077 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1078 when SPE(Statistical profiling extension)=True. The errata is fixed 1079 in r1p1. 1080 1081- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1082 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1083 It is fixed in r1p1. 1084 1085- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1086 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1087 workaround for revision r0p0. It is fixed in r1p1. 1088 1089- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1090 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1091 It is fixed in r1p1. 1092 1093- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1094 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1095 and r1p1. It is fixed in r1p2. 1096 1097- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1098 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1099 r1p1 and r1p2. It is fixed in r1p3. 1100 1101- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1102 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1103 r1p2 and r1p3. It is still open. 1104 1105- ``ERRATA_A715_3711916``: This applies errata 3711916 workaround to 1106 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1107 r1p1, r1p2 and r1p3. It is still open. 1108 1109For Cortex-A720, the following errata build flags are defined : 1110 1111- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1112 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1113 It is fixed in r0p2. 1114 1115- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1116 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1117 It is fixed in r0p2. 1118 1119- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1120 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1121 It is fixed in r0p2. 1122 1123- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1124 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1125 It is fixed in r0p2. 1126 1127- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1128 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1129 It is fixed in r0p2. 1130 1131- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1132 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1133 and r0p2. It is still open. 1134 1135- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1136 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1137 and r0p2. It is still open. 1138 1139For Cortex-A720_AE, the following errata build flags are defined : 1140 1141- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1142 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1143 It is still open. 1144 1145For Cortex-A725, the following errata build flags are defined : 1146 1147- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1148 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1149 It is fixed in r0p2. 1150 1151DSU Errata Workarounds 1152---------------------- 1153 1154Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1155Shared Unit) errata. The DSU errata details can be found in the respective Arm 1156documentation: 1157 1158- `Arm DSU Software Developers Errata Notice`_. 1159 1160Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1161document. Thus, the build flags which enable/disable the errata workarounds 1162have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1163of DSU errata workarounds are similar to `CPU errata workarounds`_. 1164 1165For DSU errata, the following build flags are defined: 1166 1167- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1168 affected DSU configurations. This errata applies only for those DSUs that 1169 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1170 workaround results in increased DSU power consumption on idle. 1171 1172- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1173 affected DSU configurations. This errata applies only for those DSUs that 1174 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1175 r2p0 it is fixed). However, please note that this workaround results in 1176 increased DSU power consumption on idle. 1177 1178- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1179 affected DSU configurations. This errata applies for those DSUs with 1180 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1181 please note that this workaround results in increased DSU power consumption 1182 on idle. 1183 1184- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1185 affected DSU-120 configurations. This erratum applies to some r2p0 1186 implementations and is fixed in r2p1. The affected r2p0 implementations 1187 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1188 and making sure it's clear. 1189 1190CPU Specific optimizations 1191-------------------------- 1192 1193This section describes some of the optimizations allowed by the CPU micro 1194architecture that can be enabled by the platform as desired. 1195 1196- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1197 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1198 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1199 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1200 is a known safe deviation from the Cortex-A57 TRM defined power down 1201 sequence. Each Cortex-A57 based platform must make its own decision on 1202 whether to use the optimization. 1203 1204- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1205 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1206 in a way most programmers expect, and will most probably result in a 1207 significant speed degradation to any code that employs them. The Armv8-A 1208 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1209 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1210 flag enforces this behaviour. This needs to be enabled only for revisions 1211 <= r0p3 of the CPU and is enabled by default. 1212 1213- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1214 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1215 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1216 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1217 `Cortex-A57 Software Optimization Guide`_. 1218 1219- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1220 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1221 this bit only if their memory system meets the requirement that cache 1222 line fill requests from the Cortex-A57 processor are atomic. Each 1223 Cortex-A57 based platform must make its own decision on whether to use 1224 the optimization. This flag is disabled by default. 1225 1226- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1227 level cache(LLC) is present in the system, and that the DataSource field 1228 on the master CHI interface indicates when data is returned from the LLC. 1229 This is used to control how the LL_CACHE* PMU events count. 1230 Default value is 0 (Disabled). 1231 1232- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1233 on the Neoverse N2 core. This is used during performance analysis to get clean 1234 and repeatable measurements of the cache by preventing speculative data fetches 1235 from interfering with benchmark results. 1236 Default value is 0 (Disabled). 1237 1238GIC Errata Workarounds 1239---------------------- 1240- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1241 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1242 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1243 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1244 then this flag is enabled; otherwise, it is 0 (Disabled). 1245 1246-------------- 1247 1248*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1249 1250.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1251.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1252.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1253.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1254.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1255.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1256