Merge changes If9672598,I219c49d3 into integration

* changes:
feat(cert-create): add pkcs11 engine support
fix(cert-create): key: Avoid having a temporary value for pkey in key_load

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround for Neoverse V2 erratum 2719105
fix(cpus): workaround for Neoverse V2 erratum 2331132

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feat(cert-create): add pkcs11 engine support

Add pkcs11 engine support which allows using keys that are securely
stored on a HSM or TPM. To use this feature the user has to supply
an RFC 7512 compli

feat(cert-create): add pkcs11 engine support

Add pkcs11 engine support which allows using keys that are securely
stored on a HSM or TPM. To use this feature the user has to supply
an RFC 7512 compliant PKCS11 URI to a key instead of a file as an
argument to one of the key options. This change is fully backwards
compatible.

This change makes use of the openssl engine API which is deprecated
since openssl 3.0 and will most likely be removed in version 4. So
pkcs11 support will have to be updated to the openssl provider API
in the near future.

Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Change-Id: If96725988ca62c5613ec59123943bf15922f5d1f

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fix(cpus): workaround for Neoverse V2 erratum 2743011

Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL

fix(cpus): workaround for Neoverse V2 erratum 2743011

Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64

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fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of C

fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80

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fix(cpus): workaround for Neoverse V2 erratum 2719105

Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CP

fix(cpus): workaround for Neoverse V2 erratum 2719105

Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba

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fix(cpus): workaround for Neoverse V2 erratum 2331132

Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b

fix(cpus): workaround for Neoverse V2 erratum 2331132

Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1

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Merge changes from topic "sm/errata_X3" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 2742421
feat(errata_abi): add support for Cortex-X3

fix(cpus): workaround for Cortex-X3 erratum 2742421

Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56

fix(cpus): workaround for Cortex-X3 erratum 2742421

Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b

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Merge "fix(cpus): workaround for Neoverse N2 erratum 2009478" into integration

fix(cpus): workaround for Neoverse N2 erratum 2009478

Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all

fix(cpus): workaround for Neoverse N2 erratum 2009478

Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all core error records before setting the PWRDN_EN
bit in CPUPWRCTLR_EL1 to request a power down.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51

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refactor(cpus): reorder Cortex-A53 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition

refactor(cpus): reorder Cortex-A53 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.

Also rename the disable_non_temporal_hint to its erratum number to
conform to convention.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id474872afebf361ab3d21c454ab3624db8354045

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fix(cpus): workaround for Neoverse N2 erratum 2779511

Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CP

fix(cpus): workaround for Neoverse N2 erratum 2779511

Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3

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fix(cpus): workaround for Neoverse N2 erratum 2743014

Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1

fix(cpus): workaround for Neoverse N2 erratum 2743014

Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192

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fix(docs): updated certain Neoverse N2 erratum status in docs

Certain Neoverse N2 erratum in docs were out of date with the latest
SDEN document and hence updated it to match the latest

SDEN docume

fix(docs): updated certain Neoverse N2 erratum status in docs

Certain Neoverse N2 erratum in docs were out of date with the latest
SDEN document and hence updated it to match the latest

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5d82a56388a46a09a42b940a633ecebdde0c74e3

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Merge "chore(docs): update march utility details" into integration

fix(cpus): workaround for Neoverse V2 erratum 2801372

Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb befo

fix(cpus): workaround for Neoverse V2 erratum 2801372

Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.

This errata is explained in SDEN 2332927 available at:
https://developer.arm.com/documentation/SDEN2332927

Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff
Signed-off-by: Moritz Fischer <moritzf@google.com>

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chore(docs): update march utility details

commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.

Update docs to provide a glimpse of march u

chore(docs): update march utility details

commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.

Update docs to provide a glimpse of march utility added.

Change-Id: I696cb9a701a30d7bf36a1ecd38a80d07df1fd551
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives

refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives to a common one as march-directive.

Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "docs: update PSCI reference" into integration

Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): add more errata framework helpers
docs: document the errata framework

docs: document the errata framework

Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan

docs: document the errata framework

Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idd876d8e598b5dfe1193aa3e7375c52f6edf5671

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docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017a

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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chore(bl): add UNALIGNED symbols for TEXT/RODATA

Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the l

chore(bl): add UNALIGNED symbols for TEXT/RODATA

Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the linker scripts") for
RO_END/COHERENT_RAM. These symbols help to know how much free
space is in the final binary because of page alignment.

Also show all *UNALIGNED__ symbols via poetry.
For example:
poetry run memory -p zynqmp -b debug

Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control regist

Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control register setup section
chore(pauth): remove redundant pauth_disable_el3() call

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