1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <platform_def.h> 31 #include <plat_imx8.h> 32 33 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 34 35 static const mmap_region_t imx_mmap[] = { 36 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 37 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, 38 ROM_MAP, DRAM_MAP, 39 {0}, 40 }; 41 42 static const struct aipstz_cfg aipstz[] = { 43 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 44 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {0}, 48 }; 49 50 static const struct imx_rdc_cfg rdc[] = { 51 /* Master domain assignment */ 52 RDC_MDAn(RDC_MDA_M7, DID1), 53 54 /* peripherals domain permission */ 55 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 56 57 /* memory region */ 58 59 /* Sentinel */ 60 {0}, 61 }; 62 63 static const struct imx_csu_cfg csu_cfg[] = { 64 /* peripherals csl setting */ 65 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 66 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 67 68 /* master HP0~1 */ 69 70 /* SA setting */ 71 72 /* HP control setting */ 73 74 /* Sentinel */ 75 {0} 76 }; 77 78 static entry_point_info_t bl32_image_ep_info; 79 static entry_point_info_t bl33_image_ep_info; 80 81 /* get SPSR for BL33 entry */ 82 static uint32_t get_spsr_for_bl33_entry(void) 83 { 84 unsigned long el_status; 85 unsigned long mode; 86 uint32_t spsr; 87 88 /* figure out what mode we enter the non-secure world */ 89 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 90 el_status &= ID_AA64PFR0_ELX_MASK; 91 92 mode = (el_status) ? MODE_EL2 : MODE_EL1; 93 94 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 95 return spsr; 96 } 97 98 static void bl31_tzc380_setup(void) 99 { 100 unsigned int val; 101 102 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 103 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 104 return; 105 106 tzc380_init(IMX_TZASC_BASE); 107 108 /* 109 * Need to substact offset 0x40000000 from CPU address when 110 * programming tzasc region for i.mx8mp. 111 */ 112 113 /* Enable 1G-5G S/NS RW */ 114 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 115 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 116 } 117 118 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 119 u_register_t arg2, u_register_t arg3) 120 { 121 unsigned int console_base = 0U; 122 static console_t console; 123 unsigned int val; 124 unsigned int i; 125 126 /* Enable CSU NS access permission */ 127 for (i = 0; i < 64; i++) { 128 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 129 } 130 131 imx_aipstz_init(aipstz); 132 133 imx_rdc_init(rdc); 134 135 imx_csu_init(csu_cfg); 136 137 /* config the ocram memory range for secure access */ 138 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 139 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 140 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 141 142 #if IMX_BOOT_UART_BASE 143 console_base = IMX_BOOT_UART_BASE; 144 #endif 145 if (console_base == 0U) { 146 console_base = imx8m_uart_get_base(); 147 } 148 149 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 150 IMX_CONSOLE_BAUDRATE, &console); 151 /* This console is only used for boot stage */ 152 console_set_scope(&console, CONSOLE_FLAG_BOOT); 153 154 imx8m_caam_init(); 155 156 /* 157 * tell BL3-1 where the non-secure software image is located 158 * and the entry state information. 159 */ 160 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 161 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 162 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 163 164 #if defined(SPD_opteed) || defined(SPD_trusty) 165 /* Populate entry point information for BL32 */ 166 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 167 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 168 bl32_image_ep_info.pc = BL32_BASE; 169 bl32_image_ep_info.spsr = 0; 170 171 /* Pass TEE base and size to bl33 */ 172 bl33_image_ep_info.args.arg1 = BL32_BASE; 173 bl33_image_ep_info.args.arg2 = BL32_SIZE; 174 175 #ifdef SPD_trusty 176 bl32_image_ep_info.args.arg0 = BL32_SIZE; 177 bl32_image_ep_info.args.arg1 = BL32_BASE; 178 #else 179 /* Make sure memory is clean */ 180 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 181 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 182 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 183 #endif 184 #endif 185 186 bl31_tzc380_setup(); 187 } 188 189 #define MAP_BL31_TOTAL \ 190 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 191 #define MAP_BL31_RO \ 192 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 193 #define MAP_COHERENT_MEM \ 194 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 195 MT_DEVICE | MT_RW | MT_SECURE) 196 #define MAP_BL32_TOTAL \ 197 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 198 199 void bl31_plat_arch_setup(void) 200 { 201 const mmap_region_t bl_regions[] = { 202 MAP_BL31_TOTAL, 203 MAP_BL31_RO, 204 #if USE_COHERENT_MEM 205 MAP_COHERENT_MEM, 206 #endif 207 /* Map TEE memory */ 208 MAP_BL32_TOTAL, 209 {0} 210 }; 211 212 setup_page_tables(bl_regions, imx_mmap); 213 enable_mmu_el3(0); 214 } 215 216 void bl31_platform_setup(void) 217 { 218 generic_delay_timer_init(); 219 220 /* select the CKIL source to 32K OSC */ 221 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 222 223 /* Init the dram info */ 224 dram_info_init(SAVED_DRAM_TIMING_BASE); 225 226 plat_gic_driver_init(); 227 plat_gic_init(); 228 229 imx_gpc_init(); 230 } 231 232 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 233 { 234 if (type == NON_SECURE) { 235 return &bl33_image_ep_info; 236 } 237 238 if (type == SECURE) { 239 return &bl32_image_ep_info; 240 } 241 242 return NULL; 243 } 244 245 unsigned int plat_get_syscnt_freq2(void) 246 { 247 return COUNTER_FREQUENCY; 248 } 249 250 #ifdef SPD_trusty 251 void plat_trusty_set_boot_args(aapcs64_params_t *args) 252 { 253 args->arg0 = BL32_SIZE; 254 args->arg1 = BL32_BASE; 255 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 256 } 257 #endif 258