1/* 2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* 28 * ERRATA_DSU_2313941: 29 * The errata is defined in dsu_helpers.S and applies to Neoverse N2. 30 * Henceforth creating symbolic names to the already existing errata 31 * workaround functions to get them registered under the Errata Framework. 32 */ 33.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 34.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa 35add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 36 37workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 38 /* Apply instruction patching sequence */ 39 ldr x0,=0x6 40 msr S3_6_c15_c8_0,x0 41 ldr x0,=0xF3A08002 42 msr S3_6_c15_c8_2,x0 43 ldr x0,=0xFFF0F7FE 44 msr S3_6_c15_c8_3,x0 45 ldr x0,=0x40000001003ff 46 msr S3_6_c15_c8_1,x0 47 ldr x0,=0x7 48 msr S3_6_c15_c8_0,x0 49 ldr x0,=0xBF200000 50 msr S3_6_c15_c8_2,x0 51 ldr x0,=0xFFEF0000 52 msr S3_6_c15_c8_3,x0 53 ldr x0,=0x40000001003f3 54 msr S3_6_c15_c8_1,x0 55workaround_reset_end neoverse_n2, ERRATUM(2002655) 56 57check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 58 59workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 60 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 61workaround_reset_end neoverse_n2, ERRATUM(2025414) 62 63check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 64 65workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 66 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 67workaround_reset_end neoverse_n2, ERRATUM(2067956) 68 69check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 70 71workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 72 /* Apply instruction patching sequence */ 73 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 74 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 75 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 76 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 77workaround_reset_end neoverse_n2, ERRATUM(2138953) 78 79check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 80 81workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 82 /* Apply instruction patching sequence */ 83 ldr x0,=0x3 84 msr S3_6_c15_c8_0,x0 85 ldr x0,=0xF3A08002 86 msr S3_6_c15_c8_2,x0 87 ldr x0,=0xFFF0F7FE 88 msr S3_6_c15_c8_3,x0 89 ldr x0,=0x10002001003FF 90 msr S3_6_c15_c8_1,x0 91 ldr x0,=0x4 92 msr S3_6_c15_c8_0,x0 93 ldr x0,=0xBF200000 94 msr S3_6_c15_c8_2,x0 95 ldr x0,=0xFFEF0000 96 msr S3_6_c15_c8_3,x0 97 ldr x0,=0x10002001003F3 98 msr S3_6_c15_c8_1,x0 99workaround_reset_end neoverse_n2, ERRATUM(2138956) 100 101check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 102 103 104workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 105 /* Apply instruction patching sequence */ 106 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 107workaround_reset_end neoverse_n2, ERRATUM(2138958) 108 109check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 110 111workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 112 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 113workaround_reset_end neoverse_n2, ERRATUM(2189731) 114 115check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 116 117workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 118 /* Apply instruction patching sequence */ 119 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 120 ldr x0, =0x2 121 msr S3_6_c15_c8_0, x0 122 ldr x0, =0x10F600E000 123 msr S3_6_c15_c8_2, x0 124 ldr x0, =0x10FF80E000 125 msr S3_6_c15_c8_3, x0 126 ldr x0, =0x80000000003FF 127 msr S3_6_c15_c8_1, x0 128workaround_reset_end neoverse_n2, ERRATUM(2242400) 129 130check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 131 132workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 133 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 134workaround_reset_end neoverse_n2, ERRATUM(2242415) 135 136check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 137 138workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 139 /* Apply instruction patching sequence */ 140 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 141workaround_reset_end neoverse_n2, ERRATUM(2280757) 142 143check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 144 145workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 146 /* Set bit 36 in ACTLR2_EL1 */ 147 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 148workaround_runtime_end neoverse_n2, ERRATUM(2326639) 149 150check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 151 152workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 153 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 154 * ST to behave like PLD/PFRM LD and not cause 155 * invalidations to other PE caches. 156 */ 157 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 158workaround_reset_end neoverse_n2, ERRATUM(2376738) 159 160check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 161 162workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 163 /*Set bit 40 in ACTLR2_EL1 */ 164 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 165workaround_reset_end neoverse_n2, ERRATUM(2388450) 166 167check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 168 169workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 170 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 171 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 172 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 173workaround_reset_end neoverse_n2, ERRATUM(2743014) 174 175check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 176 177workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 178 /* dsb before isb of power down sequence */ 179 dsb sy 180workaround_runtime_end neoverse_n2, ERRATUM(2743089) 181 182check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 183 184workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 185#if IMAGE_BL31 186 /* 187 * The Neoverse-N2 generic vectors are overridden to apply errata 188 * mitigation on exception entry from lower ELs. 189 */ 190 override_vector_table wa_cve_vbar_neoverse_n2 191#endif /* IMAGE_BL31 */ 192workaround_reset_end neoverse_n2, CVE(2022,23960) 193 194check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 195 196 /* ------------------------------------------- 197 * The CPU Ops reset function for Neoverse N2. 198 * ------------------------------------------- 199 */ 200cpu_reset_func_start neoverse_n2 201 202 /* Check if the PE implements SSBS */ 203 mrs x0, id_aa64pfr1_el1 204 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 205 b.eq 1f 206 207 /* Disable speculative loads */ 208 msr SSBS, xzr 2091: 210 /* Force all cacheable atomic instructions to be near */ 211 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 212 213#if ENABLE_FEAT_AMU 214 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 215 sysreg_bit_set cptr_el3, TAM_BIT 216 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 217 sysreg_bit_set cptr_el2, TAM_BIT 218 /* No need to enable the counters as this would be done at el3 exit */ 219#endif 220 221#if NEOVERSE_Nx_EXTERNAL_LLC 222 /* Some systems may have External LLC, core needs to be made aware */ 223 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 224#endif 225cpu_reset_func_end neoverse_n2 226 227func neoverse_n2_core_pwr_dwn 228 229 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 230 /* --------------------------------------------------- 231 * Enable CPU power down bit in power control register 232 * No need to do cache maintenance here. 233 * --------------------------------------------------- 234 */ 235 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 236 237 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 238 239 isb 240 ret 241endfunc neoverse_n2_core_pwr_dwn 242 243errata_report_shim neoverse_n2 244 245 /* --------------------------------------------- 246 * This function provides Neoverse N2 specific 247 * register information for crash reporting. 248 * It needs to return with x6 pointing to 249 * a list of register names in ASCII and 250 * x8 - x15 having values of registers to be 251 * reported. 252 * --------------------------------------------- 253 */ 254.section .rodata.neoverse_n2_regs, "aS" 255neoverse_n2_regs: /* The ASCII list of register names to be reported */ 256 .asciz "cpupwrctlr_el1", "" 257 258func neoverse_n2_cpu_reg_dump 259 adr x6, neoverse_n2_regs 260 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 261 ret 262endfunc neoverse_n2_cpu_reg_dump 263 264declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 265 neoverse_n2_reset_func, \ 266 neoverse_n2_core_pwr_dwn 267