1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `Power State Coordination Interface PDD`_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention (`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the `Arm Confidential Compute 32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management 33 Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 134 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 135 from FW_CONFIG device tree. 136 137BL1 138~~~ 139 140This stage begins execution from the platform's reset vector at EL3. The reset 141address is platform dependent but it is usually located in a Trusted ROM area. 142The BL1 data section is copied to trusted SRAM at runtime. 143 144On the Arm development platforms, BL1 code starts execution from the reset 145vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 146to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 147 148The functionality implemented by this stage is as follows. 149 150Determination of boot path 151^^^^^^^^^^^^^^^^^^^^^^^^^^ 152 153Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 154boot and a cold boot. This is done using platform-specific mechanisms (see the 155``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 156of a warm boot, a CPU is expected to continue execution from a separate 157entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 158platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 159the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 160path as described in the following sections. 161 162This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 163:ref:`CPU Reset` for more information on the effect of the 164``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 165 166Architectural initialization 167^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 168 169BL1 performs minimal architectural initialization as follows. 170 171- Exception vectors 172 173 BL1 sets up simple exception vectors for both synchronous and asynchronous 174 exceptions. The default behavior upon receiving an exception is to populate 175 a status code in the general purpose register ``X0/R0`` and call the 176 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 177 status code is one of: 178 179 For AArch64: 180 181 :: 182 183 0x0 : Synchronous exception from Current EL with SP_EL0 184 0x1 : IRQ exception from Current EL with SP_EL0 185 0x2 : FIQ exception from Current EL with SP_EL0 186 0x3 : System Error exception from Current EL with SP_EL0 187 0x4 : Synchronous exception from Current EL with SP_ELx 188 0x5 : IRQ exception from Current EL with SP_ELx 189 0x6 : FIQ exception from Current EL with SP_ELx 190 0x7 : System Error exception from Current EL with SP_ELx 191 0x8 : Synchronous exception from Lower EL using aarch64 192 0x9 : IRQ exception from Lower EL using aarch64 193 0xa : FIQ exception from Lower EL using aarch64 194 0xb : System Error exception from Lower EL using aarch64 195 0xc : Synchronous exception from Lower EL using aarch32 196 0xd : IRQ exception from Lower EL using aarch32 197 0xe : FIQ exception from Lower EL using aarch32 198 0xf : System Error exception from Lower EL using aarch32 199 200 For AArch32: 201 202 :: 203 204 0x10 : User mode 205 0x11 : FIQ mode 206 0x12 : IRQ mode 207 0x13 : SVC mode 208 0x16 : Monitor mode 209 0x17 : Abort mode 210 0x1a : Hypervisor mode 211 0x1b : Undefined mode 212 0x1f : System mode 213 214 The ``plat_report_exception()`` implementation on the Arm FVP port programs 215 the Versatile Express System LED register in the following format to 216 indicate the occurrence of an unexpected exception: 217 218 :: 219 220 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 221 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 222 For AArch32 it is always 0x0 223 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 224 of the status code 225 226 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 227 CLCD window of the FVP. 228 229 BL1 does not expect to receive any exceptions other than the SMC exception. 230 For the latter, BL1 installs a simple stub. The stub expects to receive a 231 limited set of SMC types (determined by their function IDs in the general 232 purpose register ``X0/R0``): 233 234 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 235 to EL3 Runtime Software. 236 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 237 Design Guide are supported for AArch64 only. These SMCs are currently 238 not supported when BL1 is built for AArch32. 239 240 Any other SMC leads to an assertion failure. 241 242- CPU initialization 243 244 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 245 specific reset handler function (see the section: "CPU specific operations 246 framework"). 247 248Platform initialization 249^^^^^^^^^^^^^^^^^^^^^^^ 250 251On Arm platforms, BL1 performs the following platform initializations: 252 253- Enable the Trusted Watchdog. 254- Initialize the console. 255- Configure the Interconnect to enable hardware coherency. 256- Enable the MMU and map the memory it needs to access. 257- Configure any required platform storage to load the next bootloader image 258 (BL2). 259- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 260 load it to the platform defined address and make it available to BL2 via 261 ``arg0``. 262- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 263 and NS-BL2U firmware update images. 264 265Firmware Update detection and execution 266^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 267 268After performing platform setup, BL1 common code calls 269``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 270required or to proceed with the normal boot process. If the platform code 271returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 272in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 273required and execution passes to the first image in the 274:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 275of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 276contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 277execution state of the next image. 278 279BL2 image load and execution 280^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 281 282In the normal boot flow, BL1 execution continues as follows: 283 284#. BL1 prints the following string from the primary CPU to indicate successful 285 execution of the BL1 stage: 286 287 :: 288 289 "Booting Trusted Firmware" 290 291#. BL1 loads a BL2 raw binary image from platform storage, at a 292 platform-specific base address. Prior to the load, BL1 invokes 293 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 294 use the image information. If the BL2 image file is not present or if 295 there is not enough free trusted SRAM the following error message is 296 printed: 297 298 :: 299 300 "Failed to load BL2 firmware." 301 302#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 303 for platforms to take further action after image load. This function must 304 populate the necessary arguments for BL2, which may also include the memory 305 layout. Further description of the memory layout can be found later 306 in this document. 307 308#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 309 Secure SVC mode (for AArch32), starting from its load address. 310 311BL2 312~~~ 313 314BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 315SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 316base address (more information can be found later in this document). 317The functionality implemented by BL2 is as follows. 318 319Architectural initialization 320^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 321 322For AArch64, BL2 performs the minimal architectural initialization required 323for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 324access to Floating Point and Advanced SIMD registers by setting the 325``CPACR.FPEN`` bits. 326 327For AArch32, the minimal architectural initialization required for subsequent 328stages of TF-A and normal world software is taken care of in BL1 as both BL1 329and BL2 execute at PL1. 330 331Platform initialization 332^^^^^^^^^^^^^^^^^^^^^^^ 333 334On Arm platforms, BL2 performs the following platform initializations: 335 336- Initialize the console. 337- Configure any required platform storage to allow loading further bootloader 338 images. 339- Enable the MMU and map the memory it needs to access. 340- Perform platform security setup to allow access to controlled components. 341- Reserve some memory for passing information to the next bootloader image 342 EL3 Runtime Software and populate it. 343- Define the extents of memory available for loading each subsequent 344 bootloader image. 345- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 346 then parse it. 347 348Image loading in BL2 349^^^^^^^^^^^^^^^^^^^^ 350 351BL2 generic code loads the images based on the list of loadable images 352provided by the platform. BL2 passes the list of executable images 353provided by the platform to the next handover BL image. 354 355The list of loadable images provided by the platform may also contain 356dynamic configuration files. The files are loaded and can be parsed as 357needed in the ``bl2_plat_handle_post_image_load()`` function. These 358configuration files can be passed to next Boot Loader stages as arguments 359by updating the corresponding entrypoint information in this function. 360 361SCP_BL2 (System Control Processor Firmware) image load 362^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 363 364Some systems have a separate System Control Processor (SCP) for power, clock, 365reset and system control. BL2 loads the optional SCP_BL2 image from platform 366storage into a platform-specific region of secure memory. The subsequent 367handling of SCP_BL2 is platform specific. For example, on the Juno Arm 368development platform port the image is transferred into SCP's internal memory 369using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 370memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 371for BL2 execution to continue. 372 373EL3 Runtime Software image load 374^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 375 376BL2 loads the EL3 Runtime Software image from platform storage into a platform- 377specific address in trusted SRAM. If there is not enough memory to load the 378image or image is missing it leads to an assertion failure. 379 380AArch64 BL32 (Secure-EL1 Payload) image load 381^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 382 383BL2 loads the optional BL32 image from platform storage into a platform- 384specific region of secure memory. The image executes in the secure world. BL2 385relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 386populates a platform-specific area of memory with the entrypoint/load-address 387of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 388for entry into BL32 is not determined by BL2, it is initialized by the 389Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 390managing interaction with BL32. This information is passed to BL31. 391 392BL33 (Non-trusted Firmware) image load 393^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 394 395BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 396platform storage into non-secure memory as defined by the platform. 397 398BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 399initialization is complete. Hence, BL2 populates a platform-specific area of 400memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 401normal world software image. The entrypoint is the load address of the BL33 402image. The ``SPSR`` is determined as specified in Section 5.13 of the 403`Power State Coordination Interface PDD`_. This information is passed to the 404EL3 Runtime Software. 405 406AArch64 BL31 (EL3 Runtime Software) execution 407^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 408 409BL2 execution continues as follows: 410 411#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 412 BL31 entrypoint. The exception is handled by the SMC exception handler 413 installed by BL1. 414 415#. BL1 turns off the MMU and flushes the caches. It clears the 416 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 417 and invalidates the TLBs. 418 419#. BL1 passes control to BL31 at the specified entrypoint at EL3. 420 421Running BL2 at EL3 execution level 422~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 423 424Some platforms have a non-TF-A Boot ROM that expects the next boot stage 425to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 426as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 427this waste, a special mode enables BL2 to execute at EL3, which allows 428a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 429when the build flag RESET_TO_BL2 is enabled. 430The main differences in this mode are: 431 432#. BL2 includes the reset code and the mailbox mechanism to differentiate 433 cold boot and warm boot. It runs at EL3 doing the arch 434 initialization required for EL3. 435 436#. BL2 does not receive the meminfo information from BL1 anymore. This 437 information can be passed by the Boot ROM or be internal to the 438 BL2 image. 439 440#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 441 instead of invoking the RUN_IMAGE SMC call. 442 443 444We assume 3 different types of BootROM support on the platform: 445 446#. The Boot ROM always jumps to the same address, for both cold 447 and warm boot. In this case, we will need to keep a resident part 448 of BL2 whose memory cannot be reclaimed by any other image. The 449 linker script defines the symbols __TEXT_RESIDENT_START__ and 450 __TEXT_RESIDENT_END__ that allows the platform to configure 451 correctly the memory map. 452#. The platform has some mechanism to indicate the jump address to the 453 Boot ROM. Platform code can then program the jump address with 454 psci_warmboot_entrypoint during cold boot. 455#. The platform has some mechanism to program the reset address using 456 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 457 program the reset address with psci_warmboot_entrypoint during 458 cold boot, bypassing the boot ROM for warm boot. 459 460In the last 2 cases, no part of BL2 needs to remain resident at 461runtime. In the first 2 cases, we expect the Boot ROM to be able to 462differentiate between warm and cold boot, to avoid loading BL2 again 463during warm boot. 464 465This functionality can be tested with FVP loading the image directly 466in memory and changing the address where the system jumps at reset. 467For example: 468 469 -C cluster0.cpu0.RVBAR=0x4022000 470 --data cluster0.cpu0=bl2.bin@0x4022000 471 472With this configuration, FVP is like a platform of the first case, 473where the Boot ROM jumps always to the same address. For simplification, 474BL32 is loaded in DRAM in this case, to avoid other images reclaiming 475BL2 memory. 476 477 478AArch64 BL31 479~~~~~~~~~~~~ 480 481The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 482EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 483loaded at a platform-specific base address (more information can be found later 484in this document). The functionality implemented by BL31 is as follows. 485 486Architectural initialization 487^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 488 489Currently, BL31 performs a similar architectural initialization to BL1 as 490far as system register settings are concerned. Since BL1 code resides in ROM, 491architectural initialization in BL31 allows override of any previous 492initialization done by BL1. 493 494BL31 initializes the per-CPU data framework, which provides a cache of 495frequently accessed per-CPU data optimised for fast, concurrent manipulation 496on different CPUs. This buffer includes pointers to per-CPU contexts, crash 497buffer, CPU reset and power down operations, PSCI data, platform data and so on. 498 499It then replaces the exception vectors populated by BL1 with its own. BL31 500exception vectors implement more elaborate support for handling SMCs since this 501is the only mechanism to access the runtime services implemented by BL31 (PSCI 502for example). BL31 checks each SMC for validity as specified by the 503`SMC Calling Convention`_ before passing control to the required SMC 504handler routine. 505 506BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 507counter, which is provided by the platform. 508 509Platform initialization 510^^^^^^^^^^^^^^^^^^^^^^^ 511 512BL31 performs detailed platform initialization, which enables normal world 513software to function correctly. 514 515On Arm platforms, this consists of the following: 516 517- Initialize the console. 518- Configure the Interconnect to enable hardware coherency. 519- Enable the MMU and map the memory it needs to access. 520- Initialize the generic interrupt controller. 521- Initialize the power controller device. 522- Detect the system topology. 523 524Runtime services initialization 525^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 526 527BL31 is responsible for initializing the runtime services. One of them is PSCI. 528 529As part of the PSCI initializations, BL31 detects the system topology. It also 530initializes the data structures that implement the state machine used to track 531the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 532``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 533that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 534initializes the locks that protect them. BL31 accesses the state of a CPU or 535cluster immediately after reset and before the data cache is enabled in the 536warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 537therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 538 539The runtime service framework and its initialization is described in more 540detail in the "EL3 runtime services framework" section below. 541 542Details about the status of the PSCI implementation are provided in the 543"Power State Coordination Interface" section below. 544 545AArch64 BL32 (Secure-EL1 Payload) image initialization 546^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 547 548If a BL32 image is present then there must be a matching Secure-EL1 Payload 549Dispatcher (SPD) service (see later for details). During initialization 550that service must register a function to carry out initialization of BL32 551once the runtime services are fully initialized. BL31 invokes such a 552registered function to initialize BL32 before running BL33. This initialization 553is not necessary for AArch32 SPs. 554 555Details on BL32 initialization and the SPD's role are described in the 556:ref:`firmware_design_sel1_spd` section below. 557 558BL33 (Non-trusted Firmware) execution 559^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 560 561EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 562world cold boot, ensuring that no secure state information finds its way into 563the non-secure execution state. EL3 Runtime Software uses the entrypoint 564information provided by BL2 to jump to the Non-trusted firmware image (BL33) 565at the highest available Exception Level (EL2 if available, otherwise EL1). 566 567Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 569 570Some platforms have existing implementations of Trusted Boot Firmware that 571would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 572firmware architecture it is important to provide a fully documented and stable 573interface between the Trusted Boot Firmware and BL31. 574 575Future changes to the BL31 interface will be done in a backwards compatible 576way, and this enables these firmware components to be independently enhanced/ 577updated to develop and exploit new functionality. 578 579Required CPU state when calling ``bl31_entrypoint()`` during cold boot 580^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 581 582This function must only be called by the primary CPU. 583 584On entry to this function the calling primary CPU must be executing in AArch64 585EL3, little-endian data access, and all interrupt sources masked: 586 587:: 588 589 PSTATE.EL = 3 590 PSTATE.RW = 1 591 PSTATE.DAIF = 0xf 592 SCTLR_EL3.EE = 0 593 594X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 595platform code in BL31: 596 597:: 598 599 X0 : Reserved for common TF-A information 600 X1 : Platform specific information 601 602BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 603these will be zero filled prior to invoking platform setup code. 604 605Use of the X0 and X1 parameters 606''''''''''''''''''''''''''''''' 607 608The parameters are platform specific and passed from ``bl31_entrypoint()`` to 609``bl31_early_platform_setup()``. The value of these parameters is never directly 610used by the common BL31 code. 611 612The convention is that ``X0`` conveys information regarding the BL31, BL32 and 613BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 614platform specific purpose. This convention allows platforms which use TF-A's 615BL1 and BL2 images to transfer additional platform specific information from 616Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 617pass a ``bl31_params`` structure. 618 619BL31 common and SPD initialization code depends on image and entrypoint 620information about BL33 and BL32, which is provided via BL31 platform APIs. 621This information is required until the start of execution of BL33. This 622information can be provided in a platform defined manner, e.g. compiled into 623the platform code in BL31, or provided in a platform defined memory location 624by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 625Cold boot Initialization parameters. This data may need to be cleaned out of 626the CPU caches if it is provided by an earlier boot stage and then accessed by 627BL31 platform code before the caches are enabled. 628 629TF-A's BL2 implementation passes a ``bl31_params`` structure in 630``X0`` and the Arm development platforms interpret this in the BL31 platform 631code. 632 633MMU, Data caches & Coherency 634'''''''''''''''''''''''''''' 635 636BL31 does not depend on the enabled state of the MMU, data caches or 637interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 638on entry, these should be enabled during ``bl31_plat_arch_setup()``. 639 640Data structures used in the BL31 cold boot interface 641'''''''''''''''''''''''''''''''''''''''''''''''''''' 642 643These structures are designed to support compatibility and independent 644evolution of the structures and the firmware images. For example, a version of 645BL31 that can interpret the BL3x image information from different versions of 646BL2, a platform that uses an extended entry_point_info structure to convey 647additional register information to BL31, or a ELF image loader that can convey 648more details about the firmware images. 649 650To support these scenarios the structures are versioned and sized, which enables 651BL31 to detect which information is present and respond appropriately. The 652``param_header`` is defined to capture this information: 653 654.. code:: c 655 656 typedef struct param_header { 657 uint8_t type; /* type of the structure */ 658 uint8_t version; /* version of this structure */ 659 uint16_t size; /* size of this structure in bytes */ 660 uint32_t attr; /* attributes: unused bits SBZ */ 661 } param_header_t; 662 663The structures using this format are ``entry_point_info``, ``image_info`` and 664``bl31_params``. The code that allocates and populates these structures must set 665the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 666to simplify this action. 667 668Required CPU state for BL31 Warm boot initialization 669^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 670 671When requesting a CPU power-on, or suspending a running CPU, TF-A provides 672the platform power management code with a Warm boot initialization 673entry-point, to be invoked by the CPU immediately after the reset handler. 674On entry to the Warm boot initialization function the calling CPU must be in 675AArch64 EL3, little-endian data access and all interrupt sources masked: 676 677:: 678 679 PSTATE.EL = 3 680 PSTATE.RW = 1 681 PSTATE.DAIF = 0xf 682 SCTLR_EL3.EE = 0 683 684The PSCI implementation will initialize the processor state and ensure that the 685platform power management code is then invoked as required to initialize all 686necessary system, cluster and CPU resources. 687 688AArch32 EL3 Runtime Software entrypoint interface 689~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 690 691To enable this firmware architecture it is important to provide a fully 692documented and stable interface between the Trusted Boot Firmware and the 693AArch32 EL3 Runtime Software. 694 695Future changes to the entrypoint interface will be done in a backwards 696compatible way, and this enables these firmware components to be independently 697enhanced/updated to develop and exploit new functionality. 698 699Required CPU state when entering during cold boot 700^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 701 702This function must only be called by the primary CPU. 703 704On entry to this function the calling primary CPU must be executing in AArch32 705EL3, little-endian data access, and all interrupt sources masked: 706 707:: 708 709 PSTATE.AIF = 0x7 710 SCTLR.EE = 0 711 712R0 and R1 are used to pass information from the Trusted Boot Firmware to the 713platform code in AArch32 EL3 Runtime Software: 714 715:: 716 717 R0 : Reserved for common TF-A information 718 R1 : Platform specific information 719 720Use of the R0 and R1 parameters 721''''''''''''''''''''''''''''''' 722 723The parameters are platform specific and the convention is that ``R0`` conveys 724information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 725can be used for other platform specific purpose. This convention allows 726platforms which use TF-A's BL1 and BL2 images to transfer additional platform 727specific information from Secure Boot without conflicting with future 728evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 729 730The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 731information can be obtained in a platform defined manner, e.g. compiled into 732the AArch32 EL3 Runtime Software, or provided in a platform defined memory 733location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 734via the Cold boot Initialization parameters. This data may need to be cleaned 735out of the CPU caches if it is provided by an earlier boot stage and then 736accessed by AArch32 EL3 Runtime Software before the caches are enabled. 737 738When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 739``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 740Software platform code. 741 742MMU, Data caches & Coherency 743'''''''''''''''''''''''''''' 744 745AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 746data caches or interconnect coherency in its entrypoint. They must be explicitly 747enabled if required. 748 749Data structures used in cold boot interface 750''''''''''''''''''''''''''''''''''''''''''' 751 752The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 753of ``bl31_params``. The ``bl_params`` structure is based on the convention 754described in AArch64 BL31 cold boot interface section. 755 756Required CPU state for warm boot initialization 757^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 758 759When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 760Runtime Software must ensure execution of a warm boot initialization entrypoint. 761If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 762then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 763boot entrypoint by arranging for the BL1 platform function, 764plat_get_my_entrypoint(), to return a non-zero value. 765 766In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 767data access and all interrupt sources masked: 768 769:: 770 771 PSTATE.AIF = 0x7 772 SCTLR.EE = 0 773 774The warm boot entrypoint may be implemented by using TF-A 775``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 776the pre-requisites mentioned in the 777:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 778 779EL3 runtime services framework 780------------------------------ 781 782Software executing in the non-secure state and in the secure state at exception 783levels lower than EL3 will request runtime services using the Secure Monitor 784Call (SMC) instruction. These requests will follow the convention described in 785the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 786identifiers to each SMC request and describes how arguments are passed and 787returned. 788 789The EL3 runtime services framework enables the development of services by 790different providers that can be easily integrated into final product firmware. 791The following sections describe the framework which facilitates the 792registration, initialization and use of runtime services in EL3 Runtime 793Software (BL31). 794 795The design of the runtime services depends heavily on the concepts and 796definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 797Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 798conventions. Please refer to that document for more detailed explanation of 799these terms. 800 801The following runtime services are expected to be implemented first. They have 802not all been instantiated in the current implementation. 803 804#. Standard service calls 805 806 This service is for management of the entire system. The Power State 807 Coordination Interface (`PSCI`_) is the first set of standard service calls 808 defined by Arm (see PSCI section later). 809 810#. Secure-EL1 Payload Dispatcher service 811 812 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 813 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 814 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 815 The Secure Monitor will make these world switches in response to SMCs. The 816 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 817 Application Call OEN ranges. 818 819 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 820 not defined by the `SMCCC`_ or any other standard. As a result, each 821 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 822 service - within TF-A this service is referred to as the Secure-EL1 Payload 823 Dispatcher (SPD). 824 825 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 826 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 827 :ref:`firmware_design_sel1_spd` section below. 828 829#. CPU implementation service 830 831 This service will provide an interface to CPU implementation specific 832 services for a given platform e.g. access to processor errata workarounds. 833 This service is currently unimplemented. 834 835Additional services for Arm Architecture, SiP and OEM calls can be implemented. 836Each implemented service handles a range of SMC function identifiers as 837described in the `SMCCC`_. 838 839Registration 840~~~~~~~~~~~~ 841 842A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 843the name of the service, the range of OENs covered, the type of service and 844initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 845This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 846the framework to find all service descriptors included into BL31. 847 848The specific service for a SMC Function is selected based on the OEN and call 849type of the Function ID, and the framework uses that information in the service 850descriptor to identify the handler for the SMC Call. 851 852The service descriptors do not include information to identify the precise set 853of SMC function identifiers supported by this service implementation, the 854security state from which such calls are valid nor the capability to support 85564-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 856to these aspects of a SMC call is the responsibility of the service 857implementation, the framework is focused on integration of services from 858different providers and minimizing the time taken by the framework before the 859service handler is invoked. 860 861Details of the parameters, requirements and behavior of the initialization and 862call handling functions are provided in the following sections. 863 864Initialization 865~~~~~~~~~~~~~~ 866 867``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 868framework running on the primary CPU during cold boot as part of the BL31 869initialization. This happens prior to initializing a Trusted OS and running 870Normal world boot firmware that might in turn use these services. 871Initialization involves validating each of the declared runtime service 872descriptors, calling the service initialization function and populating the 873index used for runtime lookup of the service. 874 875The BL31 linker script collects all of the declared service descriptors into a 876single array and defines symbols that allow the framework to locate and traverse 877the array, and determine its size. 878 879The framework does basic validation of each descriptor to halt firmware 880initialization if service declaration errors are detected. The framework does 881not check descriptors for the following error conditions, and may behave in an 882unpredictable manner under such scenarios: 883 884#. Overlapping OEN ranges 885#. Multiple descriptors for the same range of OENs and ``call_type`` 886#. Incorrect range of owning entity numbers for a given ``call_type`` 887 888Once validated, the service ``init()`` callback is invoked. This function carries 889out any essential EL3 initialization before servicing requests. The ``init()`` 890function is only invoked on the primary CPU during cold boot. If the service 891uses per-CPU data this must either be initialized for all CPUs during this call, 892or be done lazily when a CPU first issues an SMC call to that service. If 893``init()`` returns anything other than ``0``, this is treated as an initialization 894error and the service is ignored: this does not cause the firmware to halt. 895 896The OEN and call type fields present in the SMC Function ID cover a total of 897128 distinct services, but in practice a single descriptor can cover a range of 898OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 899service handler, the framework uses an array of 128 indices that map every 900distinct OEN/call-type combination either to one of the declared services or to 901indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 902populated for all of the OENs covered by a service after the service ``init()`` 903function has reported success. So a service that fails to initialize will never 904have it's ``handle()`` function invoked. 905 906The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 907Function ID call type and OEN onto a specific service handler in the 908``rt_svc_descs[]`` array. 909 910|Image 1| 911 912.. _handling-an-smc: 913 914Handling an SMC 915~~~~~~~~~~~~~~~ 916 917When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 918Function ID is passed in W0 from the lower exception level (as per the 919`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 920SMC Function which indicates the SMC64 calling convention: such calls are 921ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 922in R0/X0. 923 924Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 925Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 926resulting value might indicate a service that has no handler, in this case the 927framework will also report an Unknown SMC Function ID. Otherwise, the value is 928used as a further index into the ``rt_svc_descs[]`` array to locate the required 929service and handler. 930 931The service's ``handle()`` callback is provided with five of the SMC parameters 932directly, the others are saved into memory for retrieval (if needed) by the 933handler. The handler is also provided with an opaque ``handle`` for use with the 934supporting library for parameter retrieval, setting return values and context 935manipulation. The ``flags`` parameter indicates the security state of the caller 936and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 937up the execution stack for the handler, and invokes the services ``handle()`` 938function. 939 940On return from the handler the result registers are populated in X0-X7 as needed 941before restoring the stack and CPU state and returning from the original SMC. 942 943Exception Handling Framework 944---------------------------- 945 946Please refer to the :ref:`Exception Handling Framework` document. 947 948Power State Coordination Interface 949---------------------------------- 950 951TODO: Provide design walkthrough of PSCI implementation. 952 953The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 954mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 955`Power State Coordination Interface PDD`_ are implemented. The table lists 956the PSCI v1.1 APIs and their support in generic code. 957 958An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 959requires the platform to export a part of the implementation. Hence the level 960of support of the mandatory APIs depends upon the support exported by the 961platform port as well. The Juno and FVP (all variants) platforms export all the 962required support. 963 964+-----------------------------+-------------+-------------------------------+ 965| PSCI v1.1 API | Supported | Comments | 966+=============================+=============+===============================+ 967| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 968+-----------------------------+-------------+-------------------------------+ 969| ``CPU_SUSPEND`` | Yes\* | | 970+-----------------------------+-------------+-------------------------------+ 971| ``CPU_OFF`` | Yes\* | | 972+-----------------------------+-------------+-------------------------------+ 973| ``CPU_ON`` | Yes\* | | 974+-----------------------------+-------------+-------------------------------+ 975| ``AFFINITY_INFO`` | Yes | | 976+-----------------------------+-------------+-------------------------------+ 977| ``MIGRATE`` | Yes\*\* | | 978+-----------------------------+-------------+-------------------------------+ 979| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 980+-----------------------------+-------------+-------------------------------+ 981| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 982+-----------------------------+-------------+-------------------------------+ 983| ``SYSTEM_OFF`` | Yes\* | | 984+-----------------------------+-------------+-------------------------------+ 985| ``SYSTEM_RESET`` | Yes\* | | 986+-----------------------------+-------------+-------------------------------+ 987| ``PSCI_FEATURES`` | Yes | | 988+-----------------------------+-------------+-------------------------------+ 989| ``CPU_FREEZE`` | No | | 990+-----------------------------+-------------+-------------------------------+ 991| ``CPU_DEFAULT_SUSPEND`` | No | | 992+-----------------------------+-------------+-------------------------------+ 993| ``NODE_HW_STATE`` | Yes\* | | 994+-----------------------------+-------------+-------------------------------+ 995| ``SYSTEM_SUSPEND`` | Yes\* | | 996+-----------------------------+-------------+-------------------------------+ 997| ``PSCI_SET_SUSPEND_MODE`` | No | | 998+-----------------------------+-------------+-------------------------------+ 999| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1000+-----------------------------+-------------+-------------------------------+ 1001| ``PSCI_STAT_COUNT`` | Yes\* | | 1002+-----------------------------+-------------+-------------------------------+ 1003| ``SYSTEM_RESET2`` | Yes\* | | 1004+-----------------------------+-------------+-------------------------------+ 1005| ``MEM_PROTECT`` | Yes\* | | 1006+-----------------------------+-------------+-------------------------------+ 1007| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1008+-----------------------------+-------------+-------------------------------+ 1009 1010\*Note : These PSCI APIs require platform power management hooks to be 1011registered with the generic PSCI code to be supported. 1012 1013\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1014hooks to be registered with the generic PSCI code to be supported. 1015 1016The PSCI implementation in TF-A is a library which can be integrated with 1017AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1018integrating PSCI library with AArch32 EL3 Runtime Software can be found 1019at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1020 1021.. _firmware_design_sel1_spd: 1022 1023Secure-EL1 Payloads and Dispatchers 1024----------------------------------- 1025 1026On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1027the Trusted OS is coupled with a companion runtime service in the BL31 1028firmware. This service is responsible for the initialisation of the Trusted 1029OS and all communications with it. The Trusted OS is the BL32 stage of the 1030boot flow in TF-A. The firmware will attempt to locate, load and execute a 1031BL32 image. 1032 1033TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1034the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1035 1036TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1037Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1038production system using the Runtime Services Framework. On such a system, the 1039Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1040service. The TF-A build system expects that the dispatcher will define the 1041build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1042as a binary or to compile from source depending on whether the ``BL32`` build 1043option is specified or not. 1044 1045The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1046communication with the normal-world software running in EL1/EL2. Communication 1047is initiated by the normal-world software 1048 1049- either directly through a Fast SMC (as defined in the `SMCCC`_) 1050 1051- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1052 informs the TSPD about the requested power management operation. This allows 1053 the TSP to prepare for or respond to the power state change 1054 1055The TSPD service is responsible for. 1056 1057- Initializing the TSP 1058 1059- Routing requests and responses between the secure and the non-secure 1060 states during the two types of communications just described 1061 1062Initializing a BL32 Image 1063~~~~~~~~~~~~~~~~~~~~~~~~~ 1064 1065The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1066the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1067so. This is provided by: 1068 1069.. code:: c 1070 1071 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1072 1073which returns a reference to the ``entry_point_info`` structure corresponding to 1074the image which will be run in the specified security state. The SPD uses this 1075API to get entry point information for the SECURE image, BL32. 1076 1077In the absence of a BL32 image, BL31 passes control to the normal world 1078bootloader image (BL33). When the BL32 image is present, it is typical 1079that the SPD wants control to be passed to BL32 first and then later to BL33. 1080 1081To do this the SPD has to register a BL32 initialization function during 1082initialization of the SPD service. The BL32 initialization function has this 1083prototype: 1084 1085.. code:: c 1086 1087 int32_t init(void); 1088 1089and is registered using the ``bl31_register_bl32_init()`` function. 1090 1091TF-A supports two approaches for the SPD to pass control to BL32 before 1092returning through EL3 and running the non-trusted firmware (BL33): 1093 1094#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1095 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1096 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1097 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1098 1099 When the BL32 has completed initialization at Secure-EL1, it returns to 1100 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1101 receipt of this SMC, the SPD service handler should switch the CPU context 1102 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1103 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1104 the normal world firmware BL33. On return from the handler the framework 1105 will exit to EL2 and run BL33. 1106 1107#. The BL32 setup function registers an initialization function using 1108 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1109 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1110 entrypoint. 1111 1112 .. note:: 1113 The Test SPD service included with TF-A provides one implementation 1114 of such a mechanism. 1115 1116 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1117 SPD service handler invokes the synchronous call return mechanism to return 1118 to the BL32 initialization function. On return from this function, 1119 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1120 continue the boot process in the normal world. 1121 1122Crash Reporting in BL31 1123----------------------- 1124 1125BL31 implements a scheme for reporting the processor state when an unhandled 1126exception is encountered. The reporting mechanism attempts to preserve all the 1127register contents and report it via a dedicated UART (PL011 console). BL31 1128reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1129 1130A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1131the per-CPU pointer cache. The implementation attempts to minimise the memory 1132required for this feature. The file ``crash_reporting.S`` contains the 1133implementation for crash reporting. 1134 1135The sample crash output is shown below. 1136 1137:: 1138 1139 x0 = 0x000000002a4a0000 1140 x1 = 0x0000000000000001 1141 x2 = 0x0000000000000002 1142 x3 = 0x0000000000000003 1143 x4 = 0x0000000000000004 1144 x5 = 0x0000000000000005 1145 x6 = 0x0000000000000006 1146 x7 = 0x0000000000000007 1147 x8 = 0x0000000000000008 1148 x9 = 0x0000000000000009 1149 x10 = 0x0000000000000010 1150 x11 = 0x0000000000000011 1151 x12 = 0x0000000000000012 1152 x13 = 0x0000000000000013 1153 x14 = 0x0000000000000014 1154 x15 = 0x0000000000000015 1155 x16 = 0x0000000000000016 1156 x17 = 0x0000000000000017 1157 x18 = 0x0000000000000018 1158 x19 = 0x0000000000000019 1159 x20 = 0x0000000000000020 1160 x21 = 0x0000000000000021 1161 x22 = 0x0000000000000022 1162 x23 = 0x0000000000000023 1163 x24 = 0x0000000000000024 1164 x25 = 0x0000000000000025 1165 x26 = 0x0000000000000026 1166 x27 = 0x0000000000000027 1167 x28 = 0x0000000000000028 1168 x29 = 0x0000000000000029 1169 x30 = 0x0000000088000b78 1170 scr_el3 = 0x000000000003073d 1171 sctlr_el3 = 0x00000000b0cd183f 1172 cptr_el3 = 0x0000000000000000 1173 tcr_el3 = 0x000000008080351c 1174 daif = 0x00000000000002c0 1175 mair_el3 = 0x00000000004404ff 1176 spsr_el3 = 0x0000000060000349 1177 elr_el3 = 0x0000000088000114 1178 ttbr0_el3 = 0x0000000004018201 1179 esr_el3 = 0x00000000be000000 1180 far_el3 = 0x0000000000000000 1181 spsr_el1 = 0x0000000000000000 1182 elr_el1 = 0x0000000000000000 1183 spsr_abt = 0x0000000000000000 1184 spsr_und = 0x0000000000000000 1185 spsr_irq = 0x0000000000000000 1186 spsr_fiq = 0x0000000000000000 1187 sctlr_el1 = 0x0000000030d00800 1188 actlr_el1 = 0x0000000000000000 1189 cpacr_el1 = 0x0000000000000000 1190 csselr_el1 = 0x0000000000000000 1191 sp_el1 = 0x0000000000000000 1192 esr_el1 = 0x0000000000000000 1193 ttbr0_el1 = 0x0000000000000000 1194 ttbr1_el1 = 0x0000000000000000 1195 mair_el1 = 0x0000000000000000 1196 amair_el1 = 0x0000000000000000 1197 tcr_el1 = 0x0000000000000000 1198 tpidr_el1 = 0x0000000000000000 1199 tpidr_el0 = 0x0000000000000000 1200 tpidrro_el0 = 0x0000000000000000 1201 par_el1 = 0x0000000000000000 1202 mpidr_el1 = 0x0000000080000000 1203 afsr0_el1 = 0x0000000000000000 1204 afsr1_el1 = 0x0000000000000000 1205 contextidr_el1 = 0x0000000000000000 1206 vbar_el1 = 0x0000000000000000 1207 cntp_ctl_el0 = 0x0000000000000000 1208 cntp_cval_el0 = 0x0000000000000000 1209 cntv_ctl_el0 = 0x0000000000000000 1210 cntv_cval_el0 = 0x0000000000000000 1211 cntkctl_el1 = 0x0000000000000000 1212 sp_el0 = 0x0000000004014940 1213 isr_el1 = 0x0000000000000000 1214 dacr32_el2 = 0x0000000000000000 1215 ifsr32_el2 = 0x0000000000000000 1216 icc_hppir0_el1 = 0x00000000000003ff 1217 icc_hppir1_el1 = 0x00000000000003ff 1218 icc_ctlr_el3 = 0x0000000000080400 1219 gicd_ispendr regs (Offsets 0x200-0x278) 1220 Offset Value 1221 0x200: 0x0000000000000000 1222 0x208: 0x0000000000000000 1223 0x210: 0x0000000000000000 1224 0x218: 0x0000000000000000 1225 0x220: 0x0000000000000000 1226 0x228: 0x0000000000000000 1227 0x230: 0x0000000000000000 1228 0x238: 0x0000000000000000 1229 0x240: 0x0000000000000000 1230 0x248: 0x0000000000000000 1231 0x250: 0x0000000000000000 1232 0x258: 0x0000000000000000 1233 0x260: 0x0000000000000000 1234 0x268: 0x0000000000000000 1235 0x270: 0x0000000000000000 1236 0x278: 0x0000000000000000 1237 1238Guidelines for Reset Handlers 1239----------------------------- 1240 1241TF-A implements a framework that allows CPU and platform ports to perform 1242actions very early after a CPU is released from reset in both the cold and warm 1243boot paths. This is done by calling the ``reset_handler()`` function in both 1244the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1245handling functions. 1246 1247Details for implementing a CPU specific reset handler can be found in 1248:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a 1249platform specific reset handler can be found in the :ref:`Porting Guide` (see 1250the``plat_reset_handler()`` function). 1251 1252When adding functionality to a reset handler, keep in mind that if a different 1253reset handling behavior is required between the first and the subsequent 1254invocations of the reset handling code, this should be detected at runtime. 1255In other words, the reset handler should be able to detect whether an action has 1256already been performed and act as appropriate. Possible courses of actions are, 1257e.g. skip the action the second time, or undo/redo it. 1258 1259.. _configuring-secure-interrupts: 1260 1261Configuring secure interrupts 1262----------------------------- 1263 1264The GIC driver is responsible for performing initial configuration of secure 1265interrupts on the platform. To this end, the platform is expected to provide the 1266GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1267interrupt configuration during the driver initialisation. 1268 1269Secure interrupt configuration are specified in an array of secure interrupt 1270properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1271``interrupt_props`` member points to an array of interrupt properties. Each 1272element of the array specifies the interrupt number and its attributes 1273(priority, group, configuration). Each element of the array shall be populated 1274by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1275 1276- 13-bit interrupt number, 1277 1278- 8-bit interrupt priority, 1279 1280- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1281 ``INTR_TYPE_NS``), 1282 1283- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1284 ``GIC_INTR_CFG_EDGE``). 1285 1286.. _firmware_design_cpu_ops_fwk: 1287 1288CPU specific operations framework 1289--------------------------------- 1290 1291Certain aspects of the Armv8-A architecture are implementation defined, 1292that is, certain behaviours are not architecturally defined, but must be 1293defined and documented by individual processor implementations. TF-A 1294implements a framework which categorises the common implementation defined 1295behaviours and allows a processor to export its implementation of that 1296behaviour. The categories are: 1297 1298#. Processor specific reset sequence. 1299 1300#. Processor specific power down sequences. 1301 1302#. Processor specific register dumping as a part of crash reporting. 1303 1304#. Errata status reporting. 1305 1306Each of the above categories fulfils a different requirement. 1307 1308#. allows any processor specific initialization before the caches and MMU 1309 are turned on, like implementation of errata workarounds, entry into 1310 the intra-cluster coherency domain etc. 1311 1312#. allows each processor to implement the power down sequence mandated in 1313 its Technical Reference Manual (TRM). 1314 1315#. allows a processor to provide additional information to the developer 1316 in the event of a crash, for example Cortex-A53 has registers which 1317 can expose the data cache contents. 1318 1319#. allows a processor to define a function that inspects and reports the status 1320 of all errata workarounds on that processor. 1321 1322Please note that only 2. is mandated by the TRM. 1323 1324The CPU specific operations framework scales to accommodate a large number of 1325different CPUs during power down and reset handling. The platform can specify 1326any CPU optimization it wants to enable for each CPU. It can also specify 1327the CPU errata workarounds to be applied for each CPU type during reset 1328handling by defining CPU errata compile time macros. Details on these macros 1329can be found in the :ref:`Arm CPU Specific Build Macros` document. 1330 1331The CPU specific operations framework depends on the ``cpu_ops`` structure which 1332needs to be exported for each type of CPU in the platform. It is defined in 1333``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1334``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1335``cpu_reg_dump()``. 1336 1337The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1338suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1339exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1340configuration, these CPU specific files must be included in the build by 1341the platform makefile. The generic CPU specific operations framework code exists 1342in ``lib/cpus/aarch64/cpu_helpers.S``. 1343 1344CPU PCS 1345~~~~~~~ 1346 1347All assembly functions in CPU files are asked to follow a modified version of 1348the Procedure Call Standard (PCS) in their internals. This is done to ensure 1349calling these functions from outside the file doesn't unexpectedly corrupt 1350registers in the very early environment and to help the internals to be easier 1351to understand. Please see the :ref:`firmware_design_cpu_errata_implementation` 1352for any function specific restrictions. 1353 1354+--------------+---------------------------------+ 1355| register | use | 1356+==============+=================================+ 1357| x0 - x15 | scratch | 1358+--------------+---------------------------------+ 1359| x16, x17 | do not use (used by the linker) | 1360+--------------+---------------------------------+ 1361| x18 | do not use (platform register) | 1362+--------------+---------------------------------+ 1363| x19 - x28 | callee saved | 1364+--------------+---------------------------------+ 1365| x29, x30 | FP, LR | 1366+--------------+---------------------------------+ 1367 1368.. _firmware_design_cpu_specific_reset_handling: 1369 1370CPU specific Reset Handling 1371~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1372 1373After a reset, the state of the CPU when it calls generic reset handler is: 1374MMU turned off, both instruction and data caches turned off, not part 1375of any coherency domain and no stack. 1376 1377The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1378the platform to perform any system initialization required and any system 1379errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1380the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1381array and returns it. Note that only the part number and implementer fields 1382in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1383the returned ``cpu_ops`` is then invoked which executes the required reset 1384handling for that CPU and also any errata workarounds enabled by the platform. 1385 1386It should be defined using the ``cpu_reset_func_{start,end}`` macros and its 1387body may only clobber x0 to x14 with x14 being the cpu_rev parameter. 1388 1389CPU specific power down sequence 1390~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1391 1392During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1393entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1394retrieved during power down sequences. 1395 1396Various CPU drivers register handlers to perform power down at certain power 1397levels for that specific CPU. The PSCI service, upon receiving a power down 1398request, determines the highest power level at which to execute power down 1399sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1400pick the right power down handler for the requested level. The function 1401retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1402retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1403requested power level is higher than what a CPU driver supports, the handler 1404registered for highest level is invoked. 1405 1406At runtime the platform hooks for power down are invoked by the PSCI service to 1407perform platform specific operations during a power down sequence, for example 1408turning off CCI coherency during a cluster power down. 1409 1410CPU specific register reporting during crash 1411~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1412 1413If the crash reporting is enabled in BL31, when a crash occurs, the crash 1414reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1415``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1416``cpu_ops`` is invoked, which then returns the CPU specific register values to 1417be reported and a pointer to the ASCII list of register names in a format 1418expected by the crash reporting framework. 1419 1420.. _firmware_design_cpu_errata_implementation: 1421 1422CPU errata implementation 1423~~~~~~~~~~~~~~~~~~~~~~~~~ 1424 1425Errata workarounds for CPUs supported in TF-A are applied during both cold and 1426warm boots, shortly after reset. Individual Errata workarounds are enabled as 1427build options. Some errata workarounds have potential run-time implications; 1428therefore some are enabled by default, others not. Platform ports shall 1429override build options to enable or disable errata as appropriate. The CPU 1430drivers take care of applying errata workarounds that are enabled and applicable 1431to a given CPU. 1432 1433Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form: 1434``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in 1435:ref:`arm_cpu_macros_errata_workarounds` on when it should apply. 1436 1437Errata framework 1438^^^^^^^^^^^^^^^^ 1439 1440The errata framework is a convention and a small library to allow errata to be 1441automatically discovered. It enables compliant errata to be automatically 1442applied and reported at runtime (either by status reporting or the errata ABI). 1443 1444To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that 1445declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things: 1446 1447#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>`` 1448 1449 It should check whether this erratum applies on this revision of this CPU. 1450 It will be called with the CPU revision as its first parameter (x0) and 1451 should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``. 1452 1453 It may only clobber x0 to x4. The rest should be treated as callee-saved. 1454 1455#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa`` 1456 1457 It should obtain the cpu revision (with ``cpu_get_rev_var``), call its 1458 revision checker, and perform the mitigation, should the erratum apply. 1459 1460 It may only clobber x0 to x8. The rest should be treated as callee-saved. 1461 1462#. Register itself to the framework 1463 1464 Do this with 1465 ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>`` 1466 where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described 1467 above. 1468 1469See the next section on how to do this easily. 1470 1471.. note:: 1472 1473 CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the 1474 ``erratum_id`` for the checker and the workaround functions become the 1475 ``number`` part of its name and the ``ERRATUM(<number>)`` part of the 1476 registration should instead be ``CVE(<year>, <number>)``. In the extremely 1477 unlikely scenario where a CVE and an erratum numbers clash, the CVE number 1478 should be prefixed with a zero. 1479 1480 Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``. 1481 1482.. note:: 1483 1484 AArch32 uses the legacy convention. The checker function has the format 1485 ``check_errata_<erratum_id>`` and the workaround has the format 1486 ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform 1487 letter and number name of the CPU. 1488 1489 For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``. 1490 1491Errata framework helpers 1492^^^^^^^^^^^^^^^^^^^^^^^^ 1493 1494Writing these errata involves lots of boilerplate and repetitive code. On 1495AArch64 there are helpers to omit most of this. They are located in 1496``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement 1497errata. Please see their comments on how to use them. 1498 1499The most common type of erratum workaround, one that just sets a "chicken" bit 1500in some arbitrary register, would have an implementation for the Cortex-A77, 1501erratum #1925769 like:: 1502 1503 workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 1504 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 1505 workaround_reset_end cortex_a77, ERRATUM(1925769) 1506 1507 check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 1508 1509Status reporting 1510^^^^^^^^^^^^^^^^ 1511 1512In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1513runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic 1514errata status reporting function. It will read the ``errata_entries`` list of 1515that cpu and will report whether each known erratum was applied and, if not, 1516whether it should have been. 1517 1518Reporting the status of errata workaround is for informational purpose only; it 1519has no functional significance. 1520 1521Memory layout of BL images 1522-------------------------- 1523 1524Each bootloader image can be divided in 2 parts: 1525 1526- the static contents of the image. These are data actually stored in the 1527 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1528 sections; 1529 1530- the run-time contents of the image. These are data that don't occupy any 1531 space in the binary on the disk. The ELF binary just contains some 1532 metadata indicating where these data will be stored at run-time and the 1533 corresponding sections need to be allocated and initialized at run-time. 1534 In the ELF terminology, they are called ``NOBITS`` sections. 1535 1536All PROGBITS sections are grouped together at the beginning of the image, 1537followed by all NOBITS sections. This is true for all TF-A images and it is 1538governed by the linker scripts. This ensures that the raw binary images are 1539as small as possible. If a NOBITS section was inserted in between PROGBITS 1540sections then the resulting binary file would contain zero bytes in place of 1541this NOBITS section, making the image unnecessarily bigger. Smaller images 1542allow faster loading from the FIP to the main memory. 1543 1544For BL31, a platform can specify an alternate location for NOBITS sections 1545(other than immediately following PROGBITS sections) by setting 1546``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1547``BL31_NOBITS_LIMIT``. 1548 1549Linker scripts and symbols 1550~~~~~~~~~~~~~~~~~~~~~~~~~~ 1551 1552Each bootloader stage image layout is described by its own linker script. The 1553linker scripts export some symbols into the program symbol table. Their values 1554correspond to particular addresses. TF-A code can refer to these symbols to 1555figure out the image memory layout. 1556 1557Linker symbols follow the following naming convention in TF-A. 1558 1559- ``__<SECTION>_START__`` 1560 1561 Start address of a given section named ``<SECTION>``. 1562 1563- ``__<SECTION>_END__`` 1564 1565 End address of a given section named ``<SECTION>``. If there is an alignment 1566 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1567 to the end address of the section's actual contents, rounded up to the right 1568 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1569 actual end address of the section's contents. 1570 1571- ``__<SECTION>_UNALIGNED_END__`` 1572 1573 End address of a given section named ``<SECTION>`` without any padding or 1574 rounding up due to some alignment constraint. 1575 1576- ``__<SECTION>_SIZE__`` 1577 1578 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1579 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1580 corresponds to the size of the section's actual contents, rounded up to the 1581 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1582 to know the actual size of the section's contents. 1583 1584- ``__<SECTION>_UNALIGNED_SIZE__`` 1585 1586 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1587 rounding up due to some alignment constraint. In other words, 1588 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1589 1590Some of the linker symbols are mandatory as TF-A code relies on them to be 1591defined. They are listed in the following subsections. Some of them must be 1592provided for each bootloader stage and some are specific to a given bootloader 1593stage. 1594 1595The linker scripts define some extra, optional symbols. They are not actually 1596used by any code but they help in understanding the bootloader images' memory 1597layout as they are easy to spot in the link map files. 1598 1599Common linker symbols 1600^^^^^^^^^^^^^^^^^^^^^ 1601 1602All BL images share the following requirements: 1603 1604- The BSS section must be zero-initialised before executing any C code. 1605- The coherent memory section (if enabled) must be zero-initialised as well. 1606- The MMU setup code needs to know the extents of the coherent and read-only 1607 memory regions to set the right memory attributes. When 1608 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1609 read-only memory region is divided between code and data. 1610 1611The following linker symbols are defined for this purpose: 1612 1613- ``__BSS_START__`` 1614- ``__BSS_SIZE__`` 1615- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1616- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1617- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1618- ``__RO_START__`` 1619- ``__RO_END__`` 1620- ``__TEXT_START__`` 1621- ``__TEXT_END_UNALIGNED__`` 1622- ``__TEXT_END__`` 1623- ``__RODATA_START__`` 1624- ``__RODATA_END_UNALIGNED__`` 1625- ``__RODATA_END__`` 1626 1627BL1's linker symbols 1628^^^^^^^^^^^^^^^^^^^^ 1629 1630BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1631it is entirely executed in place but it needs some read-write memory for its 1632mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1633relocated from ROM to RAM before executing any C code. 1634 1635The following additional linker symbols are defined for BL1: 1636 1637- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1638 and ``.data`` section in ROM. 1639- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1640 aligned on a 16-byte boundary. 1641- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1642 copied over. Must be aligned on a 16-byte boundary. 1643- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1644- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1645- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1646 1647How to choose the right base addresses for each bootloader stage image 1648~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1649 1650There is currently no support for dynamic image loading in TF-A. This means 1651that all bootloader images need to be linked against their ultimate runtime 1652locations and the base addresses of each image must be chosen carefully such 1653that images don't overlap each other in an undesired way. As the code grows, 1654the base addresses might need adjustments to cope with the new memory layout. 1655 1656The memory layout is completely specific to the platform and so there is no 1657general recipe for choosing the right base addresses for each bootloader image. 1658However, there are tools to aid in understanding the memory layout. These are 1659the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1660being the stage bootloader. They provide a detailed view of the memory usage of 1661each image. Among other useful information, they provide the end address of 1662each image. 1663 1664- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1665- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1666- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1667- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1668 1669For each bootloader image, the platform code must provide its start address 1670as well as a limit address that it must not overstep. The latter is used in the 1671linker scripts to check that the image doesn't grow past that address. If that 1672happens, the linker will issue a message similar to the following: 1673 1674:: 1675 1676 aarch64-none-elf-ld: BLx has exceeded its limit. 1677 1678Additionally, if the platform memory layout implies some image overlaying like 1679on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1680sections must not overstep. The platform code must provide those. 1681 1682TF-A does not provide any mechanism to verify at boot time that the memory 1683to load a new image is free to prevent overwriting a previously loaded image. 1684The platform must specify the memory available in the system for all the 1685relevant BL images to be loaded. 1686 1687For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1688return the region defined by the platform where BL1 intends to load BL2. The 1689``load_image()`` function performs bounds check for the image size based on the 1690base and maximum image size provided by the platforms. Platforms must take 1691this behaviour into account when defining the base/size for each of the images. 1692 1693Memory layout on Arm development platforms 1694^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1695 1696The following list describes the memory layout on the Arm development platforms: 1697 1698- A 4KB page of shared memory is used for communication between Trusted 1699 Firmware and the platform's power controller. This is located at the base of 1700 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1701 images is reduced by the size of the shared memory. 1702 1703 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1704 this is also used for the MHU payload when passing messages to and from the 1705 SCP. 1706 1707- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1708 and also the dynamic firmware configurations. 1709 1710- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1711 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1712 data are relocated to the top of Trusted SRAM at runtime. 1713 1714- BL2 is loaded below BL1 RW 1715 1716- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1717 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1718 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1719 remain valid only until execution reaches the EL3 Runtime Software entry 1720 point during a cold boot. 1721 1722- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1723 region and transferred to the SCP before being overwritten by EL3 Runtime 1724 Software. 1725 1726- BL32 (for AArch64) can be loaded in one of the following locations: 1727 1728 - Trusted SRAM 1729 - Trusted DRAM (FVP only) 1730 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1731 controller) 1732 1733 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1734 BL31. 1735 1736The location of the BL32 image will result in different memory maps. This is 1737illustrated for both FVP and Juno in the following diagrams, using the TSP as 1738an example. 1739 1740.. note:: 1741 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1742 layout of the other images in Trusted SRAM. 1743 1744CONFIG section in memory layouts shown below contains: 1745 1746:: 1747 1748 +--------------------+ 1749 |bl2_mem_params_descs| 1750 |--------------------| 1751 | fw_configs | 1752 +--------------------+ 1753 1754``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1755BL image during boot. 1756 1757``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1758 1759**FVP with TSP in Trusted SRAM with firmware configs :** 1760(These diagrams only cover the AArch64 case) 1761 1762:: 1763 1764 DRAM 1765 0xffffffff +----------+ 1766 | EL3 TZC | 1767 0xffe00000 |----------| (secure) 1768 | AP TZC | 1769 0xff000000 +----------+ 1770 : : 1771 0x82100000 |----------| 1772 |HW_CONFIG | 1773 0x82000000 |----------| (non-secure) 1774 | | 1775 0x80000000 +----------+ 1776 1777 Trusted DRAM 1778 0x08000000 +----------+ 1779 |HW_CONFIG | 1780 0x07f00000 |----------| 1781 : : 1782 | | 1783 0x06000000 +----------+ 1784 1785 Trusted SRAM 1786 0x04040000 +----------+ loaded by BL2 +----------------+ 1787 | BL1 (rw) | <<<<<<<<<<<<< | | 1788 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1789 | BL2 | <<<<<<<<<<<<< | | 1790 |----------| <<<<<<<<<<<<< |----------------| 1791 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1792 | | <<<<<<<<<<<<< |----------------| 1793 | | <<<<<<<<<<<<< | BL32 | 1794 0x04003000 +----------+ +----------------+ 1795 | CONFIG | 1796 0x04001000 +----------+ 1797 | Shared | 1798 0x04000000 +----------+ 1799 1800 Trusted ROM 1801 0x04000000 +----------+ 1802 | BL1 (ro) | 1803 0x00000000 +----------+ 1804 1805**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1806 1807:: 1808 1809 DRAM 1810 0xffffffff +--------------+ 1811 | EL3 TZC | 1812 0xffe00000 |--------------| (secure) 1813 | AP TZC | 1814 0xff000000 +--------------+ 1815 : : 1816 0x82100000 |--------------| 1817 | HW_CONFIG | 1818 0x82000000 |--------------| (non-secure) 1819 | | 1820 0x80000000 +--------------+ 1821 1822 Trusted DRAM 1823 0x08000000 +--------------+ 1824 | HW_CONFIG | 1825 0x07f00000 |--------------| 1826 : : 1827 | BL32 | 1828 0x06000000 +--------------+ 1829 1830 Trusted SRAM 1831 0x04040000 +--------------+ loaded by BL2 +----------------+ 1832 | BL1 (rw) | <<<<<<<<<<<<< | | 1833 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1834 | BL2 | <<<<<<<<<<<<< | | 1835 |--------------| <<<<<<<<<<<<< |----------------| 1836 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1837 | | +----------------+ 1838 0x04003000 +--------------+ 1839 | CONFIG | 1840 0x04001000 +--------------+ 1841 | Shared | 1842 0x04000000 +--------------+ 1843 1844 Trusted ROM 1845 0x04000000 +--------------+ 1846 | BL1 (ro) | 1847 0x00000000 +--------------+ 1848 1849**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1850 1851:: 1852 1853 DRAM 1854 0xffffffff +----------+ 1855 | EL3 TZC | 1856 0xffe00000 |----------| (secure) 1857 | AP TZC | 1858 | (BL32) | 1859 0xff000000 +----------+ 1860 | | 1861 0x82100000 |----------| 1862 |HW_CONFIG | 1863 0x82000000 |----------| (non-secure) 1864 | | 1865 0x80000000 +----------+ 1866 1867 Trusted DRAM 1868 0x08000000 +----------+ 1869 |HW_CONFIG | 1870 0x7f000000 |----------| 1871 : : 1872 | | 1873 0x06000000 +----------+ 1874 1875 Trusted SRAM 1876 0x04040000 +----------+ loaded by BL2 +----------------+ 1877 | BL1 (rw) | <<<<<<<<<<<<< | | 1878 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1879 | BL2 | <<<<<<<<<<<<< | | 1880 |----------| <<<<<<<<<<<<< |----------------| 1881 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1882 | | +----------------+ 1883 0x04003000 +----------+ 1884 | CONFIG | 1885 0x04001000 +----------+ 1886 | Shared | 1887 0x04000000 +----------+ 1888 1889 Trusted ROM 1890 0x04000000 +----------+ 1891 | BL1 (ro) | 1892 0x00000000 +----------+ 1893 1894**Juno with BL32 in Trusted SRAM :** 1895 1896:: 1897 1898 DRAM 1899 0xFFFFFFFF +----------+ 1900 | SCP TZC | 1901 0xFFE00000 |----------| 1902 | EL3 TZC | 1903 0xFFC00000 |----------| (secure) 1904 | AP TZC | 1905 0xFF000000 +----------+ 1906 | | 1907 : : (non-secure) 1908 | | 1909 0x80000000 +----------+ 1910 1911 1912 Flash0 1913 0x0C000000 +----------+ 1914 : : 1915 0x0BED0000 |----------| 1916 | BL1 (ro) | 1917 0x0BEC0000 |----------| 1918 : : 1919 0x08000000 +----------+ BL31 is loaded 1920 after SCP_BL2 has 1921 Trusted SRAM been sent to SCP 1922 0x04040000 +----------+ loaded by BL2 +----------------+ 1923 | BL1 (rw) | <<<<<<<<<<<<< | | 1924 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1925 | BL2 | <<<<<<<<<<<<< | | 1926 |----------| <<<<<<<<<<<<< |----------------| 1927 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1928 | | <<<<<<<<<<<<< |----------------| 1929 | | <<<<<<<<<<<<< | BL32 | 1930 | | +----------------+ 1931 | | 1932 0x04001000 +----------+ 1933 | MHU | 1934 0x04000000 +----------+ 1935 1936**Juno with BL32 in TZC-secured DRAM :** 1937 1938:: 1939 1940 DRAM 1941 0xFFFFFFFF +----------+ 1942 | SCP TZC | 1943 0xFFE00000 |----------| 1944 | EL3 TZC | 1945 0xFFC00000 |----------| (secure) 1946 | AP TZC | 1947 | (BL32) | 1948 0xFF000000 +----------+ 1949 | | 1950 : : (non-secure) 1951 | | 1952 0x80000000 +----------+ 1953 1954 Flash0 1955 0x0C000000 +----------+ 1956 : : 1957 0x0BED0000 |----------| 1958 | BL1 (ro) | 1959 0x0BEC0000 |----------| 1960 : : 1961 0x08000000 +----------+ BL31 is loaded 1962 after SCP_BL2 has 1963 Trusted SRAM been sent to SCP 1964 0x04040000 +----------+ loaded by BL2 +----------------+ 1965 | BL1 (rw) | <<<<<<<<<<<<< | | 1966 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1967 | BL2 | <<<<<<<<<<<<< | | 1968 |----------| <<<<<<<<<<<<< |----------------| 1969 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1970 | | +----------------+ 1971 0x04001000 +----------+ 1972 | MHU | 1973 0x04000000 +----------+ 1974 1975.. _firmware_design_fip: 1976 1977Firmware Image Package (FIP) 1978---------------------------- 1979 1980Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1981potentially other payloads) into a single archive that can be loaded by TF-A 1982from non-volatile platform storage. A driver to load images from a FIP has 1983been added to the storage layer and allows a package to be read from supported 1984platform storage. A tool to create Firmware Image Packages is also provided 1985and described below. 1986 1987Firmware Image Package layout 1988~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1989 1990The FIP layout consists of a table of contents (ToC) followed by payload data. 1991The ToC itself has a header followed by one or more table entries. The ToC is 1992terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1993the offset equals the total size of the FIP file. All ToC entries describe some 1994payload data that has been appended to the end of the binary package. With the 1995information provided in the ToC entry the corresponding payload data can be 1996retrieved. 1997 1998:: 1999 2000 ------------------ 2001 | ToC Header | 2002 |----------------| 2003 | ToC Entry 0 | 2004 |----------------| 2005 | ToC Entry 1 | 2006 |----------------| 2007 | ToC End Marker | 2008 |----------------| 2009 | | 2010 | Data 0 | 2011 | | 2012 |----------------| 2013 | | 2014 | Data 1 | 2015 | | 2016 ------------------ 2017 2018The ToC header and entry formats are described in the header file 2019``include/tools_share/firmware_image_package.h``. This file is used by both the 2020tool and TF-A. 2021 2022The ToC header has the following fields: 2023 2024:: 2025 2026 `name`: The name of the ToC. This is currently used to validate the header. 2027 `serial_number`: A non-zero number provided by the creation tool 2028 `flags`: Flags associated with this data. 2029 Bits 0-31: Reserved 2030 Bits 32-47: Platform defined 2031 Bits 48-63: Reserved 2032 2033A ToC entry has the following fields: 2034 2035:: 2036 2037 `uuid`: All files are referred to by a pre-defined Universally Unique 2038 IDentifier [UUID] . The UUIDs are defined in 2039 `include/tools_share/firmware_image_package.h`. The platform translates 2040 the requested image name into the corresponding UUID when accessing the 2041 package. 2042 `offset_address`: The offset address at which the corresponding payload data 2043 can be found. The offset is calculated from the ToC base address. 2044 `size`: The size of the corresponding payload data in bytes. 2045 `flags`: Flags associated with this entry. None are yet defined. 2046 2047Firmware Image Package creation tool 2048~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2049 2050The FIP creation tool can be used to pack specified images into a binary 2051package that can be loaded by TF-A from platform storage. The tool currently 2052only supports packing bootloader images. Additional image definitions can be 2053added to the tool as required. 2054 2055The tool can be found in ``tools/fiptool``. 2056 2057Loading from a Firmware Image Package (FIP) 2058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2059 2060The Firmware Image Package (FIP) driver can load images from a binary package on 2061non-volatile platform storage. For the Arm development platforms, this is 2062currently NOR FLASH. 2063 2064Bootloader images are loaded according to the platform policy as specified by 2065the function ``plat_get_image_source()``. For the Arm development platforms, this 2066means the platform will attempt to load images from a Firmware Image Package 2067located at the start of NOR FLASH0. 2068 2069The Arm development platforms' policy is to only allow loading of a known set of 2070images. The platform policy can be modified to allow additional images. 2071 2072Use of coherent memory in TF-A 2073------------------------------ 2074 2075There might be loss of coherency when physical memory with mismatched 2076shareability, cacheability and memory attributes is accessed by multiple CPUs 2077(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2078in TF-A during power up/down sequences when coherency, MMU and caches are 2079turned on/off incrementally. 2080 2081TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2082in the translation tables. The translation granule size in TF-A is 4KB. This 2083is the smallest possible size of the coherent memory region. 2084 2085By default, all data structures which are susceptible to accesses with 2086mismatched attributes from various CPUs are allocated in a coherent memory 2087region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2088region accesses are Outer Shareable, non-cacheable and they can be accessed with 2089the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2090at least an extra page of memory, TF-A is able to work around coherency issues 2091due to mismatched memory attributes. 2092 2093The alternative to the above approach is to allocate the susceptible data 2094structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2095approach requires the data structures to be designed so that it is possible to 2096work around the issue of mismatched memory attributes by performing software 2097cache maintenance on them. 2098 2099Disabling the use of coherent memory in TF-A 2100~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2101 2102It might be desirable to avoid the cost of allocating coherent memory on 2103platforms which are memory constrained. TF-A enables inclusion of coherent 2104memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2105This flag is enabled by default. It can be disabled to choose the second 2106approach described above. 2107 2108The below sections analyze the data structures allocated in the coherent memory 2109region and the changes required to allocate them in normal memory. 2110 2111Coherent memory usage in PSCI implementation 2112~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2113 2114The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2115tree information for state management of power domains. By default, this data 2116structure is allocated in the coherent memory region in TF-A because it can be 2117accessed by multiple CPUs, either with caches enabled or disabled. 2118 2119.. code:: c 2120 2121 typedef struct non_cpu_pwr_domain_node { 2122 /* 2123 * Index of the first CPU power domain node level 0 which has this node 2124 * as its parent. 2125 */ 2126 unsigned int cpu_start_idx; 2127 2128 /* 2129 * Number of CPU power domains which are siblings of the domain indexed 2130 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2131 * -> cpu_start_idx + ncpus' have this node as their parent. 2132 */ 2133 unsigned int ncpus; 2134 2135 /* 2136 * Index of the parent power domain node. 2137 */ 2138 unsigned int parent_node; 2139 2140 plat_local_state_t local_state; 2141 2142 unsigned char level; 2143 2144 /* For indexing the psci_lock array*/ 2145 unsigned char lock_index; 2146 } non_cpu_pd_node_t; 2147 2148In order to move this data structure to normal memory, the use of each of its 2149fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2150``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2151them from coherent memory involves only doing a clean and invalidate of the 2152cache lines after these fields are written. 2153 2154The field ``local_state`` can be concurrently accessed by multiple CPUs in 2155different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2156mutual exclusion to this field and a clean and invalidate is needed after it 2157is written. 2158 2159Bakery lock data 2160~~~~~~~~~~~~~~~~ 2161 2162The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2163and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2164defined as follows: 2165 2166.. code:: c 2167 2168 typedef struct bakery_lock { 2169 /* 2170 * The lock_data is a bit-field of 2 members: 2171 * Bit[0] : choosing. This field is set when the CPU is 2172 * choosing its bakery number. 2173 * Bits[1 - 15] : number. This is the bakery number allocated. 2174 */ 2175 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2176 } bakery_lock_t; 2177 2178It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2179fields can be read by all CPUs but only written to by the owning CPU. 2180 2181Depending upon the data cache line size, the per-CPU fields of the 2182``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2183These per-CPU fields can be read and written during lock contention by multiple 2184CPUs with mismatched memory attributes. Since these fields are a part of the 2185lock implementation, they do not have access to any other locking primitive to 2186safeguard against the resulting coherency issues. As a result, simple software 2187cache maintenance is not enough to allocate them in coherent memory. Consider 2188the following example. 2189 2190CPU0 updates its per-CPU field with data cache enabled. This write updates a 2191local cache line which contains a copy of the fields for other CPUs as well. Now 2192CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2193disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2194its field in any other cache line in the system. This operation will invalidate 2195the update made by CPU0 as well. 2196 2197To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2198has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2199algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2200for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2201needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2202for other cores by using the total size allocated for the bakery_lock section 2203and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2204perform software cache maintenance on the lock data structure without running 2205into coherency issues associated with mismatched attributes. 2206 2207The bakery lock data structure ``bakery_info_t`` is defined for use when 2208``USE_COHERENT_MEM`` is disabled as follows: 2209 2210.. code:: c 2211 2212 typedef struct bakery_info { 2213 /* 2214 * The lock_data is a bit-field of 2 members: 2215 * Bit[0] : choosing. This field is set when the CPU is 2216 * choosing its bakery number. 2217 * Bits[1 - 15] : number. This is the bakery number allocated. 2218 */ 2219 volatile uint16_t lock_data; 2220 } bakery_info_t; 2221 2222The ``bakery_info_t`` represents a single per-CPU field of one lock and 2223the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2224system represents the complete bakery lock. The view in memory for a system 2225with n bakery locks are: 2226 2227:: 2228 2229 .bakery_lock section start 2230 |----------------| 2231 | `bakery_info_t`| <-- Lock_0 per-CPU field 2232 | Lock_0 | for CPU0 2233 |----------------| 2234 | `bakery_info_t`| <-- Lock_1 per-CPU field 2235 | Lock_1 | for CPU0 2236 |----------------| 2237 | .... | 2238 |----------------| 2239 | `bakery_info_t`| <-- Lock_N per-CPU field 2240 | Lock_N | for CPU0 2241 ------------------ 2242 | XXXXX | 2243 | Padding to | 2244 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2245 | Granule | continuous memory for remaining CPUs. 2246 ------------------ 2247 | `bakery_info_t`| <-- Lock_0 per-CPU field 2248 | Lock_0 | for CPU1 2249 |----------------| 2250 | `bakery_info_t`| <-- Lock_1 per-CPU field 2251 | Lock_1 | for CPU1 2252 |----------------| 2253 | .... | 2254 |----------------| 2255 | `bakery_info_t`| <-- Lock_N per-CPU field 2256 | Lock_N | for CPU1 2257 ------------------ 2258 | XXXXX | 2259 | Padding to | 2260 | next Cache WB | 2261 | Granule | 2262 ------------------ 2263 2264Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2265operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2266``.bakery_lock`` section need to be fetched and appropriate cache operations need 2267to be performed for each access. 2268 2269On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2270driver (``arm_lock``). 2271 2272Non Functional Impact of removing coherent memory 2273~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2274 2275Removal of the coherent memory region leads to the additional software overhead 2276of performing cache maintenance for the affected data structures. However, since 2277the memory where the data structures are allocated is cacheable, the overhead is 2278mostly mitigated by an increase in performance. 2279 2280There is however a performance impact for bakery locks, due to: 2281 2282- Additional cache maintenance operations, and 2283- Multiple cache line reads for each lock operation, since the bakery locks 2284 for each CPU are distributed across different cache lines. 2285 2286The implementation has been optimized to minimize this additional overhead. 2287Measurements indicate that when bakery locks are allocated in Normal memory, the 2288minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2289in Device memory the same is 2 micro seconds. The measurements were done on the 2290Juno Arm development platform. 2291 2292As mentioned earlier, almost a page of memory can be saved by disabling 2293``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2294whether coherent memory should be used. If a platform disables 2295``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2296optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2297:ref:`Porting Guide`). Refer to the reference platform code for examples. 2298 2299Isolating code and read-only data on separate memory pages 2300---------------------------------------------------------- 2301 2302In the Armv8-A VMSA, translation table entries include fields that define the 2303properties of the target memory region, such as its access permissions. The 2304smallest unit of memory that can be addressed by a translation table entry is 2305a memory page. Therefore, if software needs to set different permissions on two 2306memory regions then it needs to map them using different memory pages. 2307 2308The default memory layout for each BL image is as follows: 2309 2310:: 2311 2312 | ... | 2313 +-------------------+ 2314 | Read-write data | 2315 +-------------------+ Page boundary 2316 | <Padding> | 2317 +-------------------+ 2318 | Exception vectors | 2319 +-------------------+ 2 KB boundary 2320 | <Padding> | 2321 +-------------------+ 2322 | Read-only data | 2323 +-------------------+ 2324 | Code | 2325 +-------------------+ BLx_BASE 2326 2327.. note:: 2328 The 2KB alignment for the exception vectors is an architectural 2329 requirement. 2330 2331The read-write data start on a new memory page so that they can be mapped with 2332read-write permissions, whereas the code and read-only data below are configured 2333as read-only. 2334 2335However, the read-only data are not aligned on a page boundary. They are 2336contiguous to the code. Therefore, the end of the code section and the beginning 2337of the read-only data one might share a memory page. This forces both to be 2338mapped with the same memory attributes. As the code needs to be executable, this 2339means that the read-only data stored on the same memory page as the code are 2340executable as well. This could potentially be exploited as part of a security 2341attack. 2342 2343TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2344read-only data on separate memory pages. This in turn allows independent control 2345of the access permissions for the code and read-only data. In this case, 2346platform code gets a finer-grained view of the image layout and can 2347appropriately map the code region as executable and the read-only data as 2348execute-never. 2349 2350This has an impact on memory footprint, as padding bytes need to be introduced 2351between the code and read-only data to ensure the segregation of the two. To 2352limit the memory cost, this flag also changes the memory layout such that the 2353code and exception vectors are now contiguous, like so: 2354 2355:: 2356 2357 | ... | 2358 +-------------------+ 2359 | Read-write data | 2360 +-------------------+ Page boundary 2361 | <Padding> | 2362 +-------------------+ 2363 | Read-only data | 2364 +-------------------+ Page boundary 2365 | <Padding> | 2366 +-------------------+ 2367 | Exception vectors | 2368 +-------------------+ 2 KB boundary 2369 | <Padding> | 2370 +-------------------+ 2371 | Code | 2372 +-------------------+ BLx_BASE 2373 2374With this more condensed memory layout, the separation of read-only data will 2375add zero or one page to the memory footprint of each BL image. Each platform 2376should consider the trade-off between memory footprint and security. 2377 2378This build flag is disabled by default, minimising memory footprint. On Arm 2379platforms, it is enabled. 2380 2381Publish and Subscribe Framework 2382------------------------------- 2383 2384The Publish and Subscribe Framework allows EL3 components to define and publish 2385events, to which other EL3 components can subscribe. 2386 2387The following macros are provided by the framework: 2388 2389- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2390 the event name, which must be a valid C identifier. All calls to 2391 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2392 ``pubsub_events.h``. 2393 2394- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2395 subscribed handlers and calling them in turn. The handlers will be passed the 2396 parameter ``arg``. The expected use-case is to broadcast an event. 2397 2398- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2399 ``NULL`` is passed to subscribed handlers. 2400 2401- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2402 subscribe to ``event``. The handler will be executed whenever the ``event`` 2403 is published. 2404 2405- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2406 subscribed for ``event``. ``subscriber`` must be a local variable of type 2407 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2408 iteration. This macro can be used for those patterns that none of the 2409 ``PUBLISH_EVENT_*()`` macros cover. 2410 2411Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2412result in build error. Subscribing to an undefined event however won't. 2413 2414Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2415signature: 2416 2417.. code:: c 2418 2419 typedef void* (*pubsub_cb_t)(const void *arg); 2420 2421There may be arbitrary number of handlers registered to the same event. The 2422order in which subscribed handlers are notified when that event is published is 2423not defined. Subscribed handlers may be executed in any order; handlers should 2424not assume any relative ordering amongst them. 2425 2426Publishing an event on a PE will result in subscribed handlers executing on that 2427PE only; it won't cause handlers to execute on a different PE. 2428 2429Note that publishing an event on a PE blocks until all the subscribed handlers 2430finish executing on the PE. 2431 2432TF-A generic code publishes and subscribes to some events within. Platform 2433ports are discouraged from subscribing to them. These events may be withdrawn, 2434renamed, or have their semantics altered in the future. Platforms may however 2435register, publish, and subscribe to platform-specific events. 2436 2437Publish and Subscribe Example 2438~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2439 2440A publisher that wants to publish event ``foo`` would: 2441 2442- Define the event ``foo`` in the ``pubsub_events.h``. 2443 2444 .. code:: c 2445 2446 REGISTER_PUBSUB_EVENT(foo); 2447 2448- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2449 publish the event at the appropriate path and time of execution. 2450 2451A subscriber that wants to subscribe to event ``foo`` published above would 2452implement: 2453 2454.. code:: c 2455 2456 void *foo_handler(const void *arg) 2457 { 2458 void *result; 2459 2460 /* Do handling ... */ 2461 2462 return result; 2463 } 2464 2465 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2466 2467 2468Reclaiming the BL31 initialization code 2469~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2470 2471A significant amount of the code used for the initialization of BL31 is never 2472needed again after boot time. In order to reduce the runtime memory 2473footprint, the memory used for this code can be reclaimed after initialization 2474has finished and be used for runtime data. 2475 2476The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2477with a ``.text.init.*`` attribute which can be filtered and placed suitably 2478within the BL image for later reclamation by the platform. The platform can 2479specify the filter and the memory region for this init section in BL31 via the 2480plat.ld.S linker script. For example, on the FVP, this section is placed 2481overlapping the secondary CPU stacks so that after the cold boot is done, this 2482memory can be reclaimed for the stacks. The init memory section is initially 2483mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2484completed, the FVP changes the attributes of this section to ``RW``, 2485``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2486are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2487section section can be reclaimed for any data which is accessed after cold 2488boot initialization and it is upto the platform to make the decision. 2489 2490.. _firmware_design_pmf: 2491 2492Performance Measurement Framework 2493--------------------------------- 2494 2495The Performance Measurement Framework (PMF) facilitates collection of 2496timestamps by registered services and provides interfaces to retrieve them 2497from within TF-A. A platform can choose to expose appropriate SMCs to 2498retrieve these collected timestamps. 2499 2500By default, the global physical counter is used for the timestamp 2501value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2502timestamps captured by other CPUs. 2503 2504Timestamp identifier format 2505~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2506 2507A PMF timestamp is uniquely identified across the system via the 2508timestamp ID or ``tid``. The ``tid`` is composed as follows: 2509 2510:: 2511 2512 Bits 0-7: The local timestamp identifier. 2513 Bits 8-9: Reserved. 2514 Bits 10-15: The service identifier. 2515 Bits 16-31: Reserved. 2516 2517#. The service identifier. Each PMF service is identified by a 2518 service name and a service identifier. Both the service name and 2519 identifier are unique within the system as a whole. 2520 2521#. The local timestamp identifier. This identifier is unique within a given 2522 service. 2523 2524Registering a PMF service 2525~~~~~~~~~~~~~~~~~~~~~~~~~ 2526 2527To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2528is used. The arguments required are the service name, the service ID, 2529the total number of local timestamps to be captured and a set of flags. 2530 2531The ``flags`` field can be specified as a bitwise-OR of the following values: 2532 2533:: 2534 2535 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2536 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2537 2538The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2539timestamps in a PMF specific linker section at build time. 2540Additionally, it defines necessary functions to capture and 2541retrieve a particular timestamp for the given service at runtime. 2542 2543The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2544from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2545``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2546accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2547macro but additionally supports retrieving timestamps using SMCs. 2548 2549Capturing a timestamp 2550~~~~~~~~~~~~~~~~~~~~~ 2551 2552PMF timestamps are stored in a per-service timestamp region. On a 2553system with multiple CPUs, each timestamp is captured and stored 2554in a per-CPU cache line aligned memory region. 2555 2556Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2557used to capture a timestamp at the location where it is used. The macro 2558takes the service name, a local timestamp identifier and a flag as arguments. 2559 2560The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2561instructs PMF to do cache maintenance following the capture. Cache 2562maintenance is required if any of the service's timestamps are captured 2563with data cache disabled. 2564 2565To capture a timestamp in assembly code, the caller should use 2566``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2567calculate the address of where the timestamp would be stored. The 2568caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2569and store it at the determined address for later retrieval. 2570 2571Retrieving a timestamp 2572~~~~~~~~~~~~~~~~~~~~~~ 2573 2574From within TF-A, timestamps for individual CPUs can be retrieved using either 2575``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2576These macros accept the CPU's MPIDR value, or its ordinal position 2577respectively. 2578 2579From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2580into ``pmf_smc_handler()``. 2581 2582:: 2583 2584 Interface : pmf_smc_handler() 2585 Argument : unsigned int smc_fid, u_register_t x1, 2586 u_register_t x2, u_register_t x3, 2587 u_register_t x4, void *cookie, 2588 void *handle, u_register_t flags 2589 Return : uintptr_t 2590 2591 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2592 when the caller of the SMC is running in AArch32 mode 2593 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2594 x1: Timestamp identifier. 2595 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2596 This can be the `mpidr` of a different core to the one initiating 2597 the SMC. In that case, service specific cache maintenance may be 2598 required to ensure the updated copy of the timestamp is returned. 2599 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2600 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2601 cache invalidate before reading the timestamp. This ensures 2602 an updated copy is returned. 2603 2604The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2605in this implementation. 2606 2607PMF code structure 2608~~~~~~~~~~~~~~~~~~ 2609 2610#. ``pmf_main.c`` consists of core functions that implement service registration, 2611 initialization, storing, dumping and retrieving timestamps. 2612 2613#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2614 2615#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2616 2617#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2618 assembly code. 2619 2620#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2621 2622Armv8-A Architecture Extensions 2623------------------------------- 2624 2625TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2626section lists the usage of Architecture Extensions, and build flags 2627controlling them. 2628 2629Build options 2630~~~~~~~~~~~~~ 2631 2632``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` 2633 2634These build options serve dual purpose 2635 2636- Determine the architecture extension support in TF-A build: All the mandatory 2637 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included 2638 and unconditionally enabled by TF-A build system. 2639 2640- Passed to compiler via "-march" option to generate binary target : Tell the 2641 compiler to emit instructions upto ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` 2642 2643The build system requires that the platform provides a valid numeric value based on 2644CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. 2645Subsequent Arm Architecture versions also support extensions which were introduced 2646in previous versions. 2647 2648**TO-DO** : Its planned to decouple the two functionalities and introduce a new macro 2649for compiler usage. The requirement for this decoupling arises becasue TF-A code 2650always provides support for the latest and greatest architecture features but this 2651is not the case for the target compiler. 2652 2653.. seealso:: :ref:`Build Options` 2654 2655For details on the Architecture Extension and available features, please refer 2656to the respective Architecture Extension Supplement. 2657 2658Armv8.1-A 2659~~~~~~~~~ 2660 2661This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2662``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2663 2664- By default, a load-/store-exclusive instruction pair is used to implement 2665 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2666 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2667 Notice this instruction is only available in AArch64 execution state, so 2668 the option is only available to AArch64 builds. 2669 2670Armv8.2-A 2671~~~~~~~~~ 2672 2673- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2674 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2675 Processing Elements in the same Inner Shareable domain use the same 2676 translation table entries for a given stage of translation for a particular 2677 translation regime. 2678 2679Armv8.3-A 2680~~~~~~~~~ 2681 2682- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2683 the Non-secure world so that lower ELs are allowed to use them without 2684 causing a trap to EL3. 2685 2686 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2687 must be set to 1. This will add all pointer authentication system registers 2688 to the context that is saved when doing a world switch. 2689 2690 The TF-A itself has support for pointer authentication at runtime 2691 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2692 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2693 BL2, BL31, and the TSP if it is used. 2694 2695 Note that Pointer Authentication is enabled for Non-secure world irrespective 2696 of the value of these build flags if the CPU supports it. 2697 2698 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2699 enabling PAuth is lower because the compiler will use the optimized 2700 PAuth instructions rather than the backwards-compatible ones. 2701 2702Armv8.5-A 2703~~~~~~~~~ 2704 2705- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2706 option set to 1. This option defaults to 0. 2707 2708- Memory Tagging Extension feature is unconditionally enabled for both worlds 2709 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2710 implemented at all ELs, it is unconditionally enabled for only the normal 2711 world. To enable it for the secure world as well, the build option 2712 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2713 MTE support at all, it is always disabled, no matter what build options 2714 are used. 2715 2716Armv7-A 2717~~~~~~~ 2718 2719This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2720 2721There are several Armv7-A extensions available. Obviously the TrustZone 2722extension is mandatory to support the TF-A bootloader and runtime services. 2723 2724Platform implementing an Armv7-A system can to define from its target 2725Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2726``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2727Cortex-A15 target. 2728 2729Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2730Note that using neon at runtime has constraints on non secure world context. 2731TF-A does not yet provide VFP context management. 2732 2733Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2734the toolchain target architecture directive. 2735 2736Platform may choose to not define straight the toolchain target architecture 2737directive by defining ``MARCH32_DIRECTIVE``. 2738I.e: 2739 2740.. code:: make 2741 2742 MARCH32_DIRECTIVE := -mach=armv7-a 2743 2744Code Structure 2745-------------- 2746 2747TF-A code is logically divided between the three boot loader stages mentioned 2748in the previous sections. The code is also divided into the following 2749categories (present as directories in the source code): 2750 2751- **Platform specific.** Choice of architecture specific code depends upon 2752 the platform. 2753- **Common code.** This is platform and architecture agnostic code. 2754- **Library code.** This code comprises of functionality commonly used by all 2755 other code. The PSCI implementation and other EL3 runtime frameworks reside 2756 as Library components. 2757- **Stage specific.** Code specific to a boot stage. 2758- **Drivers.** 2759- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2760 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2761 2762Each boot loader stage uses code from one or more of the above mentioned 2763categories. Based upon the above, the code layout looks like this: 2764 2765:: 2766 2767 Directory Used by BL1? Used by BL2? Used by BL31? 2768 bl1 Yes No No 2769 bl2 No Yes No 2770 bl31 No No Yes 2771 plat Yes Yes Yes 2772 drivers Yes No Yes 2773 common Yes Yes Yes 2774 lib Yes Yes Yes 2775 services No No Yes 2776 2777The build system provides a non configurable build option IMAGE_BLx for each 2778boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2779defined by the build system. This enables TF-A to compile certain code only 2780for specific boot loader stages 2781 2782All assembler files have the ``.S`` extension. The linker source files for each 2783boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2784linker scripts which have the extension ``.ld``. 2785 2786FDTs provide a description of the hardware platform and are used by the Linux 2787kernel at boot time. These can be found in the ``fdts`` directory. 2788 2789.. rubric:: References 2790 2791- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2792 2793- `Power State Coordination Interface PDD`_ 2794 2795- `SMC Calling Convention`_ 2796 2797- :ref:`Interrupt Management Framework` 2798 2799-------------- 2800 2801*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* 2802 2803.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2804.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2805.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2806.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2807.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2808.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2809.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2810.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2811 2812.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2813
