1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 26 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 27 NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH 28workaround_reset_end neoverse_v2, ERRATUM(2331132) 29 30check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) 31 32workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 33 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 34workaround_reset_end neoverse_v2, ERRATUM(2719105) 35 36check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 37 38workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 39 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 40workaround_reset_end neoverse_v2, ERRATUM(2779510) 41 42check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 43 44workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 45 /* dsb before isb of power down sequence */ 46 dsb sy 47workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 48 49check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 50 51workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 52#if IMAGE_BL31 53 /* 54 * The Neoverse-V2 generic vectors are overridden to apply errata 55 * mitigation on exception entry from lower ELs. 56 */ 57 override_vector_table wa_cve_vbar_neoverse_v2 58#endif /* IMAGE_BL31 */ 59workaround_reset_end neoverse_v2, CVE(2022,23960) 60 61check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 62 63#if WORKAROUND_CVE_2022_23960 64 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 65#endif /* WORKAROUND_CVE_2022_23960 */ 66 67 /* ---------------------------------------------------- 68 * HW will do the cache maintenance while powering down 69 * ---------------------------------------------------- 70 */ 71func neoverse_v2_core_pwr_dwn 72 /* --------------------------------------------------- 73 * Enable CPU power down bit in power control register 74 * --------------------------------------------------- 75 */ 76 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 77 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 78 79 isb 80 ret 81endfunc neoverse_v2_core_pwr_dwn 82 83cpu_reset_func_start neoverse_v2 84 /* Disable speculative loads */ 85 msr SSBS, xzr 86cpu_reset_func_end neoverse_v2 87 88errata_report_shim neoverse_v2 89 /* --------------------------------------------- 90 * This function provides Neoverse V2- 91 * specific register information for crash 92 * reporting. It needs to return with x6 93 * pointing to a list of register names in ascii 94 * and x8 - x15 having values of registers to be 95 * reported. 96 * --------------------------------------------- 97 */ 98.section .rodata.neoverse_v2_regs, "aS" 99neoverse_v2_regs: /* The ascii list of register names to be reported */ 100 .asciz "cpuectlr_el1", "" 101 102func neoverse_v2_cpu_reg_dump 103 adr x6, neoverse_v2_regs 104 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 105 ret 106endfunc neoverse_v2_cpu_reg_dump 107 108declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 109 neoverse_v2_reset_func, \ 110 neoverse_v2_core_pwr_dwn 111