1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 26 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 27 NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH 28workaround_reset_end neoverse_v2, ERRATUM(2331132) 29 30check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) 31 32workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 33 /* dsb before isb of power down sequence */ 34 dsb sy 35workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 36 37check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 38 39workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 40#if IMAGE_BL31 41 /* 42 * The Neoverse-V2 generic vectors are overridden to apply errata 43 * mitigation on exception entry from lower ELs. 44 */ 45 override_vector_table wa_cve_vbar_neoverse_v2 46#endif /* IMAGE_BL31 */ 47workaround_reset_end neoverse_v2, CVE(2022,23960) 48 49check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 50 51#if WORKAROUND_CVE_2022_23960 52 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 53#endif /* WORKAROUND_CVE_2022_23960 */ 54 55 /* ---------------------------------------------------- 56 * HW will do the cache maintenance while powering down 57 * ---------------------------------------------------- 58 */ 59func neoverse_v2_core_pwr_dwn 60 /* --------------------------------------------------- 61 * Enable CPU power down bit in power control register 62 * --------------------------------------------------- 63 */ 64 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 65 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 66 67 isb 68 ret 69endfunc neoverse_v2_core_pwr_dwn 70 71cpu_reset_func_start neoverse_v2 72 /* Disable speculative loads */ 73 msr SSBS, xzr 74cpu_reset_func_end neoverse_v2 75 76errata_report_shim neoverse_v2 77 /* --------------------------------------------- 78 * This function provides Neoverse V2- 79 * specific register information for crash 80 * reporting. It needs to return with x6 81 * pointing to a list of register names in ascii 82 * and x8 - x15 having values of registers to be 83 * reported. 84 * --------------------------------------------- 85 */ 86.section .rodata.neoverse_v2_regs, "aS" 87neoverse_v2_regs: /* The ascii list of register names to be reported */ 88 .asciz "cpuectlr_el1", "" 89 90func neoverse_v2_cpu_reg_dump 91 adr x6, neoverse_v2_regs 92 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 93 ret 94endfunc neoverse_v2_cpu_reg_dump 95 96declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 97 neoverse_v2_reset_func, \ 98 neoverse_v2_core_pwr_dwn 99