1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `Power State Coordination Interface PDD`_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention (`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the `Arm Confidential Compute 32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management 33 Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 134 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 135 from FW_CONFIG device tree. 136 137BL1 138~~~ 139 140This stage begins execution from the platform's reset vector at EL3. The reset 141address is platform dependent but it is usually located in a Trusted ROM area. 142The BL1 data section is copied to trusted SRAM at runtime. 143 144On the Arm development platforms, BL1 code starts execution from the reset 145vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 146to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 147 148The functionality implemented by this stage is as follows. 149 150Determination of boot path 151^^^^^^^^^^^^^^^^^^^^^^^^^^ 152 153Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 154boot and a cold boot. This is done using platform-specific mechanisms (see the 155``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 156of a warm boot, a CPU is expected to continue execution from a separate 157entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 158platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 159the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 160path as described in the following sections. 161 162This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 163:ref:`CPU Reset` for more information on the effect of the 164``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 165 166Architectural initialization 167^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 168 169BL1 performs minimal architectural initialization as follows. 170 171- Exception vectors 172 173 BL1 sets up simple exception vectors for both synchronous and asynchronous 174 exceptions. The default behavior upon receiving an exception is to populate 175 a status code in the general purpose register ``X0/R0`` and call the 176 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 177 status code is one of: 178 179 For AArch64: 180 181 :: 182 183 0x0 : Synchronous exception from Current EL with SP_EL0 184 0x1 : IRQ exception from Current EL with SP_EL0 185 0x2 : FIQ exception from Current EL with SP_EL0 186 0x3 : System Error exception from Current EL with SP_EL0 187 0x4 : Synchronous exception from Current EL with SP_ELx 188 0x5 : IRQ exception from Current EL with SP_ELx 189 0x6 : FIQ exception from Current EL with SP_ELx 190 0x7 : System Error exception from Current EL with SP_ELx 191 0x8 : Synchronous exception from Lower EL using aarch64 192 0x9 : IRQ exception from Lower EL using aarch64 193 0xa : FIQ exception from Lower EL using aarch64 194 0xb : System Error exception from Lower EL using aarch64 195 0xc : Synchronous exception from Lower EL using aarch32 196 0xd : IRQ exception from Lower EL using aarch32 197 0xe : FIQ exception from Lower EL using aarch32 198 0xf : System Error exception from Lower EL using aarch32 199 200 For AArch32: 201 202 :: 203 204 0x10 : User mode 205 0x11 : FIQ mode 206 0x12 : IRQ mode 207 0x13 : SVC mode 208 0x16 : Monitor mode 209 0x17 : Abort mode 210 0x1a : Hypervisor mode 211 0x1b : Undefined mode 212 0x1f : System mode 213 214 The ``plat_report_exception()`` implementation on the Arm FVP port programs 215 the Versatile Express System LED register in the following format to 216 indicate the occurrence of an unexpected exception: 217 218 :: 219 220 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 221 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 222 For AArch32 it is always 0x0 223 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 224 of the status code 225 226 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 227 CLCD window of the FVP. 228 229 BL1 does not expect to receive any exceptions other than the SMC exception. 230 For the latter, BL1 installs a simple stub. The stub expects to receive a 231 limited set of SMC types (determined by their function IDs in the general 232 purpose register ``X0/R0``): 233 234 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 235 to EL3 Runtime Software. 236 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 237 Design Guide are supported for AArch64 only. These SMCs are currently 238 not supported when BL1 is built for AArch32. 239 240 Any other SMC leads to an assertion failure. 241 242- CPU initialization 243 244 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 245 specific reset handler function (see the section: "CPU specific operations 246 framework"). 247 248Platform initialization 249^^^^^^^^^^^^^^^^^^^^^^^ 250 251On Arm platforms, BL1 performs the following platform initializations: 252 253- Enable the Trusted Watchdog. 254- Initialize the console. 255- Configure the Interconnect to enable hardware coherency. 256- Enable the MMU and map the memory it needs to access. 257- Configure any required platform storage to load the next bootloader image 258 (BL2). 259- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 260 load it to the platform defined address and make it available to BL2 via 261 ``arg0``. 262- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 263 and NS-BL2U firmware update images. 264 265Firmware Update detection and execution 266^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 267 268After performing platform setup, BL1 common code calls 269``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 270required or to proceed with the normal boot process. If the platform code 271returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 272in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 273required and execution passes to the first image in the 274:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 275of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 276contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 277execution state of the next image. 278 279BL2 image load and execution 280^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 281 282In the normal boot flow, BL1 execution continues as follows: 283 284#. BL1 prints the following string from the primary CPU to indicate successful 285 execution of the BL1 stage: 286 287 :: 288 289 "Booting Trusted Firmware" 290 291#. BL1 loads a BL2 raw binary image from platform storage, at a 292 platform-specific base address. Prior to the load, BL1 invokes 293 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 294 use the image information. If the BL2 image file is not present or if 295 there is not enough free trusted SRAM the following error message is 296 printed: 297 298 :: 299 300 "Failed to load BL2 firmware." 301 302#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 303 for platforms to take further action after image load. This function must 304 populate the necessary arguments for BL2, which may also include the memory 305 layout. Further description of the memory layout can be found later 306 in this document. 307 308#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 309 Secure SVC mode (for AArch32), starting from its load address. 310 311BL2 312~~~ 313 314BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 315SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 316base address (more information can be found later in this document). 317The functionality implemented by BL2 is as follows. 318 319Architectural initialization 320^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 321 322For AArch64, BL2 performs the minimal architectural initialization required 323for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 324access to Floating Point and Advanced SIMD registers by setting the 325``CPACR.FPEN`` bits. 326 327For AArch32, the minimal architectural initialization required for subsequent 328stages of TF-A and normal world software is taken care of in BL1 as both BL1 329and BL2 execute at PL1. 330 331Platform initialization 332^^^^^^^^^^^^^^^^^^^^^^^ 333 334On Arm platforms, BL2 performs the following platform initializations: 335 336- Initialize the console. 337- Configure any required platform storage to allow loading further bootloader 338 images. 339- Enable the MMU and map the memory it needs to access. 340- Perform platform security setup to allow access to controlled components. 341- Reserve some memory for passing information to the next bootloader image 342 EL3 Runtime Software and populate it. 343- Define the extents of memory available for loading each subsequent 344 bootloader image. 345- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 346 then parse it. 347 348Image loading in BL2 349^^^^^^^^^^^^^^^^^^^^ 350 351BL2 generic code loads the images based on the list of loadable images 352provided by the platform. BL2 passes the list of executable images 353provided by the platform to the next handover BL image. 354 355The list of loadable images provided by the platform may also contain 356dynamic configuration files. The files are loaded and can be parsed as 357needed in the ``bl2_plat_handle_post_image_load()`` function. These 358configuration files can be passed to next Boot Loader stages as arguments 359by updating the corresponding entrypoint information in this function. 360 361SCP_BL2 (System Control Processor Firmware) image load 362^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 363 364Some systems have a separate System Control Processor (SCP) for power, clock, 365reset and system control. BL2 loads the optional SCP_BL2 image from platform 366storage into a platform-specific region of secure memory. The subsequent 367handling of SCP_BL2 is platform specific. For example, on the Juno Arm 368development platform port the image is transferred into SCP's internal memory 369using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 370memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 371for BL2 execution to continue. 372 373EL3 Runtime Software image load 374^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 375 376BL2 loads the EL3 Runtime Software image from platform storage into a platform- 377specific address in trusted SRAM. If there is not enough memory to load the 378image or image is missing it leads to an assertion failure. 379 380AArch64 BL32 (Secure-EL1 Payload) image load 381^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 382 383BL2 loads the optional BL32 image from platform storage into a platform- 384specific region of secure memory. The image executes in the secure world. BL2 385relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 386populates a platform-specific area of memory with the entrypoint/load-address 387of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 388for entry into BL32 is not determined by BL2, it is initialized by the 389Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 390managing interaction with BL32. This information is passed to BL31. 391 392BL33 (Non-trusted Firmware) image load 393^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 394 395BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 396platform storage into non-secure memory as defined by the platform. 397 398BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 399initialization is complete. Hence, BL2 populates a platform-specific area of 400memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 401normal world software image. The entrypoint is the load address of the BL33 402image. The ``SPSR`` is determined as specified in Section 5.13 of the 403`Power State Coordination Interface PDD`_. This information is passed to the 404EL3 Runtime Software. 405 406AArch64 BL31 (EL3 Runtime Software) execution 407^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 408 409BL2 execution continues as follows: 410 411#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 412 BL31 entrypoint. The exception is handled by the SMC exception handler 413 installed by BL1. 414 415#. BL1 turns off the MMU and flushes the caches. It clears the 416 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 417 and invalidates the TLBs. 418 419#. BL1 passes control to BL31 at the specified entrypoint at EL3. 420 421Running BL2 at EL3 execution level 422~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 423 424Some platforms have a non-TF-A Boot ROM that expects the next boot stage 425to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 426as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 427this waste, a special mode enables BL2 to execute at EL3, which allows 428a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 429when the build flag RESET_TO_BL2 is enabled. 430The main differences in this mode are: 431 432#. BL2 includes the reset code and the mailbox mechanism to differentiate 433 cold boot and warm boot. It runs at EL3 doing the arch 434 initialization required for EL3. 435 436#. BL2 does not receive the meminfo information from BL1 anymore. This 437 information can be passed by the Boot ROM or be internal to the 438 BL2 image. 439 440#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 441 instead of invoking the RUN_IMAGE SMC call. 442 443 444We assume 3 different types of BootROM support on the platform: 445 446#. The Boot ROM always jumps to the same address, for both cold 447 and warm boot. In this case, we will need to keep a resident part 448 of BL2 whose memory cannot be reclaimed by any other image. The 449 linker script defines the symbols __TEXT_RESIDENT_START__ and 450 __TEXT_RESIDENT_END__ that allows the platform to configure 451 correctly the memory map. 452#. The platform has some mechanism to indicate the jump address to the 453 Boot ROM. Platform code can then program the jump address with 454 psci_warmboot_entrypoint during cold boot. 455#. The platform has some mechanism to program the reset address using 456 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 457 program the reset address with psci_warmboot_entrypoint during 458 cold boot, bypassing the boot ROM for warm boot. 459 460In the last 2 cases, no part of BL2 needs to remain resident at 461runtime. In the first 2 cases, we expect the Boot ROM to be able to 462differentiate between warm and cold boot, to avoid loading BL2 again 463during warm boot. 464 465This functionality can be tested with FVP loading the image directly 466in memory and changing the address where the system jumps at reset. 467For example: 468 469 -C cluster0.cpu0.RVBAR=0x4022000 470 --data cluster0.cpu0=bl2.bin@0x4022000 471 472With this configuration, FVP is like a platform of the first case, 473where the Boot ROM jumps always to the same address. For simplification, 474BL32 is loaded in DRAM in this case, to avoid other images reclaiming 475BL2 memory. 476 477 478AArch64 BL31 479~~~~~~~~~~~~ 480 481The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 482EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 483loaded at a platform-specific base address (more information can be found later 484in this document). The functionality implemented by BL31 is as follows. 485 486Architectural initialization 487^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 488 489Currently, BL31 performs a similar architectural initialization to BL1 as 490far as system register settings are concerned. Since BL1 code resides in ROM, 491architectural initialization in BL31 allows override of any previous 492initialization done by BL1. 493 494BL31 initializes the per-CPU data framework, which provides a cache of 495frequently accessed per-CPU data optimised for fast, concurrent manipulation 496on different CPUs. This buffer includes pointers to per-CPU contexts, crash 497buffer, CPU reset and power down operations, PSCI data, platform data and so on. 498 499It then replaces the exception vectors populated by BL1 with its own. BL31 500exception vectors implement more elaborate support for handling SMCs since this 501is the only mechanism to access the runtime services implemented by BL31 (PSCI 502for example). BL31 checks each SMC for validity as specified by the 503`SMC Calling Convention`_ before passing control to the required SMC 504handler routine. 505 506BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 507counter, which is provided by the platform. 508 509Platform initialization 510^^^^^^^^^^^^^^^^^^^^^^^ 511 512BL31 performs detailed platform initialization, which enables normal world 513software to function correctly. 514 515On Arm platforms, this consists of the following: 516 517- Initialize the console. 518- Configure the Interconnect to enable hardware coherency. 519- Enable the MMU and map the memory it needs to access. 520- Initialize the generic interrupt controller. 521- Initialize the power controller device. 522- Detect the system topology. 523 524Runtime services initialization 525^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 526 527BL31 is responsible for initializing the runtime services. One of them is PSCI. 528 529As part of the PSCI initializations, BL31 detects the system topology. It also 530initializes the data structures that implement the state machine used to track 531the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 532``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 533that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 534initializes the locks that protect them. BL31 accesses the state of a CPU or 535cluster immediately after reset and before the data cache is enabled in the 536warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 537therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 538 539The runtime service framework and its initialization is described in more 540detail in the "EL3 runtime services framework" section below. 541 542Details about the status of the PSCI implementation are provided in the 543"Power State Coordination Interface" section below. 544 545AArch64 BL32 (Secure-EL1 Payload) image initialization 546^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 547 548If a BL32 image is present then there must be a matching Secure-EL1 Payload 549Dispatcher (SPD) service (see later for details). During initialization 550that service must register a function to carry out initialization of BL32 551once the runtime services are fully initialized. BL31 invokes such a 552registered function to initialize BL32 before running BL33. This initialization 553is not necessary for AArch32 SPs. 554 555Details on BL32 initialization and the SPD's role are described in the 556:ref:`firmware_design_sel1_spd` section below. 557 558BL33 (Non-trusted Firmware) execution 559^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 560 561EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 562world cold boot, ensuring that no secure state information finds its way into 563the non-secure execution state. EL3 Runtime Software uses the entrypoint 564information provided by BL2 to jump to the Non-trusted firmware image (BL33) 565at the highest available Exception Level (EL2 if available, otherwise EL1). 566 567Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 569 570Some platforms have existing implementations of Trusted Boot Firmware that 571would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 572firmware architecture it is important to provide a fully documented and stable 573interface between the Trusted Boot Firmware and BL31. 574 575Future changes to the BL31 interface will be done in a backwards compatible 576way, and this enables these firmware components to be independently enhanced/ 577updated to develop and exploit new functionality. 578 579Required CPU state when calling ``bl31_entrypoint()`` during cold boot 580^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 581 582This function must only be called by the primary CPU. 583 584On entry to this function the calling primary CPU must be executing in AArch64 585EL3, little-endian data access, and all interrupt sources masked: 586 587:: 588 589 PSTATE.EL = 3 590 PSTATE.RW = 1 591 PSTATE.DAIF = 0xf 592 SCTLR_EL3.EE = 0 593 594X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 595platform code in BL31: 596 597:: 598 599 X0 : Reserved for common TF-A information 600 X1 : Platform specific information 601 602BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 603these will be zero filled prior to invoking platform setup code. 604 605Use of the X0 and X1 parameters 606''''''''''''''''''''''''''''''' 607 608The parameters are platform specific and passed from ``bl31_entrypoint()`` to 609``bl31_early_platform_setup()``. The value of these parameters is never directly 610used by the common BL31 code. 611 612The convention is that ``X0`` conveys information regarding the BL31, BL32 and 613BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 614platform specific purpose. This convention allows platforms which use TF-A's 615BL1 and BL2 images to transfer additional platform specific information from 616Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 617pass a ``bl31_params`` structure. 618 619BL31 common and SPD initialization code depends on image and entrypoint 620information about BL33 and BL32, which is provided via BL31 platform APIs. 621This information is required until the start of execution of BL33. This 622information can be provided in a platform defined manner, e.g. compiled into 623the platform code in BL31, or provided in a platform defined memory location 624by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 625Cold boot Initialization parameters. This data may need to be cleaned out of 626the CPU caches if it is provided by an earlier boot stage and then accessed by 627BL31 platform code before the caches are enabled. 628 629TF-A's BL2 implementation passes a ``bl31_params`` structure in 630``X0`` and the Arm development platforms interpret this in the BL31 platform 631code. 632 633MMU, Data caches & Coherency 634'''''''''''''''''''''''''''' 635 636BL31 does not depend on the enabled state of the MMU, data caches or 637interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 638on entry, these should be enabled during ``bl31_plat_arch_setup()``. 639 640Data structures used in the BL31 cold boot interface 641'''''''''''''''''''''''''''''''''''''''''''''''''''' 642 643These structures are designed to support compatibility and independent 644evolution of the structures and the firmware images. For example, a version of 645BL31 that can interpret the BL3x image information from different versions of 646BL2, a platform that uses an extended entry_point_info structure to convey 647additional register information to BL31, or a ELF image loader that can convey 648more details about the firmware images. 649 650To support these scenarios the structures are versioned and sized, which enables 651BL31 to detect which information is present and respond appropriately. The 652``param_header`` is defined to capture this information: 653 654.. code:: c 655 656 typedef struct param_header { 657 uint8_t type; /* type of the structure */ 658 uint8_t version; /* version of this structure */ 659 uint16_t size; /* size of this structure in bytes */ 660 uint32_t attr; /* attributes: unused bits SBZ */ 661 } param_header_t; 662 663The structures using this format are ``entry_point_info``, ``image_info`` and 664``bl31_params``. The code that allocates and populates these structures must set 665the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 666to simplify this action. 667 668Required CPU state for BL31 Warm boot initialization 669^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 670 671When requesting a CPU power-on, or suspending a running CPU, TF-A provides 672the platform power management code with a Warm boot initialization 673entry-point, to be invoked by the CPU immediately after the reset handler. 674On entry to the Warm boot initialization function the calling CPU must be in 675AArch64 EL3, little-endian data access and all interrupt sources masked: 676 677:: 678 679 PSTATE.EL = 3 680 PSTATE.RW = 1 681 PSTATE.DAIF = 0xf 682 SCTLR_EL3.EE = 0 683 684The PSCI implementation will initialize the processor state and ensure that the 685platform power management code is then invoked as required to initialize all 686necessary system, cluster and CPU resources. 687 688AArch32 EL3 Runtime Software entrypoint interface 689~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 690 691To enable this firmware architecture it is important to provide a fully 692documented and stable interface between the Trusted Boot Firmware and the 693AArch32 EL3 Runtime Software. 694 695Future changes to the entrypoint interface will be done in a backwards 696compatible way, and this enables these firmware components to be independently 697enhanced/updated to develop and exploit new functionality. 698 699Required CPU state when entering during cold boot 700^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 701 702This function must only be called by the primary CPU. 703 704On entry to this function the calling primary CPU must be executing in AArch32 705EL3, little-endian data access, and all interrupt sources masked: 706 707:: 708 709 PSTATE.AIF = 0x7 710 SCTLR.EE = 0 711 712R0 and R1 are used to pass information from the Trusted Boot Firmware to the 713platform code in AArch32 EL3 Runtime Software: 714 715:: 716 717 R0 : Reserved for common TF-A information 718 R1 : Platform specific information 719 720Use of the R0 and R1 parameters 721''''''''''''''''''''''''''''''' 722 723The parameters are platform specific and the convention is that ``R0`` conveys 724information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 725can be used for other platform specific purpose. This convention allows 726platforms which use TF-A's BL1 and BL2 images to transfer additional platform 727specific information from Secure Boot without conflicting with future 728evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 729 730The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 731information can be obtained in a platform defined manner, e.g. compiled into 732the AArch32 EL3 Runtime Software, or provided in a platform defined memory 733location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 734via the Cold boot Initialization parameters. This data may need to be cleaned 735out of the CPU caches if it is provided by an earlier boot stage and then 736accessed by AArch32 EL3 Runtime Software before the caches are enabled. 737 738When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 739``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 740Software platform code. 741 742MMU, Data caches & Coherency 743'''''''''''''''''''''''''''' 744 745AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 746data caches or interconnect coherency in its entrypoint. They must be explicitly 747enabled if required. 748 749Data structures used in cold boot interface 750''''''''''''''''''''''''''''''''''''''''''' 751 752The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 753of ``bl31_params``. The ``bl_params`` structure is based on the convention 754described in AArch64 BL31 cold boot interface section. 755 756Required CPU state for warm boot initialization 757^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 758 759When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 760Runtime Software must ensure execution of a warm boot initialization entrypoint. 761If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 762then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 763boot entrypoint by arranging for the BL1 platform function, 764plat_get_my_entrypoint(), to return a non-zero value. 765 766In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 767data access and all interrupt sources masked: 768 769:: 770 771 PSTATE.AIF = 0x7 772 SCTLR.EE = 0 773 774The warm boot entrypoint may be implemented by using TF-A 775``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 776the pre-requisites mentioned in the 777:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 778 779EL3 runtime services framework 780------------------------------ 781 782Software executing in the non-secure state and in the secure state at exception 783levels lower than EL3 will request runtime services using the Secure Monitor 784Call (SMC) instruction. These requests will follow the convention described in 785the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 786identifiers to each SMC request and describes how arguments are passed and 787returned. 788 789The EL3 runtime services framework enables the development of services by 790different providers that can be easily integrated into final product firmware. 791The following sections describe the framework which facilitates the 792registration, initialization and use of runtime services in EL3 Runtime 793Software (BL31). 794 795The design of the runtime services depends heavily on the concepts and 796definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 797Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 798conventions. Please refer to that document for more detailed explanation of 799these terms. 800 801The following runtime services are expected to be implemented first. They have 802not all been instantiated in the current implementation. 803 804#. Standard service calls 805 806 This service is for management of the entire system. The Power State 807 Coordination Interface (`PSCI`_) is the first set of standard service calls 808 defined by Arm (see PSCI section later). 809 810#. Secure-EL1 Payload Dispatcher service 811 812 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 813 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 814 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 815 The Secure Monitor will make these world switches in response to SMCs. The 816 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 817 Application Call OEN ranges. 818 819 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 820 not defined by the `SMCCC`_ or any other standard. As a result, each 821 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 822 service - within TF-A this service is referred to as the Secure-EL1 Payload 823 Dispatcher (SPD). 824 825 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 826 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 827 :ref:`firmware_design_sel1_spd` section below. 828 829#. CPU implementation service 830 831 This service will provide an interface to CPU implementation specific 832 services for a given platform e.g. access to processor errata workarounds. 833 This service is currently unimplemented. 834 835Additional services for Arm Architecture, SiP and OEM calls can be implemented. 836Each implemented service handles a range of SMC function identifiers as 837described in the `SMCCC`_. 838 839Registration 840~~~~~~~~~~~~ 841 842A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 843the name of the service, the range of OENs covered, the type of service and 844initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 845This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 846the framework to find all service descriptors included into BL31. 847 848The specific service for a SMC Function is selected based on the OEN and call 849type of the Function ID, and the framework uses that information in the service 850descriptor to identify the handler for the SMC Call. 851 852The service descriptors do not include information to identify the precise set 853of SMC function identifiers supported by this service implementation, the 854security state from which such calls are valid nor the capability to support 85564-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 856to these aspects of a SMC call is the responsibility of the service 857implementation, the framework is focused on integration of services from 858different providers and minimizing the time taken by the framework before the 859service handler is invoked. 860 861Details of the parameters, requirements and behavior of the initialization and 862call handling functions are provided in the following sections. 863 864Initialization 865~~~~~~~~~~~~~~ 866 867``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 868framework running on the primary CPU during cold boot as part of the BL31 869initialization. This happens prior to initializing a Trusted OS and running 870Normal world boot firmware that might in turn use these services. 871Initialization involves validating each of the declared runtime service 872descriptors, calling the service initialization function and populating the 873index used for runtime lookup of the service. 874 875The BL31 linker script collects all of the declared service descriptors into a 876single array and defines symbols that allow the framework to locate and traverse 877the array, and determine its size. 878 879The framework does basic validation of each descriptor to halt firmware 880initialization if service declaration errors are detected. The framework does 881not check descriptors for the following error conditions, and may behave in an 882unpredictable manner under such scenarios: 883 884#. Overlapping OEN ranges 885#. Multiple descriptors for the same range of OENs and ``call_type`` 886#. Incorrect range of owning entity numbers for a given ``call_type`` 887 888Once validated, the service ``init()`` callback is invoked. This function carries 889out any essential EL3 initialization before servicing requests. The ``init()`` 890function is only invoked on the primary CPU during cold boot. If the service 891uses per-CPU data this must either be initialized for all CPUs during this call, 892or be done lazily when a CPU first issues an SMC call to that service. If 893``init()`` returns anything other than ``0``, this is treated as an initialization 894error and the service is ignored: this does not cause the firmware to halt. 895 896The OEN and call type fields present in the SMC Function ID cover a total of 897128 distinct services, but in practice a single descriptor can cover a range of 898OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 899service handler, the framework uses an array of 128 indices that map every 900distinct OEN/call-type combination either to one of the declared services or to 901indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 902populated for all of the OENs covered by a service after the service ``init()`` 903function has reported success. So a service that fails to initialize will never 904have it's ``handle()`` function invoked. 905 906The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 907Function ID call type and OEN onto a specific service handler in the 908``rt_svc_descs[]`` array. 909 910|Image 1| 911 912.. _handling-an-smc: 913 914Handling an SMC 915~~~~~~~~~~~~~~~ 916 917When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 918Function ID is passed in W0 from the lower exception level (as per the 919`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 920SMC Function which indicates the SMC64 calling convention: such calls are 921ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 922in R0/X0. 923 924Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 925Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 926resulting value might indicate a service that has no handler, in this case the 927framework will also report an Unknown SMC Function ID. Otherwise, the value is 928used as a further index into the ``rt_svc_descs[]`` array to locate the required 929service and handler. 930 931The service's ``handle()`` callback is provided with five of the SMC parameters 932directly, the others are saved into memory for retrieval (if needed) by the 933handler. The handler is also provided with an opaque ``handle`` for use with the 934supporting library for parameter retrieval, setting return values and context 935manipulation. The ``flags`` parameter indicates the security state of the caller 936and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 937up the execution stack for the handler, and invokes the services ``handle()`` 938function. 939 940On return from the handler the result registers are populated in X0-X7 as needed 941before restoring the stack and CPU state and returning from the original SMC. 942 943Exception Handling Framework 944---------------------------- 945 946Please refer to the :ref:`Exception Handling Framework` document. 947 948Power State Coordination Interface 949---------------------------------- 950 951TODO: Provide design walkthrough of PSCI implementation. 952 953The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 954mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 955`Power State Coordination Interface PDD`_ are implemented. The table lists 956the PSCI v1.1 APIs and their support in generic code. 957 958An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 959requires the platform to export a part of the implementation. Hence the level 960of support of the mandatory APIs depends upon the support exported by the 961platform port as well. The Juno and FVP (all variants) platforms export all the 962required support. 963 964+-----------------------------+-------------+-------------------------------+ 965| PSCI v1.1 API | Supported | Comments | 966+=============================+=============+===============================+ 967| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 968+-----------------------------+-------------+-------------------------------+ 969| ``CPU_SUSPEND`` | Yes\* | | 970+-----------------------------+-------------+-------------------------------+ 971| ``CPU_OFF`` | Yes\* | | 972+-----------------------------+-------------+-------------------------------+ 973| ``CPU_ON`` | Yes\* | | 974+-----------------------------+-------------+-------------------------------+ 975| ``AFFINITY_INFO`` | Yes | | 976+-----------------------------+-------------+-------------------------------+ 977| ``MIGRATE`` | Yes\*\* | | 978+-----------------------------+-------------+-------------------------------+ 979| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 980+-----------------------------+-------------+-------------------------------+ 981| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 982+-----------------------------+-------------+-------------------------------+ 983| ``SYSTEM_OFF`` | Yes\* | | 984+-----------------------------+-------------+-------------------------------+ 985| ``SYSTEM_RESET`` | Yes\* | | 986+-----------------------------+-------------+-------------------------------+ 987| ``PSCI_FEATURES`` | Yes | | 988+-----------------------------+-------------+-------------------------------+ 989| ``CPU_FREEZE`` | No | | 990+-----------------------------+-------------+-------------------------------+ 991| ``CPU_DEFAULT_SUSPEND`` | No | | 992+-----------------------------+-------------+-------------------------------+ 993| ``NODE_HW_STATE`` | Yes\* | | 994+-----------------------------+-------------+-------------------------------+ 995| ``SYSTEM_SUSPEND`` | Yes\* | | 996+-----------------------------+-------------+-------------------------------+ 997| ``PSCI_SET_SUSPEND_MODE`` | No | | 998+-----------------------------+-------------+-------------------------------+ 999| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1000+-----------------------------+-------------+-------------------------------+ 1001| ``PSCI_STAT_COUNT`` | Yes\* | | 1002+-----------------------------+-------------+-------------------------------+ 1003| ``SYSTEM_RESET2`` | Yes\* | | 1004+-----------------------------+-------------+-------------------------------+ 1005| ``MEM_PROTECT`` | Yes\* | | 1006+-----------------------------+-------------+-------------------------------+ 1007| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1008+-----------------------------+-------------+-------------------------------+ 1009 1010\*Note : These PSCI APIs require platform power management hooks to be 1011registered with the generic PSCI code to be supported. 1012 1013\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1014hooks to be registered with the generic PSCI code to be supported. 1015 1016The PSCI implementation in TF-A is a library which can be integrated with 1017AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1018integrating PSCI library with AArch32 EL3 Runtime Software can be found 1019at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1020 1021.. _firmware_design_sel1_spd: 1022 1023Secure-EL1 Payloads and Dispatchers 1024----------------------------------- 1025 1026On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1027the Trusted OS is coupled with a companion runtime service in the BL31 1028firmware. This service is responsible for the initialisation of the Trusted 1029OS and all communications with it. The Trusted OS is the BL32 stage of the 1030boot flow in TF-A. The firmware will attempt to locate, load and execute a 1031BL32 image. 1032 1033TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1034the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1035 1036TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1037Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1038production system using the Runtime Services Framework. On such a system, the 1039Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1040service. The TF-A build system expects that the dispatcher will define the 1041build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1042as a binary or to compile from source depending on whether the ``BL32`` build 1043option is specified or not. 1044 1045The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1046communication with the normal-world software running in EL1/EL2. Communication 1047is initiated by the normal-world software 1048 1049- either directly through a Fast SMC (as defined in the `SMCCC`_) 1050 1051- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1052 informs the TSPD about the requested power management operation. This allows 1053 the TSP to prepare for or respond to the power state change 1054 1055The TSPD service is responsible for. 1056 1057- Initializing the TSP 1058 1059- Routing requests and responses between the secure and the non-secure 1060 states during the two types of communications just described 1061 1062Initializing a BL32 Image 1063~~~~~~~~~~~~~~~~~~~~~~~~~ 1064 1065The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1066the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1067so. This is provided by: 1068 1069.. code:: c 1070 1071 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1072 1073which returns a reference to the ``entry_point_info`` structure corresponding to 1074the image which will be run in the specified security state. The SPD uses this 1075API to get entry point information for the SECURE image, BL32. 1076 1077In the absence of a BL32 image, BL31 passes control to the normal world 1078bootloader image (BL33). When the BL32 image is present, it is typical 1079that the SPD wants control to be passed to BL32 first and then later to BL33. 1080 1081To do this the SPD has to register a BL32 initialization function during 1082initialization of the SPD service. The BL32 initialization function has this 1083prototype: 1084 1085.. code:: c 1086 1087 int32_t init(void); 1088 1089and is registered using the ``bl31_register_bl32_init()`` function. 1090 1091TF-A supports two approaches for the SPD to pass control to BL32 before 1092returning through EL3 and running the non-trusted firmware (BL33): 1093 1094#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1095 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1096 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1097 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1098 1099 When the BL32 has completed initialization at Secure-EL1, it returns to 1100 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1101 receipt of this SMC, the SPD service handler should switch the CPU context 1102 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1103 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1104 the normal world firmware BL33. On return from the handler the framework 1105 will exit to EL2 and run BL33. 1106 1107#. The BL32 setup function registers an initialization function using 1108 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1109 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1110 entrypoint. 1111 1112 .. note:: 1113 The Test SPD service included with TF-A provides one implementation 1114 of such a mechanism. 1115 1116 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1117 SPD service handler invokes the synchronous call return mechanism to return 1118 to the BL32 initialization function. On return from this function, 1119 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1120 continue the boot process in the normal world. 1121 1122Crash Reporting in BL31 1123----------------------- 1124 1125BL31 implements a scheme for reporting the processor state when an unhandled 1126exception is encountered. The reporting mechanism attempts to preserve all the 1127register contents and report it via a dedicated UART (PL011 console). BL31 1128reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1129 1130A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1131the per-CPU pointer cache. The implementation attempts to minimise the memory 1132required for this feature. The file ``crash_reporting.S`` contains the 1133implementation for crash reporting. 1134 1135The sample crash output is shown below. 1136 1137:: 1138 1139 x0 = 0x000000002a4a0000 1140 x1 = 0x0000000000000001 1141 x2 = 0x0000000000000002 1142 x3 = 0x0000000000000003 1143 x4 = 0x0000000000000004 1144 x5 = 0x0000000000000005 1145 x6 = 0x0000000000000006 1146 x7 = 0x0000000000000007 1147 x8 = 0x0000000000000008 1148 x9 = 0x0000000000000009 1149 x10 = 0x0000000000000010 1150 x11 = 0x0000000000000011 1151 x12 = 0x0000000000000012 1152 x13 = 0x0000000000000013 1153 x14 = 0x0000000000000014 1154 x15 = 0x0000000000000015 1155 x16 = 0x0000000000000016 1156 x17 = 0x0000000000000017 1157 x18 = 0x0000000000000018 1158 x19 = 0x0000000000000019 1159 x20 = 0x0000000000000020 1160 x21 = 0x0000000000000021 1161 x22 = 0x0000000000000022 1162 x23 = 0x0000000000000023 1163 x24 = 0x0000000000000024 1164 x25 = 0x0000000000000025 1165 x26 = 0x0000000000000026 1166 x27 = 0x0000000000000027 1167 x28 = 0x0000000000000028 1168 x29 = 0x0000000000000029 1169 x30 = 0x0000000088000b78 1170 scr_el3 = 0x000000000003073d 1171 sctlr_el3 = 0x00000000b0cd183f 1172 cptr_el3 = 0x0000000000000000 1173 tcr_el3 = 0x000000008080351c 1174 daif = 0x00000000000002c0 1175 mair_el3 = 0x00000000004404ff 1176 spsr_el3 = 0x0000000060000349 1177 elr_el3 = 0x0000000088000114 1178 ttbr0_el3 = 0x0000000004018201 1179 esr_el3 = 0x00000000be000000 1180 far_el3 = 0x0000000000000000 1181 spsr_el1 = 0x0000000000000000 1182 elr_el1 = 0x0000000000000000 1183 spsr_abt = 0x0000000000000000 1184 spsr_und = 0x0000000000000000 1185 spsr_irq = 0x0000000000000000 1186 spsr_fiq = 0x0000000000000000 1187 sctlr_el1 = 0x0000000030d00800 1188 actlr_el1 = 0x0000000000000000 1189 cpacr_el1 = 0x0000000000000000 1190 csselr_el1 = 0x0000000000000000 1191 sp_el1 = 0x0000000000000000 1192 esr_el1 = 0x0000000000000000 1193 ttbr0_el1 = 0x0000000000000000 1194 ttbr1_el1 = 0x0000000000000000 1195 mair_el1 = 0x0000000000000000 1196 amair_el1 = 0x0000000000000000 1197 tcr_el1 = 0x0000000000000000 1198 tpidr_el1 = 0x0000000000000000 1199 tpidr_el0 = 0x0000000000000000 1200 tpidrro_el0 = 0x0000000000000000 1201 par_el1 = 0x0000000000000000 1202 mpidr_el1 = 0x0000000080000000 1203 afsr0_el1 = 0x0000000000000000 1204 afsr1_el1 = 0x0000000000000000 1205 contextidr_el1 = 0x0000000000000000 1206 vbar_el1 = 0x0000000000000000 1207 cntp_ctl_el0 = 0x0000000000000000 1208 cntp_cval_el0 = 0x0000000000000000 1209 cntv_ctl_el0 = 0x0000000000000000 1210 cntv_cval_el0 = 0x0000000000000000 1211 cntkctl_el1 = 0x0000000000000000 1212 sp_el0 = 0x0000000004014940 1213 isr_el1 = 0x0000000000000000 1214 dacr32_el2 = 0x0000000000000000 1215 ifsr32_el2 = 0x0000000000000000 1216 icc_hppir0_el1 = 0x00000000000003ff 1217 icc_hppir1_el1 = 0x00000000000003ff 1218 icc_ctlr_el3 = 0x0000000000080400 1219 gicd_ispendr regs (Offsets 0x200-0x278) 1220 Offset Value 1221 0x200: 0x0000000000000000 1222 0x208: 0x0000000000000000 1223 0x210: 0x0000000000000000 1224 0x218: 0x0000000000000000 1225 0x220: 0x0000000000000000 1226 0x228: 0x0000000000000000 1227 0x230: 0x0000000000000000 1228 0x238: 0x0000000000000000 1229 0x240: 0x0000000000000000 1230 0x248: 0x0000000000000000 1231 0x250: 0x0000000000000000 1232 0x258: 0x0000000000000000 1233 0x260: 0x0000000000000000 1234 0x268: 0x0000000000000000 1235 0x270: 0x0000000000000000 1236 0x278: 0x0000000000000000 1237 1238Guidelines for Reset Handlers 1239----------------------------- 1240 1241TF-A implements a framework that allows CPU and platform ports to perform 1242actions very early after a CPU is released from reset in both the cold and warm 1243boot paths. This is done by calling the ``reset_handler()`` function in both 1244the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1245handling functions. 1246 1247Details for implementing a CPU specific reset handler can be found in 1248Section 8. Details for implementing a platform specific reset handler can be 1249found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). 1250 1251When adding functionality to a reset handler, keep in mind that if a different 1252reset handling behavior is required between the first and the subsequent 1253invocations of the reset handling code, this should be detected at runtime. 1254In other words, the reset handler should be able to detect whether an action has 1255already been performed and act as appropriate. Possible courses of actions are, 1256e.g. skip the action the second time, or undo/redo it. 1257 1258.. _configuring-secure-interrupts: 1259 1260Configuring secure interrupts 1261----------------------------- 1262 1263The GIC driver is responsible for performing initial configuration of secure 1264interrupts on the platform. To this end, the platform is expected to provide the 1265GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1266interrupt configuration during the driver initialisation. 1267 1268Secure interrupt configuration are specified in an array of secure interrupt 1269properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1270``interrupt_props`` member points to an array of interrupt properties. Each 1271element of the array specifies the interrupt number and its attributes 1272(priority, group, configuration). Each element of the array shall be populated 1273by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1274 1275- 13-bit interrupt number, 1276 1277- 8-bit interrupt priority, 1278 1279- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1280 ``INTR_TYPE_NS``), 1281 1282- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1283 ``GIC_INTR_CFG_EDGE``). 1284 1285.. _firmware_design_cpu_ops_fwk: 1286 1287CPU specific operations framework 1288--------------------------------- 1289 1290Certain aspects of the Armv8-A architecture are implementation defined, 1291that is, certain behaviours are not architecturally defined, but must be 1292defined and documented by individual processor implementations. TF-A 1293implements a framework which categorises the common implementation defined 1294behaviours and allows a processor to export its implementation of that 1295behaviour. The categories are: 1296 1297#. Processor specific reset sequence. 1298 1299#. Processor specific power down sequences. 1300 1301#. Processor specific register dumping as a part of crash reporting. 1302 1303#. Errata status reporting. 1304 1305Each of the above categories fulfils a different requirement. 1306 1307#. allows any processor specific initialization before the caches and MMU 1308 are turned on, like implementation of errata workarounds, entry into 1309 the intra-cluster coherency domain etc. 1310 1311#. allows each processor to implement the power down sequence mandated in 1312 its Technical Reference Manual (TRM). 1313 1314#. allows a processor to provide additional information to the developer 1315 in the event of a crash, for example Cortex-A53 has registers which 1316 can expose the data cache contents. 1317 1318#. allows a processor to define a function that inspects and reports the status 1319 of all errata workarounds on that processor. 1320 1321Please note that only 2. is mandated by the TRM. 1322 1323The CPU specific operations framework scales to accommodate a large number of 1324different CPUs during power down and reset handling. The platform can specify 1325any CPU optimization it wants to enable for each CPU. It can also specify 1326the CPU errata workarounds to be applied for each CPU type during reset 1327handling by defining CPU errata compile time macros. Details on these macros 1328can be found in the :ref:`Arm CPU Specific Build Macros` document. 1329 1330The CPU specific operations framework depends on the ``cpu_ops`` structure which 1331needs to be exported for each type of CPU in the platform. It is defined in 1332``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1333``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1334``cpu_reg_dump()``. 1335 1336The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1337suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1338exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1339configuration, these CPU specific files must be included in the build by 1340the platform makefile. The generic CPU specific operations framework code exists 1341in ``lib/cpus/aarch64/cpu_helpers.S``. 1342 1343CPU specific Reset Handling 1344~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1345 1346After a reset, the state of the CPU when it calls generic reset handler is: 1347MMU turned off, both instruction and data caches turned off and not part 1348of any coherency domain. 1349 1350The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1351the platform to perform any system initialization required and any system 1352errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1353the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1354array and returns it. Note that only the part number and implementer fields 1355in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1356the returned ``cpu_ops`` is then invoked which executes the required reset 1357handling for that CPU and also any errata workarounds enabled by the platform. 1358This function must preserve the values of general purpose registers x20 to x29. 1359 1360Refer to Section "Guidelines for Reset Handlers" for general guidelines 1361regarding placement of code in a reset handler. 1362 1363CPU specific power down sequence 1364~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1365 1366During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1367entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1368retrieved during power down sequences. 1369 1370Various CPU drivers register handlers to perform power down at certain power 1371levels for that specific CPU. The PSCI service, upon receiving a power down 1372request, determines the highest power level at which to execute power down 1373sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1374pick the right power down handler for the requested level. The function 1375retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1376retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1377requested power level is higher than what a CPU driver supports, the handler 1378registered for highest level is invoked. 1379 1380At runtime the platform hooks for power down are invoked by the PSCI service to 1381perform platform specific operations during a power down sequence, for example 1382turning off CCI coherency during a cluster power down. 1383 1384CPU specific register reporting during crash 1385~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1386 1387If the crash reporting is enabled in BL31, when a crash occurs, the crash 1388reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1389``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1390``cpu_ops`` is invoked, which then returns the CPU specific register values to 1391be reported and a pointer to the ASCII list of register names in a format 1392expected by the crash reporting framework. 1393 1394.. _firmware_design_cpu_errata_reporting: 1395 1396CPU errata status reporting 1397~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1398 1399Errata workarounds for CPUs supported in TF-A are applied during both cold and 1400warm boots, shortly after reset. Individual Errata workarounds are enabled as 1401build options. Some errata workarounds have potential run-time implications; 1402therefore some are enabled by default, others not. Platform ports shall 1403override build options to enable or disable errata as appropriate. The CPU 1404drivers take care of applying errata workarounds that are enabled and applicable 1405to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more 1406information. 1407 1408Functions in CPU drivers that apply errata workaround must follow the 1409conventions listed below. 1410 1411The errata workaround must be authored as two separate functions: 1412 1413- One that checks for errata. This function must determine whether that errata 1414 applies to the current CPU. Typically this involves matching the current 1415 CPUs revision and variant against a value that's known to be affected by the 1416 errata. If the function determines that the errata applies to this CPU, it 1417 must return ``ERRATA_APPLIES``; otherwise, it must return 1418 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1419 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1420 1421For an errata identified as ``E``, the check function must be named 1422``check_errata_E``. 1423 1424This function will be invoked at different times, both from assembly and from 1425C run time. Therefore it must follow AAPCS, and must not use stack. 1426 1427- Another one that applies the errata workaround. This function would call the 1428 check function described above, and applies errata workaround if required. 1429 1430CPU drivers that apply errata workaround can optionally implement an assembly 1431function that report the status of errata workarounds pertaining to that CPU. 1432For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1433macro, the errata reporting function, if it exists, must be named 1434``cpux_errata_report``. This function will always be called with MMU enabled; it 1435must follow AAPCS and may use stack. 1436 1437In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1438runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1439status reporting function, if one exists, for that type of CPU. 1440 1441To report the status of each errata workaround, the function shall use the 1442assembler macro ``report_errata``, passing it: 1443 1444- The build option that enables the errata; 1445 1446- The name of the CPU: this must be the same identifier that CPU driver 1447 registered itself with, using ``declare_cpu_ops``; 1448 1449- And the errata identifier: the identifier must match what's used in the 1450 errata's check function described above. 1451 1452The errata status reporting function will be called once per CPU type/errata 1453combination during the software's active life time. 1454 1455It's expected that whenever an errata workaround is submitted to TF-A, the 1456errata reporting function is appropriately extended to report its status as 1457well. 1458 1459Reporting the status of errata workaround is for informational purpose only; it 1460has no functional significance. 1461 1462Memory layout of BL images 1463-------------------------- 1464 1465Each bootloader image can be divided in 2 parts: 1466 1467- the static contents of the image. These are data actually stored in the 1468 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1469 sections; 1470 1471- the run-time contents of the image. These are data that don't occupy any 1472 space in the binary on the disk. The ELF binary just contains some 1473 metadata indicating where these data will be stored at run-time and the 1474 corresponding sections need to be allocated and initialized at run-time. 1475 In the ELF terminology, they are called ``NOBITS`` sections. 1476 1477All PROGBITS sections are grouped together at the beginning of the image, 1478followed by all NOBITS sections. This is true for all TF-A images and it is 1479governed by the linker scripts. This ensures that the raw binary images are 1480as small as possible. If a NOBITS section was inserted in between PROGBITS 1481sections then the resulting binary file would contain zero bytes in place of 1482this NOBITS section, making the image unnecessarily bigger. Smaller images 1483allow faster loading from the FIP to the main memory. 1484 1485For BL31, a platform can specify an alternate location for NOBITS sections 1486(other than immediately following PROGBITS sections) by setting 1487``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1488``BL31_NOBITS_LIMIT``. 1489 1490Linker scripts and symbols 1491~~~~~~~~~~~~~~~~~~~~~~~~~~ 1492 1493Each bootloader stage image layout is described by its own linker script. The 1494linker scripts export some symbols into the program symbol table. Their values 1495correspond to particular addresses. TF-A code can refer to these symbols to 1496figure out the image memory layout. 1497 1498Linker symbols follow the following naming convention in TF-A. 1499 1500- ``__<SECTION>_START__`` 1501 1502 Start address of a given section named ``<SECTION>``. 1503 1504- ``__<SECTION>_END__`` 1505 1506 End address of a given section named ``<SECTION>``. If there is an alignment 1507 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1508 to the end address of the section's actual contents, rounded up to the right 1509 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1510 actual end address of the section's contents. 1511 1512- ``__<SECTION>_UNALIGNED_END__`` 1513 1514 End address of a given section named ``<SECTION>`` without any padding or 1515 rounding up due to some alignment constraint. 1516 1517- ``__<SECTION>_SIZE__`` 1518 1519 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1520 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1521 corresponds to the size of the section's actual contents, rounded up to the 1522 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1523 to know the actual size of the section's contents. 1524 1525- ``__<SECTION>_UNALIGNED_SIZE__`` 1526 1527 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1528 rounding up due to some alignment constraint. In other words, 1529 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1530 1531Some of the linker symbols are mandatory as TF-A code relies on them to be 1532defined. They are listed in the following subsections. Some of them must be 1533provided for each bootloader stage and some are specific to a given bootloader 1534stage. 1535 1536The linker scripts define some extra, optional symbols. They are not actually 1537used by any code but they help in understanding the bootloader images' memory 1538layout as they are easy to spot in the link map files. 1539 1540Common linker symbols 1541^^^^^^^^^^^^^^^^^^^^^ 1542 1543All BL images share the following requirements: 1544 1545- The BSS section must be zero-initialised before executing any C code. 1546- The coherent memory section (if enabled) must be zero-initialised as well. 1547- The MMU setup code needs to know the extents of the coherent and read-only 1548 memory regions to set the right memory attributes. When 1549 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1550 read-only memory region is divided between code and data. 1551 1552The following linker symbols are defined for this purpose: 1553 1554- ``__BSS_START__`` 1555- ``__BSS_SIZE__`` 1556- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1557- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1558- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1559- ``__RO_START__`` 1560- ``__RO_END__`` 1561- ``__TEXT_START__`` 1562- ``__TEXT_END_UNALIGNED__`` 1563- ``__TEXT_END__`` 1564- ``__RODATA_START__`` 1565- ``__RODATA_END_UNALIGNED__`` 1566- ``__RODATA_END__`` 1567 1568BL1's linker symbols 1569^^^^^^^^^^^^^^^^^^^^ 1570 1571BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1572it is entirely executed in place but it needs some read-write memory for its 1573mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1574relocated from ROM to RAM before executing any C code. 1575 1576The following additional linker symbols are defined for BL1: 1577 1578- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1579 and ``.data`` section in ROM. 1580- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1581 aligned on a 16-byte boundary. 1582- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1583 copied over. Must be aligned on a 16-byte boundary. 1584- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1585- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1586- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1587 1588How to choose the right base addresses for each bootloader stage image 1589~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1590 1591There is currently no support for dynamic image loading in TF-A. This means 1592that all bootloader images need to be linked against their ultimate runtime 1593locations and the base addresses of each image must be chosen carefully such 1594that images don't overlap each other in an undesired way. As the code grows, 1595the base addresses might need adjustments to cope with the new memory layout. 1596 1597The memory layout is completely specific to the platform and so there is no 1598general recipe for choosing the right base addresses for each bootloader image. 1599However, there are tools to aid in understanding the memory layout. These are 1600the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1601being the stage bootloader. They provide a detailed view of the memory usage of 1602each image. Among other useful information, they provide the end address of 1603each image. 1604 1605- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1606- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1607- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1608- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1609 1610For each bootloader image, the platform code must provide its start address 1611as well as a limit address that it must not overstep. The latter is used in the 1612linker scripts to check that the image doesn't grow past that address. If that 1613happens, the linker will issue a message similar to the following: 1614 1615:: 1616 1617 aarch64-none-elf-ld: BLx has exceeded its limit. 1618 1619Additionally, if the platform memory layout implies some image overlaying like 1620on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1621sections must not overstep. The platform code must provide those. 1622 1623TF-A does not provide any mechanism to verify at boot time that the memory 1624to load a new image is free to prevent overwriting a previously loaded image. 1625The platform must specify the memory available in the system for all the 1626relevant BL images to be loaded. 1627 1628For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1629return the region defined by the platform where BL1 intends to load BL2. The 1630``load_image()`` function performs bounds check for the image size based on the 1631base and maximum image size provided by the platforms. Platforms must take 1632this behaviour into account when defining the base/size for each of the images. 1633 1634Memory layout on Arm development platforms 1635^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1636 1637The following list describes the memory layout on the Arm development platforms: 1638 1639- A 4KB page of shared memory is used for communication between Trusted 1640 Firmware and the platform's power controller. This is located at the base of 1641 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1642 images is reduced by the size of the shared memory. 1643 1644 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1645 this is also used for the MHU payload when passing messages to and from the 1646 SCP. 1647 1648- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1649 and also the dynamic firmware configurations. 1650 1651- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1652 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1653 data are relocated to the top of Trusted SRAM at runtime. 1654 1655- BL2 is loaded below BL1 RW 1656 1657- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1658 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1659 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1660 remain valid only until execution reaches the EL3 Runtime Software entry 1661 point during a cold boot. 1662 1663- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1664 region and transferred to the SCP before being overwritten by EL3 Runtime 1665 Software. 1666 1667- BL32 (for AArch64) can be loaded in one of the following locations: 1668 1669 - Trusted SRAM 1670 - Trusted DRAM (FVP only) 1671 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1672 controller) 1673 1674 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1675 BL31. 1676 1677The location of the BL32 image will result in different memory maps. This is 1678illustrated for both FVP and Juno in the following diagrams, using the TSP as 1679an example. 1680 1681.. note:: 1682 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1683 layout of the other images in Trusted SRAM. 1684 1685CONFIG section in memory layouts shown below contains: 1686 1687:: 1688 1689 +--------------------+ 1690 |bl2_mem_params_descs| 1691 |--------------------| 1692 | fw_configs | 1693 +--------------------+ 1694 1695``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1696BL image during boot. 1697 1698``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1699 1700**FVP with TSP in Trusted SRAM with firmware configs :** 1701(These diagrams only cover the AArch64 case) 1702 1703:: 1704 1705 DRAM 1706 0xffffffff +----------+ 1707 | EL3 TZC | 1708 0xffe00000 |----------| (secure) 1709 | AP TZC | 1710 0xff000000 +----------+ 1711 : : 1712 0x82100000 |----------| 1713 |HW_CONFIG | 1714 0x82000000 |----------| (non-secure) 1715 | | 1716 0x80000000 +----------+ 1717 1718 Trusted DRAM 1719 0x08000000 +----------+ 1720 |HW_CONFIG | 1721 0x07f00000 |----------| 1722 : : 1723 | | 1724 0x06000000 +----------+ 1725 1726 Trusted SRAM 1727 0x04040000 +----------+ loaded by BL2 +----------------+ 1728 | BL1 (rw) | <<<<<<<<<<<<< | | 1729 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1730 | BL2 | <<<<<<<<<<<<< | | 1731 |----------| <<<<<<<<<<<<< |----------------| 1732 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1733 | | <<<<<<<<<<<<< |----------------| 1734 | | <<<<<<<<<<<<< | BL32 | 1735 0x04003000 +----------+ +----------------+ 1736 | CONFIG | 1737 0x04001000 +----------+ 1738 | Shared | 1739 0x04000000 +----------+ 1740 1741 Trusted ROM 1742 0x04000000 +----------+ 1743 | BL1 (ro) | 1744 0x00000000 +----------+ 1745 1746**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1747 1748:: 1749 1750 DRAM 1751 0xffffffff +--------------+ 1752 | EL3 TZC | 1753 0xffe00000 |--------------| (secure) 1754 | AP TZC | 1755 0xff000000 +--------------+ 1756 : : 1757 0x82100000 |--------------| 1758 | HW_CONFIG | 1759 0x82000000 |--------------| (non-secure) 1760 | | 1761 0x80000000 +--------------+ 1762 1763 Trusted DRAM 1764 0x08000000 +--------------+ 1765 | HW_CONFIG | 1766 0x07f00000 |--------------| 1767 : : 1768 | BL32 | 1769 0x06000000 +--------------+ 1770 1771 Trusted SRAM 1772 0x04040000 +--------------+ loaded by BL2 +----------------+ 1773 | BL1 (rw) | <<<<<<<<<<<<< | | 1774 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1775 | BL2 | <<<<<<<<<<<<< | | 1776 |--------------| <<<<<<<<<<<<< |----------------| 1777 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1778 | | +----------------+ 1779 0x04003000 +--------------+ 1780 | CONFIG | 1781 0x04001000 +--------------+ 1782 | Shared | 1783 0x04000000 +--------------+ 1784 1785 Trusted ROM 1786 0x04000000 +--------------+ 1787 | BL1 (ro) | 1788 0x00000000 +--------------+ 1789 1790**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1791 1792:: 1793 1794 DRAM 1795 0xffffffff +----------+ 1796 | EL3 TZC | 1797 0xffe00000 |----------| (secure) 1798 | AP TZC | 1799 | (BL32) | 1800 0xff000000 +----------+ 1801 | | 1802 0x82100000 |----------| 1803 |HW_CONFIG | 1804 0x82000000 |----------| (non-secure) 1805 | | 1806 0x80000000 +----------+ 1807 1808 Trusted DRAM 1809 0x08000000 +----------+ 1810 |HW_CONFIG | 1811 0x7f000000 |----------| 1812 : : 1813 | | 1814 0x06000000 +----------+ 1815 1816 Trusted SRAM 1817 0x04040000 +----------+ loaded by BL2 +----------------+ 1818 | BL1 (rw) | <<<<<<<<<<<<< | | 1819 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1820 | BL2 | <<<<<<<<<<<<< | | 1821 |----------| <<<<<<<<<<<<< |----------------| 1822 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1823 | | +----------------+ 1824 0x04003000 +----------+ 1825 | CONFIG | 1826 0x04001000 +----------+ 1827 | Shared | 1828 0x04000000 +----------+ 1829 1830 Trusted ROM 1831 0x04000000 +----------+ 1832 | BL1 (ro) | 1833 0x00000000 +----------+ 1834 1835**Juno with BL32 in Trusted SRAM :** 1836 1837:: 1838 1839 DRAM 1840 0xFFFFFFFF +----------+ 1841 | SCP TZC | 1842 0xFFE00000 |----------| 1843 | EL3 TZC | 1844 0xFFC00000 |----------| (secure) 1845 | AP TZC | 1846 0xFF000000 +----------+ 1847 | | 1848 : : (non-secure) 1849 | | 1850 0x80000000 +----------+ 1851 1852 1853 Flash0 1854 0x0C000000 +----------+ 1855 : : 1856 0x0BED0000 |----------| 1857 | BL1 (ro) | 1858 0x0BEC0000 |----------| 1859 : : 1860 0x08000000 +----------+ BL31 is loaded 1861 after SCP_BL2 has 1862 Trusted SRAM been sent to SCP 1863 0x04040000 +----------+ loaded by BL2 +----------------+ 1864 | BL1 (rw) | <<<<<<<<<<<<< | | 1865 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1866 | BL2 | <<<<<<<<<<<<< | | 1867 |----------| <<<<<<<<<<<<< |----------------| 1868 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1869 | | <<<<<<<<<<<<< |----------------| 1870 | | <<<<<<<<<<<<< | BL32 | 1871 | | +----------------+ 1872 | | 1873 0x04001000 +----------+ 1874 | MHU | 1875 0x04000000 +----------+ 1876 1877**Juno with BL32 in TZC-secured DRAM :** 1878 1879:: 1880 1881 DRAM 1882 0xFFFFFFFF +----------+ 1883 | SCP TZC | 1884 0xFFE00000 |----------| 1885 | EL3 TZC | 1886 0xFFC00000 |----------| (secure) 1887 | AP TZC | 1888 | (BL32) | 1889 0xFF000000 +----------+ 1890 | | 1891 : : (non-secure) 1892 | | 1893 0x80000000 +----------+ 1894 1895 Flash0 1896 0x0C000000 +----------+ 1897 : : 1898 0x0BED0000 |----------| 1899 | BL1 (ro) | 1900 0x0BEC0000 |----------| 1901 : : 1902 0x08000000 +----------+ BL31 is loaded 1903 after SCP_BL2 has 1904 Trusted SRAM been sent to SCP 1905 0x04040000 +----------+ loaded by BL2 +----------------+ 1906 | BL1 (rw) | <<<<<<<<<<<<< | | 1907 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1908 | BL2 | <<<<<<<<<<<<< | | 1909 |----------| <<<<<<<<<<<<< |----------------| 1910 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1911 | | +----------------+ 1912 0x04001000 +----------+ 1913 | MHU | 1914 0x04000000 +----------+ 1915 1916.. _firmware_design_fip: 1917 1918Firmware Image Package (FIP) 1919---------------------------- 1920 1921Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1922potentially other payloads) into a single archive that can be loaded by TF-A 1923from non-volatile platform storage. A driver to load images from a FIP has 1924been added to the storage layer and allows a package to be read from supported 1925platform storage. A tool to create Firmware Image Packages is also provided 1926and described below. 1927 1928Firmware Image Package layout 1929~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1930 1931The FIP layout consists of a table of contents (ToC) followed by payload data. 1932The ToC itself has a header followed by one or more table entries. The ToC is 1933terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1934the offset equals the total size of the FIP file. All ToC entries describe some 1935payload data that has been appended to the end of the binary package. With the 1936information provided in the ToC entry the corresponding payload data can be 1937retrieved. 1938 1939:: 1940 1941 ------------------ 1942 | ToC Header | 1943 |----------------| 1944 | ToC Entry 0 | 1945 |----------------| 1946 | ToC Entry 1 | 1947 |----------------| 1948 | ToC End Marker | 1949 |----------------| 1950 | | 1951 | Data 0 | 1952 | | 1953 |----------------| 1954 | | 1955 | Data 1 | 1956 | | 1957 ------------------ 1958 1959The ToC header and entry formats are described in the header file 1960``include/tools_share/firmware_image_package.h``. This file is used by both the 1961tool and TF-A. 1962 1963The ToC header has the following fields: 1964 1965:: 1966 1967 `name`: The name of the ToC. This is currently used to validate the header. 1968 `serial_number`: A non-zero number provided by the creation tool 1969 `flags`: Flags associated with this data. 1970 Bits 0-31: Reserved 1971 Bits 32-47: Platform defined 1972 Bits 48-63: Reserved 1973 1974A ToC entry has the following fields: 1975 1976:: 1977 1978 `uuid`: All files are referred to by a pre-defined Universally Unique 1979 IDentifier [UUID] . The UUIDs are defined in 1980 `include/tools_share/firmware_image_package.h`. The platform translates 1981 the requested image name into the corresponding UUID when accessing the 1982 package. 1983 `offset_address`: The offset address at which the corresponding payload data 1984 can be found. The offset is calculated from the ToC base address. 1985 `size`: The size of the corresponding payload data in bytes. 1986 `flags`: Flags associated with this entry. None are yet defined. 1987 1988Firmware Image Package creation tool 1989~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1990 1991The FIP creation tool can be used to pack specified images into a binary 1992package that can be loaded by TF-A from platform storage. The tool currently 1993only supports packing bootloader images. Additional image definitions can be 1994added to the tool as required. 1995 1996The tool can be found in ``tools/fiptool``. 1997 1998Loading from a Firmware Image Package (FIP) 1999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2000 2001The Firmware Image Package (FIP) driver can load images from a binary package on 2002non-volatile platform storage. For the Arm development platforms, this is 2003currently NOR FLASH. 2004 2005Bootloader images are loaded according to the platform policy as specified by 2006the function ``plat_get_image_source()``. For the Arm development platforms, this 2007means the platform will attempt to load images from a Firmware Image Package 2008located at the start of NOR FLASH0. 2009 2010The Arm development platforms' policy is to only allow loading of a known set of 2011images. The platform policy can be modified to allow additional images. 2012 2013Use of coherent memory in TF-A 2014------------------------------ 2015 2016There might be loss of coherency when physical memory with mismatched 2017shareability, cacheability and memory attributes is accessed by multiple CPUs 2018(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2019in TF-A during power up/down sequences when coherency, MMU and caches are 2020turned on/off incrementally. 2021 2022TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2023in the translation tables. The translation granule size in TF-A is 4KB. This 2024is the smallest possible size of the coherent memory region. 2025 2026By default, all data structures which are susceptible to accesses with 2027mismatched attributes from various CPUs are allocated in a coherent memory 2028region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2029region accesses are Outer Shareable, non-cacheable and they can be accessed with 2030the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2031at least an extra page of memory, TF-A is able to work around coherency issues 2032due to mismatched memory attributes. 2033 2034The alternative to the above approach is to allocate the susceptible data 2035structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2036approach requires the data structures to be designed so that it is possible to 2037work around the issue of mismatched memory attributes by performing software 2038cache maintenance on them. 2039 2040Disabling the use of coherent memory in TF-A 2041~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2042 2043It might be desirable to avoid the cost of allocating coherent memory on 2044platforms which are memory constrained. TF-A enables inclusion of coherent 2045memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2046This flag is enabled by default. It can be disabled to choose the second 2047approach described above. 2048 2049The below sections analyze the data structures allocated in the coherent memory 2050region and the changes required to allocate them in normal memory. 2051 2052Coherent memory usage in PSCI implementation 2053~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2054 2055The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2056tree information for state management of power domains. By default, this data 2057structure is allocated in the coherent memory region in TF-A because it can be 2058accessed by multiple CPUs, either with caches enabled or disabled. 2059 2060.. code:: c 2061 2062 typedef struct non_cpu_pwr_domain_node { 2063 /* 2064 * Index of the first CPU power domain node level 0 which has this node 2065 * as its parent. 2066 */ 2067 unsigned int cpu_start_idx; 2068 2069 /* 2070 * Number of CPU power domains which are siblings of the domain indexed 2071 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2072 * -> cpu_start_idx + ncpus' have this node as their parent. 2073 */ 2074 unsigned int ncpus; 2075 2076 /* 2077 * Index of the parent power domain node. 2078 */ 2079 unsigned int parent_node; 2080 2081 plat_local_state_t local_state; 2082 2083 unsigned char level; 2084 2085 /* For indexing the psci_lock array*/ 2086 unsigned char lock_index; 2087 } non_cpu_pd_node_t; 2088 2089In order to move this data structure to normal memory, the use of each of its 2090fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2091``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2092them from coherent memory involves only doing a clean and invalidate of the 2093cache lines after these fields are written. 2094 2095The field ``local_state`` can be concurrently accessed by multiple CPUs in 2096different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2097mutual exclusion to this field and a clean and invalidate is needed after it 2098is written. 2099 2100Bakery lock data 2101~~~~~~~~~~~~~~~~ 2102 2103The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2104and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2105defined as follows: 2106 2107.. code:: c 2108 2109 typedef struct bakery_lock { 2110 /* 2111 * The lock_data is a bit-field of 2 members: 2112 * Bit[0] : choosing. This field is set when the CPU is 2113 * choosing its bakery number. 2114 * Bits[1 - 15] : number. This is the bakery number allocated. 2115 */ 2116 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2117 } bakery_lock_t; 2118 2119It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2120fields can be read by all CPUs but only written to by the owning CPU. 2121 2122Depending upon the data cache line size, the per-CPU fields of the 2123``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2124These per-CPU fields can be read and written during lock contention by multiple 2125CPUs with mismatched memory attributes. Since these fields are a part of the 2126lock implementation, they do not have access to any other locking primitive to 2127safeguard against the resulting coherency issues. As a result, simple software 2128cache maintenance is not enough to allocate them in coherent memory. Consider 2129the following example. 2130 2131CPU0 updates its per-CPU field with data cache enabled. This write updates a 2132local cache line which contains a copy of the fields for other CPUs as well. Now 2133CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2134disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2135its field in any other cache line in the system. This operation will invalidate 2136the update made by CPU0 as well. 2137 2138To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2139has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2140algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2141for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2142needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2143for other cores by using the total size allocated for the bakery_lock section 2144and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2145perform software cache maintenance on the lock data structure without running 2146into coherency issues associated with mismatched attributes. 2147 2148The bakery lock data structure ``bakery_info_t`` is defined for use when 2149``USE_COHERENT_MEM`` is disabled as follows: 2150 2151.. code:: c 2152 2153 typedef struct bakery_info { 2154 /* 2155 * The lock_data is a bit-field of 2 members: 2156 * Bit[0] : choosing. This field is set when the CPU is 2157 * choosing its bakery number. 2158 * Bits[1 - 15] : number. This is the bakery number allocated. 2159 */ 2160 volatile uint16_t lock_data; 2161 } bakery_info_t; 2162 2163The ``bakery_info_t`` represents a single per-CPU field of one lock and 2164the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2165system represents the complete bakery lock. The view in memory for a system 2166with n bakery locks are: 2167 2168:: 2169 2170 .bakery_lock section start 2171 |----------------| 2172 | `bakery_info_t`| <-- Lock_0 per-CPU field 2173 | Lock_0 | for CPU0 2174 |----------------| 2175 | `bakery_info_t`| <-- Lock_1 per-CPU field 2176 | Lock_1 | for CPU0 2177 |----------------| 2178 | .... | 2179 |----------------| 2180 | `bakery_info_t`| <-- Lock_N per-CPU field 2181 | Lock_N | for CPU0 2182 ------------------ 2183 | XXXXX | 2184 | Padding to | 2185 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2186 | Granule | continuous memory for remaining CPUs. 2187 ------------------ 2188 | `bakery_info_t`| <-- Lock_0 per-CPU field 2189 | Lock_0 | for CPU1 2190 |----------------| 2191 | `bakery_info_t`| <-- Lock_1 per-CPU field 2192 | Lock_1 | for CPU1 2193 |----------------| 2194 | .... | 2195 |----------------| 2196 | `bakery_info_t`| <-- Lock_N per-CPU field 2197 | Lock_N | for CPU1 2198 ------------------ 2199 | XXXXX | 2200 | Padding to | 2201 | next Cache WB | 2202 | Granule | 2203 ------------------ 2204 2205Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2206operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2207``.bakery_lock`` section need to be fetched and appropriate cache operations need 2208to be performed for each access. 2209 2210On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2211driver (``arm_lock``). 2212 2213Non Functional Impact of removing coherent memory 2214~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2215 2216Removal of the coherent memory region leads to the additional software overhead 2217of performing cache maintenance for the affected data structures. However, since 2218the memory where the data structures are allocated is cacheable, the overhead is 2219mostly mitigated by an increase in performance. 2220 2221There is however a performance impact for bakery locks, due to: 2222 2223- Additional cache maintenance operations, and 2224- Multiple cache line reads for each lock operation, since the bakery locks 2225 for each CPU are distributed across different cache lines. 2226 2227The implementation has been optimized to minimize this additional overhead. 2228Measurements indicate that when bakery locks are allocated in Normal memory, the 2229minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2230in Device memory the same is 2 micro seconds. The measurements were done on the 2231Juno Arm development platform. 2232 2233As mentioned earlier, almost a page of memory can be saved by disabling 2234``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2235whether coherent memory should be used. If a platform disables 2236``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2237optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2238:ref:`Porting Guide`). Refer to the reference platform code for examples. 2239 2240Isolating code and read-only data on separate memory pages 2241---------------------------------------------------------- 2242 2243In the Armv8-A VMSA, translation table entries include fields that define the 2244properties of the target memory region, such as its access permissions. The 2245smallest unit of memory that can be addressed by a translation table entry is 2246a memory page. Therefore, if software needs to set different permissions on two 2247memory regions then it needs to map them using different memory pages. 2248 2249The default memory layout for each BL image is as follows: 2250 2251:: 2252 2253 | ... | 2254 +-------------------+ 2255 | Read-write data | 2256 +-------------------+ Page boundary 2257 | <Padding> | 2258 +-------------------+ 2259 | Exception vectors | 2260 +-------------------+ 2 KB boundary 2261 | <Padding> | 2262 +-------------------+ 2263 | Read-only data | 2264 +-------------------+ 2265 | Code | 2266 +-------------------+ BLx_BASE 2267 2268.. note:: 2269 The 2KB alignment for the exception vectors is an architectural 2270 requirement. 2271 2272The read-write data start on a new memory page so that they can be mapped with 2273read-write permissions, whereas the code and read-only data below are configured 2274as read-only. 2275 2276However, the read-only data are not aligned on a page boundary. They are 2277contiguous to the code. Therefore, the end of the code section and the beginning 2278of the read-only data one might share a memory page. This forces both to be 2279mapped with the same memory attributes. As the code needs to be executable, this 2280means that the read-only data stored on the same memory page as the code are 2281executable as well. This could potentially be exploited as part of a security 2282attack. 2283 2284TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2285read-only data on separate memory pages. This in turn allows independent control 2286of the access permissions for the code and read-only data. In this case, 2287platform code gets a finer-grained view of the image layout and can 2288appropriately map the code region as executable and the read-only data as 2289execute-never. 2290 2291This has an impact on memory footprint, as padding bytes need to be introduced 2292between the code and read-only data to ensure the segregation of the two. To 2293limit the memory cost, this flag also changes the memory layout such that the 2294code and exception vectors are now contiguous, like so: 2295 2296:: 2297 2298 | ... | 2299 +-------------------+ 2300 | Read-write data | 2301 +-------------------+ Page boundary 2302 | <Padding> | 2303 +-------------------+ 2304 | Read-only data | 2305 +-------------------+ Page boundary 2306 | <Padding> | 2307 +-------------------+ 2308 | Exception vectors | 2309 +-------------------+ 2 KB boundary 2310 | <Padding> | 2311 +-------------------+ 2312 | Code | 2313 +-------------------+ BLx_BASE 2314 2315With this more condensed memory layout, the separation of read-only data will 2316add zero or one page to the memory footprint of each BL image. Each platform 2317should consider the trade-off between memory footprint and security. 2318 2319This build flag is disabled by default, minimising memory footprint. On Arm 2320platforms, it is enabled. 2321 2322Publish and Subscribe Framework 2323------------------------------- 2324 2325The Publish and Subscribe Framework allows EL3 components to define and publish 2326events, to which other EL3 components can subscribe. 2327 2328The following macros are provided by the framework: 2329 2330- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2331 the event name, which must be a valid C identifier. All calls to 2332 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2333 ``pubsub_events.h``. 2334 2335- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2336 subscribed handlers and calling them in turn. The handlers will be passed the 2337 parameter ``arg``. The expected use-case is to broadcast an event. 2338 2339- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2340 ``NULL`` is passed to subscribed handlers. 2341 2342- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2343 subscribe to ``event``. The handler will be executed whenever the ``event`` 2344 is published. 2345 2346- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2347 subscribed for ``event``. ``subscriber`` must be a local variable of type 2348 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2349 iteration. This macro can be used for those patterns that none of the 2350 ``PUBLISH_EVENT_*()`` macros cover. 2351 2352Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2353result in build error. Subscribing to an undefined event however won't. 2354 2355Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2356signature: 2357 2358.. code:: c 2359 2360 typedef void* (*pubsub_cb_t)(const void *arg); 2361 2362There may be arbitrary number of handlers registered to the same event. The 2363order in which subscribed handlers are notified when that event is published is 2364not defined. Subscribed handlers may be executed in any order; handlers should 2365not assume any relative ordering amongst them. 2366 2367Publishing an event on a PE will result in subscribed handlers executing on that 2368PE only; it won't cause handlers to execute on a different PE. 2369 2370Note that publishing an event on a PE blocks until all the subscribed handlers 2371finish executing on the PE. 2372 2373TF-A generic code publishes and subscribes to some events within. Platform 2374ports are discouraged from subscribing to them. These events may be withdrawn, 2375renamed, or have their semantics altered in the future. Platforms may however 2376register, publish, and subscribe to platform-specific events. 2377 2378Publish and Subscribe Example 2379~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2380 2381A publisher that wants to publish event ``foo`` would: 2382 2383- Define the event ``foo`` in the ``pubsub_events.h``. 2384 2385 .. code:: c 2386 2387 REGISTER_PUBSUB_EVENT(foo); 2388 2389- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2390 publish the event at the appropriate path and time of execution. 2391 2392A subscriber that wants to subscribe to event ``foo`` published above would 2393implement: 2394 2395.. code:: c 2396 2397 void *foo_handler(const void *arg) 2398 { 2399 void *result; 2400 2401 /* Do handling ... */ 2402 2403 return result; 2404 } 2405 2406 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2407 2408 2409Reclaiming the BL31 initialization code 2410~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2411 2412A significant amount of the code used for the initialization of BL31 is never 2413needed again after boot time. In order to reduce the runtime memory 2414footprint, the memory used for this code can be reclaimed after initialization 2415has finished and be used for runtime data. 2416 2417The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2418with a ``.text.init.*`` attribute which can be filtered and placed suitably 2419within the BL image for later reclamation by the platform. The platform can 2420specify the filter and the memory region for this init section in BL31 via the 2421plat.ld.S linker script. For example, on the FVP, this section is placed 2422overlapping the secondary CPU stacks so that after the cold boot is done, this 2423memory can be reclaimed for the stacks. The init memory section is initially 2424mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2425completed, the FVP changes the attributes of this section to ``RW``, 2426``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2427are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2428section section can be reclaimed for any data which is accessed after cold 2429boot initialization and it is upto the platform to make the decision. 2430 2431.. _firmware_design_pmf: 2432 2433Performance Measurement Framework 2434--------------------------------- 2435 2436The Performance Measurement Framework (PMF) facilitates collection of 2437timestamps by registered services and provides interfaces to retrieve them 2438from within TF-A. A platform can choose to expose appropriate SMCs to 2439retrieve these collected timestamps. 2440 2441By default, the global physical counter is used for the timestamp 2442value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2443timestamps captured by other CPUs. 2444 2445Timestamp identifier format 2446~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2447 2448A PMF timestamp is uniquely identified across the system via the 2449timestamp ID or ``tid``. The ``tid`` is composed as follows: 2450 2451:: 2452 2453 Bits 0-7: The local timestamp identifier. 2454 Bits 8-9: Reserved. 2455 Bits 10-15: The service identifier. 2456 Bits 16-31: Reserved. 2457 2458#. The service identifier. Each PMF service is identified by a 2459 service name and a service identifier. Both the service name and 2460 identifier are unique within the system as a whole. 2461 2462#. The local timestamp identifier. This identifier is unique within a given 2463 service. 2464 2465Registering a PMF service 2466~~~~~~~~~~~~~~~~~~~~~~~~~ 2467 2468To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2469is used. The arguments required are the service name, the service ID, 2470the total number of local timestamps to be captured and a set of flags. 2471 2472The ``flags`` field can be specified as a bitwise-OR of the following values: 2473 2474:: 2475 2476 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2477 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2478 2479The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2480timestamps in a PMF specific linker section at build time. 2481Additionally, it defines necessary functions to capture and 2482retrieve a particular timestamp for the given service at runtime. 2483 2484The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2485from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2486``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2487accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2488macro but additionally supports retrieving timestamps using SMCs. 2489 2490Capturing a timestamp 2491~~~~~~~~~~~~~~~~~~~~~ 2492 2493PMF timestamps are stored in a per-service timestamp region. On a 2494system with multiple CPUs, each timestamp is captured and stored 2495in a per-CPU cache line aligned memory region. 2496 2497Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2498used to capture a timestamp at the location where it is used. The macro 2499takes the service name, a local timestamp identifier and a flag as arguments. 2500 2501The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2502instructs PMF to do cache maintenance following the capture. Cache 2503maintenance is required if any of the service's timestamps are captured 2504with data cache disabled. 2505 2506To capture a timestamp in assembly code, the caller should use 2507``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2508calculate the address of where the timestamp would be stored. The 2509caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2510and store it at the determined address for later retrieval. 2511 2512Retrieving a timestamp 2513~~~~~~~~~~~~~~~~~~~~~~ 2514 2515From within TF-A, timestamps for individual CPUs can be retrieved using either 2516``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2517These macros accept the CPU's MPIDR value, or its ordinal position 2518respectively. 2519 2520From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2521into ``pmf_smc_handler()``. 2522 2523:: 2524 2525 Interface : pmf_smc_handler() 2526 Argument : unsigned int smc_fid, u_register_t x1, 2527 u_register_t x2, u_register_t x3, 2528 u_register_t x4, void *cookie, 2529 void *handle, u_register_t flags 2530 Return : uintptr_t 2531 2532 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2533 when the caller of the SMC is running in AArch32 mode 2534 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2535 x1: Timestamp identifier. 2536 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2537 This can be the `mpidr` of a different core to the one initiating 2538 the SMC. In that case, service specific cache maintenance may be 2539 required to ensure the updated copy of the timestamp is returned. 2540 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2541 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2542 cache invalidate before reading the timestamp. This ensures 2543 an updated copy is returned. 2544 2545The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2546in this implementation. 2547 2548PMF code structure 2549~~~~~~~~~~~~~~~~~~ 2550 2551#. ``pmf_main.c`` consists of core functions that implement service registration, 2552 initialization, storing, dumping and retrieving timestamps. 2553 2554#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2555 2556#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2557 2558#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2559 assembly code. 2560 2561#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2562 2563Armv8-A Architecture Extensions 2564------------------------------- 2565 2566TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2567section lists the usage of Architecture Extensions, and build flags 2568controlling them. 2569 2570Build options 2571~~~~~~~~~~~~~ 2572 2573``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` 2574 2575These build options serve dual purpose 2576 2577- Determine the architecture extension support in TF-A build: All the mandatory 2578 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included 2579 and unconditionally enabled by TF-A build system. 2580 2581- Passed to compiler via "-march" option to generate binary target : Tell the 2582 compiler to emit instructions upto ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` 2583 2584The build system requires that the platform provides a valid numeric value based on 2585CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. 2586Subsequent Arm Architecture versions also support extensions which were introduced 2587in previous versions. 2588 2589**TO-DO** : Its planned to decouple the two functionalities and introduce a new macro 2590for compiler usage. The requirement for this decoupling arises becasue TF-A code 2591always provides support for the latest and greatest architecture features but this 2592is not the case for the target compiler. 2593 2594.. seealso:: :ref:`Build Options` 2595 2596For details on the Architecture Extension and available features, please refer 2597to the respective Architecture Extension Supplement. 2598 2599Armv8.1-A 2600~~~~~~~~~ 2601 2602This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2603``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2604 2605- By default, a load-/store-exclusive instruction pair is used to implement 2606 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2607 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2608 Notice this instruction is only available in AArch64 execution state, so 2609 the option is only available to AArch64 builds. 2610 2611Armv8.2-A 2612~~~~~~~~~ 2613 2614- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2615 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2616 Processing Elements in the same Inner Shareable domain use the same 2617 translation table entries for a given stage of translation for a particular 2618 translation regime. 2619 2620Armv8.3-A 2621~~~~~~~~~ 2622 2623- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2624 the Non-secure world so that lower ELs are allowed to use them without 2625 causing a trap to EL3. 2626 2627 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2628 must be set to 1. This will add all pointer authentication system registers 2629 to the context that is saved when doing a world switch. 2630 2631 The TF-A itself has support for pointer authentication at runtime 2632 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2633 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2634 BL2, BL31, and the TSP if it is used. 2635 2636 Note that Pointer Authentication is enabled for Non-secure world irrespective 2637 of the value of these build flags if the CPU supports it. 2638 2639 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2640 enabling PAuth is lower because the compiler will use the optimized 2641 PAuth instructions rather than the backwards-compatible ones. 2642 2643Armv8.5-A 2644~~~~~~~~~ 2645 2646- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2647 option set to 1. This option defaults to 0. 2648 2649- Memory Tagging Extension feature is unconditionally enabled for both worlds 2650 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2651 implemented at all ELs, it is unconditionally enabled for only the normal 2652 world. To enable it for the secure world as well, the build option 2653 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2654 MTE support at all, it is always disabled, no matter what build options 2655 are used. 2656 2657Armv7-A 2658~~~~~~~ 2659 2660This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2661 2662There are several Armv7-A extensions available. Obviously the TrustZone 2663extension is mandatory to support the TF-A bootloader and runtime services. 2664 2665Platform implementing an Armv7-A system can to define from its target 2666Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2667``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2668Cortex-A15 target. 2669 2670Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2671Note that using neon at runtime has constraints on non secure world context. 2672TF-A does not yet provide VFP context management. 2673 2674Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2675the toolchain target architecture directive. 2676 2677Platform may choose to not define straight the toolchain target architecture 2678directive by defining ``MARCH32_DIRECTIVE``. 2679I.e: 2680 2681.. code:: make 2682 2683 MARCH32_DIRECTIVE := -mach=armv7-a 2684 2685Code Structure 2686-------------- 2687 2688TF-A code is logically divided between the three boot loader stages mentioned 2689in the previous sections. The code is also divided into the following 2690categories (present as directories in the source code): 2691 2692- **Platform specific.** Choice of architecture specific code depends upon 2693 the platform. 2694- **Common code.** This is platform and architecture agnostic code. 2695- **Library code.** This code comprises of functionality commonly used by all 2696 other code. The PSCI implementation and other EL3 runtime frameworks reside 2697 as Library components. 2698- **Stage specific.** Code specific to a boot stage. 2699- **Drivers.** 2700- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2701 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2702 2703Each boot loader stage uses code from one or more of the above mentioned 2704categories. Based upon the above, the code layout looks like this: 2705 2706:: 2707 2708 Directory Used by BL1? Used by BL2? Used by BL31? 2709 bl1 Yes No No 2710 bl2 No Yes No 2711 bl31 No No Yes 2712 plat Yes Yes Yes 2713 drivers Yes No Yes 2714 common Yes Yes Yes 2715 lib Yes Yes Yes 2716 services No No Yes 2717 2718The build system provides a non configurable build option IMAGE_BLx for each 2719boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2720defined by the build system. This enables TF-A to compile certain code only 2721for specific boot loader stages 2722 2723All assembler files have the ``.S`` extension. The linker source files for each 2724boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2725linker scripts which have the extension ``.ld``. 2726 2727FDTs provide a description of the hardware platform and are used by the Linux 2728kernel at boot time. These can be found in the ``fdts`` directory. 2729 2730.. rubric:: References 2731 2732- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2733 2734- `Power State Coordination Interface PDD`_ 2735 2736- `SMC Calling Convention`_ 2737 2738- :ref:`Interrupt Management Framework` 2739 2740-------------- 2741 2742*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* 2743 2744.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2745.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2746.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2747.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2748.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2749.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2750.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2751.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2752 2753.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2754
