core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Er

zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-o

core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rename interrupt controller functions

This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic()

core: rename interrupt controller functions

This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic() to secondary_init_intc()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This chang

drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This change
factorize this logic from gic_init() implementation and makes
gic_init_base_addr() local to gic.c.

For that purpose functions gic_init_base_address() and gic_dt_get_irq()
are moved inside gic.c source file.
source file.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This

core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This change factorize these implementation by moving the definition
of the controller data instance straight in the controller driver
source file. This change makes each controller driver to implement
straight itr_core_handler() function, preventing a extra branch on
interrupt execution. Interrupt controller driver initialization
function now straight calls itr_core_init().

This changes treats case when CFG_CORE_WORKAROUND_ARM_NMFI is enable
to not conflict with core/arch/arm/kernel/thread.c that already
overrides itr_core_handler() weak implementation.

With this change, the main controller initialization function
(gic_init(), gic_init_base_addr(), gic_cpu_init() and hfic_init())
no more gets the controller data as input argument.

As a consequence, definition of struct hfic_data and struct gic_data
moves from their respective driver header file to the respective
driver source file.

As a consequence, gic_dump() no more requires an argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-zynqmp: fixes interrupt controller

Updates GICC_OFFSET to account for the already-offset GIC_BASE.
Additionally initializes the interrupt controller with a pointer
to the interrupt chip.

Signe

plat-zynqmp: fixes interrupt controller

Updates GICC_OFFSET to account for the already-offset GIC_BASE.
Additionally initializes the interrupt controller with a pointer
to the interrupt chip.

Signed-off-by: Zachary Clark <zach.clark@dornerworks.com>
Reviewed-by: Ricardo Salveti <ricardo@foundries.io>

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plat-zynqmp: add ZCU104 and ZCU106 flavour support

Adding support for the ZCU104 and ZCU106 boards
since they possess the same core as the ZCU102.
This is to avoid having the "flavour not supported

plat-zynqmp: add ZCU104 and ZCU106 flavour support

Adding support for the ZCU104 and ZCU106 boards
since they possess the same core as the ZCU102.
This is to avoid having the "flavour not supported error"
when compiling for the ZCU104 and ZCU106.

Tested successfully on the ZCU106

Tested-by: Nasreddine Ouldei Tebina <tebina1@live.fr>
Signed-off-by: Nasreddine Ouldei Tebina <tebina1@live.fr>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>

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drivers: zynqmp_huk: Add AES eFuse and HUK seed support

When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption

drivers: zynqmp_huk: Add AES eFuse and HUK seed support

When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption is
in use AES eFuse key becomes device key instead of PUF generated key.

In order to re-plenish additional device specific entropy that PUF would
provide utilize selected set of User programmable eFuses.

Selected user eFuses should be programmed during device manufacturing with
cryptographically good random numbers.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-zynqmp: Added __nex_bss symbol for virtualization support

Without the __nex_bss symbol added to gic_data and console_data
the zynqmp platform results in a deadlock when attempting
to write to t

plat-zynqmp: Added __nex_bss symbol for virtualization support

Without the __nex_bss symbol added to gic_data and console_data
the zynqmp platform results in a deadlock when attempting
to write to the serial device on the platform. This fix resolves
the deadlock issue. More details can be found in the referred link.

Link: https://github.com/OP-TEE/optee_os/issues/5384
Signed-off-by: Michael Doran <michael.doran@dornerworks.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: provide uart configuration during compilation

Add possibility to provide UART configuration as a compile
flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).

Acked-by: Jerome Foris

zynqmp: platform: provide uart configuration during compilation

Add possibility to provide UART configuration as a compile
flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm.mk: set CFG_WITH_LPAE=y when CFG_ARCH64_core=y

Since CFG_WITH_LPAE=y is mandatory when CFG_ARCH64_core=y, set it in the
common file core/arch/arm/arm.mk instead of leaving it to the platfo

core: arm.mk: set CFG_WITH_LPAE=y when CFG_ARCH64_core=y

Since CFG_WITH_LPAE=y is mandatory when CFG_ARCH64_core=y, set it in the
common file core/arch/arm/arm.mk instead of leaving it to the platforms.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: arm: fix refactor GIC initialization

Commit 60801696667d ("plat: arm: refactor GIC initialization") converts
functions gic_init_base_addr() and gic_init() to take physical addresses
instead of

plat: arm: fix refactor GIC initialization

Commit 60801696667d ("plat: arm: refactor GIC initialization") converts
functions gic_init_base_addr() and gic_init() to take physical addresses
instead of virtual, but only converts half the platforms. This causes
boot failure on all the others.

Convert the rest here.

Fixes: 60801696667d ("plat: arm: refactor GIC initialization")
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: wrap lines >80 characters; cite commit using commonly used format]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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zynqmp: zcu102: Fix DDR memory size to 4 GiB

Xilinx ZCU102 board has 4 GiB of DDR memory and size must be configured
properly in order for dynamic shared memory feature to work.

Without it followin

zynqmp: zcu102: Fix DDR memory size to 4 GiB

Xilinx ZCU102 board has 4 GiB of DDR memory and size must be configured
properly in order for dynamic shared memory feature to work.

Without it following error might be present during kernel startup:

E/TC:0 0 std_smc_entry:183 Bad arg address 0x803989000

When compiling for 32 bits only first 2 GiB is available.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: make it possible to configure DDR size more flexible

Default DDR size comes from platform selection.

If only DDR size is different it is possible to override it with
setting CFG_D

zynqmp: platform: make it possible to configure DDR size more flexible

Default DDR size comes from platform selection.

If only DDR size is different it is possible to override it with
setting CFG_DDR_SIZE.

Automatic configuration of DDR memory mappings can also be done by device
tree (CFG_DT=y) and by overriding if necessary memory address for device
tree (CFG_DT_ADDR).

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: configure default device tree address

Xilinx has selected 0x100000 as default memory address for device tree.

Configure it by default and make it possible to override it (CFG_DT_A

zynqmp: platform: configure default device tree address

Xilinx has selected 0x100000 as default memory address for device tree.

Configure it by default and make it possible to override it (CFG_DT_ADDR).

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: configure physical address space size

ZynqMP has several operation modes for physical address mapping:
32 bit mode, 36 bits and 40 bits

When compiling for 64 bits use full 40 bits

zynqmp: platform: configure physical address space size

ZynqMP has several operation modes for physical address mapping:
32 bit mode, 36 bits and 40 bits

When compiling for 64 bits use full 40 bits mode as default to support all
features of the chip.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: use HUK derived from PUF KEK for RPMB

Enable the RPMB key when the HUK is generated from the PUF KEK.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Tested-by: Ricardo Sa

zynqmp: platform: use HUK derived from PUF KEK for RPMB

Enable the RPMB key when the HUK is generated from the PUF KEK.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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zynqmp: drivers: generate HUK from PUF KEK

If authenticated boot was disabled we allow generating the HUK using
the SHA-256 of the DNA unique identifier.

If authenticated boot was enabled, use the

zynqmp: drivers: generate HUK from PUF KEK

If authenticated boot was disabled we allow generating the HUK using
the SHA-256 of the DNA unique identifier.

If authenticated boot was enabled, use the PUK KEK to generate the
HUK instead. The PUF KEK must be registered while securing the board
using the Xilinx tools. In this case, the HUK is generated by reading
the DNA eFuses. This 96 bits value is used to generate a 16 byte
digest which is then AES-GCM encrypted using the PUF KEK. The
resulting 16 byte value is the HUK. To prevent the HUK from being
leaked, the AES-GCM module must be reserved.

The HUK generation was validated on Zynqmp zu3cg using the Xilinx
Lightweight Provisioning Tool to enable authenticated boot and to
provision the PUF (burning a number of eFuses in the process).

Tested-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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