1PLATFORM_FLAVOR ?= zcu102 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5$(call force,CFG_TEE_CORE_NB_CORE,4) 6$(call force,CFG_CDNS_UART,y) 7$(call force,CFG_GIC,y) 8$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 9$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 10 11# Disable core ASLR for two reasons: 12# 1. There is no source for ALSR seed, as ATF does not provide a 13# DTB to OP-TEE. Hardware RNG is also not currently supported. 14# 2. OP-TEE does not boot with enabled CFG_CORE_ASLR. 15$(call force,CFG_CORE_ASLR,n) 16 17ifeq ($(CFG_ARM64_core),y) 18$(call force,CFG_WITH_LPAE,y) 19 20# ZynqMP supports up to 40 bits of physical addresses 21CFG_CORE_ARM64_PA_BITS ?= 40 22else 23$(call force,CFG_ARM32_core,y) 24endif 25 26# Configure DDR size either by using device tree or override it with: 27CFG_DDR_SIZE ?= 0x80000000 28 29# By default use DT address as specified by Xilinx 30CFG_DT_ADDR ?= 0x100000 31 32CFG_TZDRAM_START ?= 0x60000000 33CFG_TZDRAM_SIZE ?= 0x10000000 34CFG_SHMEM_START ?= 0x70000000 35CFG_SHMEM_SIZE ?= 0x10000000 36 37CFG_WITH_STATS ?= y 38CFG_CRYPTO_WITH_CE ?= y 39 40CFG_ZYNQMP_PM ?= $(CFG_ARM64_core) 41 42ifeq ($(CFG_RPMB_FS),y) 43$(call force,CFG_ZYNQMP_HUK,y,Mandated by CFG_RPMB_FS) 44endif 45 46ifeq ($(CFG_ZYNQMP_HUK),y) 47$(call force,CFG_ZYNQMP_CSU_AES,y,Mandated by CFG_ZYNQMP_HUK) 48$(call force,CFG_ZYNQMP_CSU_PUF,y,Mandated by CFG_ZYNQMP_HUK) 49endif 50 51ifeq ($(CFG_ZYNQMP_CSU_AES),y) 52$(call force,CFG_ZYNQMP_CSUDMA,y,Mandated by CFG_ZYNQMP_CSU_AES) 53$(call force,CFG_DT,y,Mandated by CFG_ZYNQMP_CSU_AES) 54endif 55 56ifneq (,$(filter y, $(CFG_ZYNQMP_CSU_PUF) $(CFG_ZYNQMP_CSUDMA) $(CFG_ZYNQMP_CSU_AES))) 57$(call force,CFG_ZYNQMP_CSU,y,Mandated by CFG_ZYNQMP_CSU* clients) 58endif 59