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Searched refs:VQ_PIDFLT_CTRL (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h991 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h1014 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c4229 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
4230 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h1020 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c4645 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
4646 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h1011 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c4608 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
4609 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h1047 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c4975 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
4976 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h1051 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c5300 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
5301 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h1051 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c5317 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
5318 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h1066 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c5373 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
5374 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h1066 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
H A DhalTSP.c5334 _HAL_REG32_W(&_TspCtrl[0].VQ_PIDFLT_CTRL, in HAL_TSP_Set_Req_VQ_RX_Threshold()
5335 (_HAL_REG32_R(&_TspCtrl[0].VQ_PIDFLT_CTRL) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value); in HAL_TSP_Set_Req_VQ_RX_Threshold()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DregTSP.h912 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h948 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h950 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h988 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h968 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h968 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h990 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h968 REG16 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 member