Home
last modified time | relevance | path

Searched refs:TSP_VID_SRC_SHIFT (Results 1 – 25 of 29) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h1086 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c2491 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
2635 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
2654 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
H A DregTSP.h1118 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h1113 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2728 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
2871 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
2890 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h1104 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2693 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
2836 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
2855 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h1167 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2582 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
2789 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
2814 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h1171 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2785 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
2992 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
3017 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h1171 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2785 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
2992 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
3017 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h1187 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2863 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
3069 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
3094 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h1187 #define TSP_VID_SRC_SHIFT 6UL macro
H A DhalTSP.c2824 …REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (TSP_SRC_FROM_PKTDMXFL << TSP_VID_SRC_SHIFT)); in HAL_TSP_PS_Path_Enable()
3030 …IFO_Src, (_HAL_REG32_R(&_TspCtrl[0].FIFO_Src) & ~TSP_VID_SRC_MASK)| (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
3055 _HAL_TSP_CMD_Write_HWPCR_Reg(TSP_VID_SRC_MASK, (u32Src << TSP_VID_SRC_SHIFT)); in HAL_TSP_AVFIFO_Src_Select()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DregTSP.h1017 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h1053 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h1055 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h1093 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h1063 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h1063 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h1095 #define TSP_VID_SRC_SHIFT 6 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h1063 #define TSP_VID_SRC_SHIFT 6 macro

12