| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | regTSP.h | 458 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | regTSP.h | 459 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| H A D | halTSP.c | 3640 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
3643 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | regTSP.h | 461 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| H A D | halTSP.c | 4018 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
4021 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | regTSP.h | 452 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| H A D | halTSP.c | 3981 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
3984 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | regTSP.h | 474 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| H A D | halTSP.c | 4044 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
4047 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | regTSP.h | 476 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| H A D | halTSP.c | 4287 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
4290 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | regTSP.h | 476 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| H A D | halTSP.c | 4304 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
4307 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PVR2_Config), TSP_PVR2_LPCR1_WLD)); in HAL_TSP_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | regTSP.h | 483 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | regTSP.h | 483 #define TSP_PVR2_LPCR1_WLD 0x00000001UL macro
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | regTSP.h | 364 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| H A D | halTSP.c | 4179 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4183 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | regTSP.h | 399 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| H A D | halTSP.c | 5499 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5503 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | regTSP.h | 401 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | regTSP.h | 433 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | regTSP.h | 431 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | regTSP.h | 431 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | regTSP.h | 435 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | regTSP.h | 431 #define TSP_PVR2_LPCR1_WLD 0x00000001 macro
|