| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | regTSP.h | 932 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | regTSP.h | 918 #define TSP_OPT_ORACESS_TIMING 0x80000000 macro
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| H A D | halTSP.c | 802 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
807 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | regTSP.h | 925 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 925 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
930 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | regTSP.h | 916 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 911 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
916 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | regTSP.h | 947 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 862 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
867 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | regTSP.h | 951 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 931 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
936 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | regTSP.h | 951 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 931 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
936 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | regTSP.h | 958 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 949 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
954 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | regTSP.h | 958 #define TSP_OPT_ORACESS_TIMING 0x80000000UL macro
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| H A D | halTSP.c | 949 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
954 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | regTSP.h | 846 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | regTSP.h | 882 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | regTSP.h | 884 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | regTSP.h | 922 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | regTSP.h | 909 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | regTSP.h | 909 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | regTSP.h | 924 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | regTSP.h | 909 #define TSP_OPT_ORACESS_TIMING 0x8000 macro
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