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Searched refs:MAU1_LV2_0_MIU_SEL (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h367 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2423 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2433 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2443 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2468 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2478 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2488 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2439 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2449 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2459 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2438 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2448 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2458 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2559 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2569 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2579 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2577 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2587 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2597 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2505 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2515 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2525 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2744 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2754 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2764 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2725 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2735 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2745 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h381 #define MAU1_LV2_0_MIU_SEL(vpu) (MAU1_LV2_0_BASE(vpu)+(0x0001<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2719 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2729 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2739 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2715 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2725 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2735 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2727 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2737 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00); in HAL_VPU_EX_CPUSetting()
2747 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()

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