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/rk3399_ARM-atf/plat/common/aarch64/
H A Dcrash_console_helpers.S74 mrs x1, sctlr_el3
75 tst x1, #SCTLR_C_BIT
80 adrp x1, crash_console_triggered
81 add x1, x1, :lo12:crash_console_triggered
82 ldarb w2, [x1]
87 stlrb w3, [x1]
111 adrp x1, crash_console_reg_stash
112 add x1, x1, :lo12:crash_console_reg_stash
113 stp x14, x15, [x1]
114 stp x16, x17, [x1, #16]
[all …]
/rk3399_ARM-atf/include/arch/aarch64/
H A Del3_common_macros.S40 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
45 orr x0, x0, x1
51 is_feat_sctlr2_present_asm x1
54 mov x1, #SCTLR2_RESET_VAL
55 msr SCTLR2_EL3, x1
87 mrs x1, id_aa64pfr0_el1
88 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
89 cbz x1, 1f
225 mov_imm x1, \_pie_fixup_size
226 add x1, x1, x0
[all …]
H A Dconsole_macros.S26 adrp x1, console_\_driver\()_putc
27 add x1, x1, :lo12:console_\_driver\()_putc
28 str x1, [x0, #CONSOLE_T_PUTC]
39 adrp x1, console_\_driver\()_getc
40 add x1, x1, :lo12:console_\_driver\()_getc
41 str x1, [x0, #CONSOLE_T_GETC]
49 adrp x1, console_\_driver\()_flush
50 add x1, x1, :lo12:console_\_driver\()_flush
51 str x1, [x0, #CONSOLE_T_FLUSH]
56 mov x1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
[all …]
/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Ddsu_macros.S19 mrs x1, CLUSTERIDR_EL1
22 ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\
24 mov x1, #(0x0 << CLUSTERIDR_REV_SHIFT)
25 cmp x0, x1
50 mrs x1, CLUSTERCFR_EL1
51 ubfx x1, x1, #CLUSTERCFR_ACP_SHIFT, #1
52 cbz x1, 1f
55 mrs x1, CLUSTERIDR_EL1
58 ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\
69 ldr x1, =DSU_ERRATA_936184_MASK
[all …]
/rk3399_ARM-atf/plat/st/stm32mp2/aarch64/
H A Dstm32mp2_helper.S67 and x1, x0, #MPIDR_CPU_MASK
69 add x0, x1, x0, LSR #6
92 mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG)
94 ldr w0, [x1]
96 str w0, [x1]
98 ldr w0, [x1]
102 str w0, [x1]
104 ldr w0, [x1]
108 mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
109 ldr w2, [x1]
[all …]
/rk3399_ARM-atf/bl31/aarch64/
H A Dbl31_entrypoint.S31 mov x21, x1
76 mov x1, x21
95 adrp x1, __DATA_END__
96 add x1, x1, :lo12:__DATA_END__
97 sub x1, x1, x0
102 adrp x1, __BSS_END__
103 add x1, x1, :lo12:__BSS_END__
104 sub x1, x1, x0
109 adrp x1, __PER_CPU_END__
110 add x1, x1, :lo12:__PER_CPU_END__
[all …]
/rk3399_ARM-atf/bl2/aarch64/
H A Dbl2_entrypoint.S23 mov x21, x1
48 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
50 orr x0, x0, x1
69 adr x1, __RW_END__
70 sub x1, x1, x0
81 adrp x1, __BSS_END__
82 add x1, x1, :lo12:__BSS_END__
83 sub x1, x1, x0
89 adrp x1, __COHERENT_RAM_END_UNALIGNED__
90 add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
[all …]
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/aarch64/
H A Dlx2160a_warm_rst.S45 ldr x1, =NXP_DDR_ADDR
47 ldr w0, [x1, #SDRAM_CFG]
49 str w0, [x1, #SDRAM_CFG]
51 ldr w0, [x1, #DEBUG_2]
55 ldr w0, [x1, #DEBUG_26]
64 str w0, [x1, #DEBUG_26]
66 ldr w0, [x1, #SDRAM_CFG_2]
68 str w0, [x1, #SDRAM_CFG_2]
71 ldr w0, [x1, #DDR_DSR2]
73 str w0, [x1, #DDR_DSR2]
[all …]
H A Dlx2160a.S102 mov x1, xzr
190 mov x1, x0
194 lsr x1, x0, #32
207 ldr x1, =NXP_SEC_REGFILE_ADDR
212 str w0, [x1, #CORE_HOLD_OFFSET]
215 mov x1, #NXP_RESET_ADDR
216 ldr w2, [x1, #BRR_OFFSET]
220 str w2, [x1, #BRR_OFFSET]
242 ldr x1, =NXP_DCFG_ADDR
245 ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
[all …]
/rk3399_ARM-atf/plat/arm/board/common/aarch64/
H A Dboard_arm_helpers.S23 mrs x1, CurrentEl
24 lsr x1, x1, #MODE_EL_SHIFT
25 lsl x1, x1, #V2M_SYS_LED_EL_SHIFT
29 orr x0, x0, x1
30 mov x1, #V2M_SYSREGS_BASE
31 add x1, x1, #V2M_SYS_LED
32 str w0, [x1]
/rk3399_ARM-atf/drivers/coreboot/cbmem_console/aarch64/
H A Dcbmem_console.S38 str x0, [x1, #CONSOLE_T_BASE]
40 str w2, [x1, #CONSOLE_T_CBMC_SIZE]
41 mov x0, x1
56 ldr w2, [x1, #CONSOLE_T_CBMC_SIZE]
57 ldr x1, [x1, #CONSOLE_T_BASE]
58 add x1, x1, #8 /* keep address of body in x1 */
60 ldr w16, [x1, #-4] /* load cursor (one u32 before body) */
70 strb w0, [x1, w16, uxtw] /* body[cursor] = character */
80 str w16, [x1, #-4] /* write back cursor to memory */
94 ldr x1, [x0, #CONSOLE_T_CBMC_SIZE]
[all …]
/rk3399_ARM-atf/plat/arm/board/fvp/aarch64/
H A Dfvp_helpers.S44 mrs x1, CPUPWRCTLR_EL1
45 orr x1, x1, #CPUPWRCTLR_EL1_CORE_PWRDN_BIT
46 msr CPUPWRCTLR_EL1, x1
58 mov_imm x1, PWRC_BASE
59 str w0, [x1, #PPOFFR_OFF]
75 ldr x1, [x0]
76 cbz x1, 1f
77 br x1
109 mov_imm x1, PWRC_BASE
110 str w2, [x1, #PSYSR_OFF]
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/aarch64/
H A Dls1028a.S82 mov x1, xzr
135 ldr x1, =NXP_DCFG_ADDR
138 ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
182 ldr x1, =NXP_SEC_REGFILE_ADDR
183 str w0, [x1, #CORE_HOLD_OFFSET]
186 mov x1, #NXP_RESET_ADDR
187 ldr w2, [x1, #BRR_OFFSET]
189 str w2, [x1, #BRR_OFFSET]
210 mov x1, x0
214 lsr x1, x0, #32
[all …]
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmrvl_sip_svc.c74 u_register_t x1, in mrvl_sip_smc_handler() argument
82 u_register_t ret, read, x5 = x1; in mrvl_sip_smc_handler()
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
90 if (!is_cp_range_valid(&x1)) { in mrvl_sip_smc_handler()
92 __func__, smc_fid, x1); in mrvl_sip_smc_handler()
96 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; in mrvl_sip_smc_handler()
97 x1 += MVEBU_COMPHY_OFFSET; in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); in mrvl_sip_smc_handler()
119 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
[all …]
/rk3399_ARM-atf/services/spd/trusty/
H A Dtrusty_helpers.S40 ldr x2, [x1]
41 ldr x3, [x1, #0x08]
42 ldr x4, [x1, #0x10]
43 ldr x5, [x1, #0x18]
44 ldr x6, [x1, #0x20]
45 ldr x7, [x1, #0x28]
46 ldr x10, [x1, #0x30]
47 ldr x11, [x1, #0x38]
59 push x8, xzr, x1
60 push xzr, xzr, x1
[all …]
/rk3399_ARM-atf/plat/qti/msm8916/aarch64/
H A Dmsm8916_helpers.S38 mov_imm x1, BLSP_UART_BASE
52 mov_imm x1, BLSP_UART_BASE
64 mov_imm x1, BLSP_UART_BASE
87 mrs x1, mpidr_el1
88 and x0, x1, #MPIDR_CPU_MASK
90 and x1, x1, #MPIDR_CLUSTER_MASK
91 orr x0, x0, x1, LSR #(MPIDR_AFFINITY_BITS - \
117 mov_imm x1, APCS_CFG(0)
118 ldr w2, [x1, #APCS_TCM_START_ADDR]
120 str w2, [x1, #APCS_TCM_START_ADDR]
[all …]
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/
H A Drdv3_per_cpu.S40 mov x1, x0
46 cmp x1, x0
50 udiv x0, x1, x2
51 msub x2, x0, x2, x1
54 adrp x1, per_cpu_nodes_base
55 add x1, x1, :lo12:per_cpu_nodes_base
56 add x1, x1, x0, lsl #3
58 ldr x0, [x1]
61 ldr x1, =__PER_CPU_UNIT_SECTION_SIZE__
62 madd x0, x2, x1, x0
/rk3399_ARM-atf/plat/intel/soc/common/aarch64/
H A Dplat_helpers.S46 ldr x1, [x0]
53 br x1
90 and x1, x0, #MPIDR_CPU_MASK
93 add x0, x1, x0, LSR #8
95 add x0, x1, x0, LSR #6
133 mov_imm x1, PLAT_SEC_ENTRY
134 str xzr, [x1]
135 mrs x1, rmr_el3
136 orr x1, x1, #0x02
137 msr rmr_el3, x1
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_trampoline.S24 ldr x1, [x0]
28 cmp x1, x2
32 mov x1, #TEGRA194_STATE_SYSTEM_RESUME
33 lsl x1, x1, #16
35 add x1, x1, x2
36 str x1, [x0]
41 adr x1, __tegra194_cpu_reset_handler_end
49 ldp x3, x4, [x1], #16
56 ldrb w3, [x1], #1
113 adr x1, tegra194_cpu_reset_handler
[all …]
/rk3399_ARM-atf/plat/imx/common/
H A Dimx_sip_svc.c25 u_register_t x1, in imx_sip_handler() argument
35 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
46 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
50 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
53 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
56 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
60 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
62 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
67 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
69 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
[all …]
/rk3399_ARM-atf/plat/arm/css/common/aarch64/
H A Dcss_helpers.S40 ldr x1, [x0]
41 cbz x1, 1f
42 br x1
78 and x1, x0, #MPIDR_CPU_MASK
81 add x0, x1, x0, LSR #6
99 mov x1, #0xffffffff
100 cmp x0, x1
112 mov_imm x1, SCP_BOOT_CFG_ADDR
113 ldr x1, [x1]
114 ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
[all …]
/rk3399_ARM-atf/bl2u/aarch64/
H A Dbl2u_entrypoint.S21 mov x20, x1
45 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
47 orr x0, x0, x1
66 adr x1, __RW_END__
67 sub x1, x1, x0
78 adrp x1, __BSS_END__
79 add x1, x1, :lo12:__BSS_END__
80 sub x1, x1, x0
108 mov x1, x21
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/aarch64/
H A Dls1046a.S99 mov x1, #NXP_SCFG_ADDR
101 str w3, [x1, #SCFG_COREBCR_OFFSET]
105 mov x1, #NXP_DCFG_ADDR
106 ldr w2, [x1, #DCFG_BRR_OFFSET]
110 str w2, [x1, #DCFG_BRR_OFFSET]
135 ldr x1, =NXP_RCPM_ADDR
137 str w2, [x1, #RCPM_PCPH20CLRR_OFFSET]
182 mov x1, #NXP_DCFG_ADDR
185 ldr w1, [x1, #DCFG_COREDISR_OFFSET]
239 mrs x1, DAIF
[all …]
/rk3399_ARM-atf/lib/libc/aarch64/
H A Dmemset.S35 aligned:cbz x1, x1_zero
38 bfi x1, x1, #32, #32
45 stp x1, x1, [x3], #16 /* write 64 bytes in a loop */
50 stp x1, x1, [x3], #16 /* write 32 bytes */
51 stp x1, x1, [x3], #16
53 stp x1, x1, [x3], #16 /* write 16 bytes */
55 str x1, [x3], #8 /* write 8 bytes */
/rk3399_ARM-atf/lib/psci/aarch64/
H A Dpsci_helpers.S29 mrs x1, sctlr_el3
30 bic x1, x1, #SCTLR_C_BIT
31 msr sctlr_el3, x1
48 mov x1, sp
49 sub x1, x0, x1
60 sub x1, sp, x0
94 mov x1, sp
95 sub x1, x0, x1

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