| #
4301798d |
| 05-May-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "refactor_eip76_driver" into integration
* changes:
feat(marvell): add trng driver
revert(rambus-trng): remove ip-76 driver
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| #
6d5fad8d |
| 23-Apr-2025 |
Wilson Ding <dingwei@marvell.com> |
feat(marvell): add trng driver
Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.
This trivial driver provisions
feat(marvell): add trng driver
Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.
This trivial driver provisions a simple API to read the random numbers
from hardware. It allows the bootloader to get one 32-bit or 64-bit
random number via SMC call to support KASLR.
Change-Id: I1707a85512ca163b8c7ab1644ff0f7e2fcf57344
Signed-off-by: Wilson Ding <dingwei@marvell.com>
show more ...
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| #
8fd026ab |
| 23-Apr-2025 |
Wilson Ding <dingwei@marvell.com> |
revert(rambus-trng): remove ip-76 driver
The Rambus TRNG IP-76 driver was ported from Linux kernel (omap-rng.c),
which was initially licensed under GPL-2.0. In term of the license
violation, remove
revert(rambus-trng): remove ip-76 driver
The Rambus TRNG IP-76 driver was ported from Linux kernel (omap-rng.c),
which was initially licensed under GPL-2.0. In term of the license
violation, remove this driver and the related SMC call that originally
added by the following two commits:
commit 57660d9d7945 ("plat/marvell/armada/a8k: support HW RNG by SMC")
commit 6aa9f5d164e8 ("drivers/rambus: add TRNG-IP-76 driver")
Change-Id: Id8c99db2e51b49623b3b034106c989a46f690b60
Signed-off-by: Wilson Ding <dingwei@marvell.com>
show more ...
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| #
2939f68a |
| 20-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration
* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is pr
Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration
* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is present
plat/marvell: a8k: move efuse definitions to separate header
plat/marvell/armada: fix TRNG return SMC handling
drivers: marvell: comphy: add rx training on 10G port
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
plat: marvell: armada: a8k: Fix LD selector mask
plat/marvell/armada: allow builds without MSS support
drivers: marvell: misc-dfx: extend dfx whitelist
drivers: marvell: add support for secure read/write of dfx register-set
ddr_phy: use smc calls to access ddr phy registers
drivers: marvell: thermal: use dedicated function for thermal SiPs
drivers: marvell: add thermal sensor driver and expose it via SIP service
fix: plat: marvell: fix MSS loader for A8K family
show more ...
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| #
2e1dba44 |
| 02-Aug-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single
plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single SMC call.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
show more ...
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| #
550a06df |
| 24-Jun-2020 |
Alex Evraev <alexev@marvell.com> |
drivers: marvell: comphy: add rx training on 10G port
This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Ie
drivers: marvell: comphy: add rx training on 10G port
This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
show more ...
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| #
81c2a044 |
| 03-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In intr
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
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| #
b81444e8 |
| 25-Dec-2019 |
Alex Leibovich <alexl@marvell.com> |
ddr_phy: use smc calls to access ddr phy registers
Added smc calls support to access ddr phy registers.
Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@mar
ddr_phy: use smc calls to access ddr phy registers
Added smc calls support to access ddr phy registers.
Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20791
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
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| #
0cedca63 |
| 02-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name for thermal
SiP services.
Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25054
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
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| #
ad416958 |
| 18-Dec-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), acce
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
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| #
8909fa9b |
| 25-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mappin
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
include/drivers/marvell/mochi: add detection of secure mode
plat/marvell: fix SPD handling in dram port
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
drivers/marvell/mochi: add missing stream IDs configurations
plat/marvell/armada/a8k: support HW RNG by SMC
drivers/rambus: add TRNG-IP-76 driver
show more ...
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| #
57660d9d |
| 26-Jul-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR suppo
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR support.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
show more ...
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| #
9935047b |
| 17-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble:
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble: ap807: clean-up PLL configuration sequence
ddr: a80x0: add DDR 32-bit mode support
plat: marvell: mci: perform mci link tuning for all mci interfaces
plat: marvell: mci: use more meaningful name for mci link tuning
plat: marvell: a8k: remove wrong or unnecessary comments
plat: marvell: ap807: enable snoop filter for ap807
plat: marvell: ap807: update configuration space of each CP
plat: marvell: ap807: use correct address for MCIx4 register
plat: marvell: add support for PLL 2.2GHz mode
plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
marvell: armada: add extra level in marvell platform hierarchy
show more ...
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| #
a2847172 |
| 05-Nov-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.
Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
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